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469 lines
12 KiB
469 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* ci.h - common structures, functions, and macros of the ChipIdea driver |
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* |
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. |
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* |
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* Author: David Lopo |
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*/ |
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#ifndef __DRIVERS_USB_CHIPIDEA_CI_H |
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#define __DRIVERS_USB_CHIPIDEA_CI_H |
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#include <linux/list.h> |
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#include <linux/irqreturn.h> |
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#include <linux/usb.h> |
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#include <linux/usb/gadget.h> |
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#include <linux/usb/otg-fsm.h> |
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#include <linux/usb/otg.h> |
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#include <linux/usb/role.h> |
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#include <linux/ulpi/interface.h> |
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/****************************************************************************** |
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* DEFINE |
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*****************************************************************************/ |
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#define TD_PAGE_COUNT 5 |
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#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */ |
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#define ENDPT_MAX 32 |
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#define CI_MAX_BUF_SIZE (TD_PAGE_COUNT * CI_HDRC_PAGE_SIZE) |
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/****************************************************************************** |
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* REGISTERS |
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*****************************************************************************/ |
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/* Identification Registers */ |
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#define ID_ID 0x0 |
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#define ID_HWGENERAL 0x4 |
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#define ID_HWHOST 0x8 |
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#define ID_HWDEVICE 0xc |
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#define ID_HWTXBUF 0x10 |
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#define ID_HWRXBUF 0x14 |
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#define ID_SBUSCFG 0x90 |
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/* register indices */ |
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enum ci_hw_regs { |
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CAP_CAPLENGTH, |
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CAP_HCCPARAMS, |
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CAP_DCCPARAMS, |
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CAP_TESTMODE, |
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CAP_LAST = CAP_TESTMODE, |
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OP_USBCMD, |
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OP_USBSTS, |
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OP_USBINTR, |
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OP_DEVICEADDR, |
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OP_ENDPTLISTADDR, |
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OP_TTCTRL, |
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OP_BURSTSIZE, |
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OP_ULPI_VIEWPORT, |
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OP_PORTSC, |
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OP_DEVLC, |
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OP_OTGSC, |
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OP_USBMODE, |
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OP_ENDPTSETUPSTAT, |
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OP_ENDPTPRIME, |
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OP_ENDPTFLUSH, |
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OP_ENDPTSTAT, |
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OP_ENDPTCOMPLETE, |
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OP_ENDPTCTRL, |
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/* endptctrl1..15 follow */ |
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OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2, |
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}; |
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/****************************************************************************** |
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* STRUCTURES |
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*****************************************************************************/ |
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/** |
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* struct ci_hw_ep - endpoint representation |
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* @ep: endpoint structure for gadget drivers |
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* @dir: endpoint direction (TX/RX) |
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* @num: endpoint number |
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* @type: endpoint type |
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* @name: string description of the endpoint |
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* @qh: queue head for this endpoint |
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* @wedge: is the endpoint wedged |
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* @ci: pointer to the controller |
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* @lock: pointer to controller's spinlock |
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* @td_pool: pointer to controller's TD pool |
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*/ |
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struct ci_hw_ep { |
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struct usb_ep ep; |
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u8 dir; |
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u8 num; |
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u8 type; |
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char name[16]; |
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struct { |
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struct list_head queue; |
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struct ci_hw_qh *ptr; |
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dma_addr_t dma; |
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} qh; |
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int wedge; |
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/* global resources */ |
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struct ci_hdrc *ci; |
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spinlock_t *lock; |
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struct dma_pool *td_pool; |
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struct td_node *pending_td; |
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}; |
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enum ci_role { |
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CI_ROLE_HOST = 0, |
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CI_ROLE_GADGET, |
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CI_ROLE_END, |
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}; |
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enum ci_revision { |
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CI_REVISION_1X = 10, /* Revision 1.x */ |
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CI_REVISION_20 = 20, /* Revision 2.0 */ |
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CI_REVISION_21, /* Revision 2.1 */ |
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CI_REVISION_22, /* Revision 2.2 */ |
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CI_REVISION_23, /* Revision 2.3 */ |
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CI_REVISION_24, /* Revision 2.4 */ |
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CI_REVISION_25, /* Revision 2.5 */ |
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CI_REVISION_25_PLUS, /* Revision above than 2.5 */ |
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CI_REVISION_UNKNOWN = 99, /* Unknown Revision */ |
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}; |
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/** |
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* struct ci_role_driver - host/gadget role driver |
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* @start: start this role |
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* @stop: stop this role |
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* @irq: irq handler for this role |
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* @name: role name string (host/gadget) |
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*/ |
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struct ci_role_driver { |
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int (*start)(struct ci_hdrc *); |
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void (*stop)(struct ci_hdrc *); |
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irqreturn_t (*irq)(struct ci_hdrc *); |
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const char *name; |
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}; |
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/** |
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* struct hw_bank - hardware register mapping representation |
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* @lpm: set if the device is LPM capable |
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* @phys: physical address of the controller's registers |
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* @abs: absolute address of the beginning of register window |
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* @cap: capability registers |
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* @op: operational registers |
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* @size: size of the register window |
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* @regmap: register lookup table |
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*/ |
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struct hw_bank { |
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unsigned lpm; |
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resource_size_t phys; |
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void __iomem *abs; |
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void __iomem *cap; |
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void __iomem *op; |
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size_t size; |
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void __iomem *regmap[OP_LAST + 1]; |
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}; |
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/** |
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* struct ci_hdrc - chipidea device representation |
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* @dev: pointer to parent device |
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* @lock: access synchronization |
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* @hw_bank: hardware register mapping |
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* @irq: IRQ number |
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* @roles: array of supported roles for this controller |
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* @role: current role |
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* @is_otg: if the device is otg-capable |
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* @fsm: otg finite state machine |
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* @otg_fsm_hrtimer: hrtimer for otg fsm timers |
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* @hr_timeouts: time out list for active otg fsm timers |
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* @enabled_otg_timer_bits: bits of enabled otg timers |
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* @next_otg_timer: next nearest enabled timer to be expired |
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* @work: work for role changing |
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* @wq: workqueue thread |
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* @qh_pool: allocation pool for queue heads |
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* @td_pool: allocation pool for transfer descriptors |
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* @gadget: device side representation for peripheral controller |
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* @driver: gadget driver |
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* @resume_state: save the state of gadget suspend from |
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* @hw_ep_max: total number of endpoints supported by hardware |
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* @ci_hw_ep: array of endpoints |
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* @ep0_dir: ep0 direction |
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* @ep0out: pointer to ep0 OUT endpoint |
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* @ep0in: pointer to ep0 IN endpoint |
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* @status: ep0 status request |
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* @setaddr: if we should set the address on status completion |
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* @address: usb address received from the host |
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* @remote_wakeup: host-enabled remote wakeup |
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* @suspended: suspended by host |
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* @test_mode: the selected test mode |
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* @platdata: platform specific information supplied by parent device |
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* @vbus_active: is VBUS active |
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* @ulpi: pointer to ULPI device, if any |
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* @ulpi_ops: ULPI read/write ops for this device |
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* @phy: pointer to PHY, if any |
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* @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework |
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* @hcd: pointer to usb_hcd for ehci host driver |
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* @id_event: indicates there is an id event, and handled at ci_otg_work |
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* @b_sess_valid_event: indicates there is a vbus event, and handled |
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* at ci_otg_work |
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* @imx28_write_fix: Freescale imx28 needs swp instruction for writing |
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* @supports_runtime_pm: if runtime pm is supported |
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* @in_lpm: if the core in low power mode |
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* @wakeup_int: if wakeup interrupt occur |
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* @rev: The revision number for controller |
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*/ |
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struct ci_hdrc { |
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struct device *dev; |
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spinlock_t lock; |
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struct hw_bank hw_bank; |
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int irq; |
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struct ci_role_driver *roles[CI_ROLE_END]; |
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enum ci_role role; |
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bool is_otg; |
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struct usb_otg otg; |
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struct otg_fsm fsm; |
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struct hrtimer otg_fsm_hrtimer; |
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ktime_t hr_timeouts[NUM_OTG_FSM_TIMERS]; |
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unsigned enabled_otg_timer_bits; |
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enum otg_fsm_timer next_otg_timer; |
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struct usb_role_switch *role_switch; |
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struct work_struct work; |
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struct workqueue_struct *wq; |
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struct dma_pool *qh_pool; |
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struct dma_pool *td_pool; |
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struct usb_gadget gadget; |
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struct usb_gadget_driver *driver; |
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enum usb_device_state resume_state; |
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unsigned hw_ep_max; |
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struct ci_hw_ep ci_hw_ep[ENDPT_MAX]; |
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u32 ep0_dir; |
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struct ci_hw_ep *ep0out, *ep0in; |
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struct usb_request *status; |
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bool setaddr; |
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u8 address; |
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u8 remote_wakeup; |
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u8 suspended; |
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u8 test_mode; |
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struct ci_hdrc_platform_data *platdata; |
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int vbus_active; |
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struct ulpi *ulpi; |
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struct ulpi_ops ulpi_ops; |
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struct phy *phy; |
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/* old usb_phy interface */ |
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struct usb_phy *usb_phy; |
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struct usb_hcd *hcd; |
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bool id_event; |
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bool b_sess_valid_event; |
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bool imx28_write_fix; |
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bool supports_runtime_pm; |
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bool in_lpm; |
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bool wakeup_int; |
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enum ci_revision rev; |
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}; |
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static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) |
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{ |
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BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]); |
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return ci->roles[ci->role]; |
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} |
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static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) |
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{ |
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int ret; |
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if (role >= CI_ROLE_END) |
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return -EINVAL; |
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if (!ci->roles[role]) |
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return -ENXIO; |
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ret = ci->roles[role]->start(ci); |
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if (!ret) |
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ci->role = role; |
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return ret; |
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} |
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static inline void ci_role_stop(struct ci_hdrc *ci) |
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{ |
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enum ci_role role = ci->role; |
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if (role == CI_ROLE_END) |
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return; |
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ci->role = CI_ROLE_END; |
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ci->roles[role]->stop(ci); |
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} |
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static inline enum usb_role ci_role_to_usb_role(struct ci_hdrc *ci) |
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{ |
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if (ci->role == CI_ROLE_HOST) |
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return USB_ROLE_HOST; |
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else if (ci->role == CI_ROLE_GADGET && ci->vbus_active) |
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return USB_ROLE_DEVICE; |
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else |
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return USB_ROLE_NONE; |
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} |
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static inline enum ci_role usb_role_to_ci_role(enum usb_role role) |
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{ |
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if (role == USB_ROLE_HOST) |
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return CI_ROLE_HOST; |
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else if (role == USB_ROLE_DEVICE) |
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return CI_ROLE_GADGET; |
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else |
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return CI_ROLE_END; |
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} |
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/** |
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* hw_read_id_reg: reads from a identification register |
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* @ci: the controller |
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* @offset: offset from the beginning of identification registers region |
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* @mask: bitfield mask |
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* |
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* This function returns register contents |
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*/ |
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static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) |
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{ |
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return ioread32(ci->hw_bank.abs + offset) & mask; |
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} |
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/** |
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* hw_write_id_reg: writes to a identification register |
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* @ci: the controller |
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* @offset: offset from the beginning of identification registers region |
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* @mask: bitfield mask |
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* @data: new value |
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*/ |
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static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset, |
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u32 mask, u32 data) |
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{ |
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if (~mask) |
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data = (ioread32(ci->hw_bank.abs + offset) & ~mask) |
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| (data & mask); |
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iowrite32(data, ci->hw_bank.abs + offset); |
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} |
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/** |
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* hw_read: reads from a hw register |
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* @ci: the controller |
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* @reg: register index |
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* @mask: bitfield mask |
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* |
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* This function returns register contents |
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*/ |
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static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) |
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{ |
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return ioread32(ci->hw_bank.regmap[reg]) & mask; |
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} |
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#ifdef CONFIG_SOC_IMX28 |
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static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
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{ |
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__asm__ ("swp %0, %0, [%1]" : : "r"(val), "r"(addr)); |
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} |
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#else |
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static inline void imx28_ci_writel(u32 val, volatile void __iomem *addr) |
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{ |
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} |
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#endif |
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static inline void __hw_write(struct ci_hdrc *ci, u32 val, |
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void __iomem *addr) |
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{ |
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if (ci->imx28_write_fix) |
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imx28_ci_writel(val, addr); |
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else |
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iowrite32(val, addr); |
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} |
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/** |
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* hw_write: writes to a hw register |
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* @ci: the controller |
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* @reg: register index |
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* @mask: bitfield mask |
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* @data: new value |
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*/ |
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static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
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u32 mask, u32 data) |
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{ |
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if (~mask) |
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data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) |
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| (data & mask); |
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__hw_write(ci, data, ci->hw_bank.regmap[reg]); |
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} |
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/** |
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* hw_test_and_clear: tests & clears a hw register |
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* @ci: the controller |
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* @reg: register index |
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* @mask: bitfield mask |
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* |
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* This function returns register contents |
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*/ |
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static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, |
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u32 mask) |
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{ |
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u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; |
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__hw_write(ci, val, ci->hw_bank.regmap[reg]); |
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return val; |
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} |
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/** |
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* hw_test_and_write: tests & writes a hw register |
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* @ci: the controller |
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* @reg: register index |
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* @mask: bitfield mask |
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* @data: new value |
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* |
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* This function returns register contents |
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*/ |
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static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, |
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u32 mask, u32 data) |
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{ |
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u32 val = hw_read(ci, reg, ~0); |
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hw_write(ci, reg, mask, data); |
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return (val & mask) >> __ffs(mask); |
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} |
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/** |
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* ci_otg_is_fsm_mode: runtime check if otg controller |
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* is in otg fsm mode. |
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* |
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* @ci: chipidea device |
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*/ |
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static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci) |
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{ |
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#ifdef CONFIG_USB_OTG_FSM |
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struct usb_otg_caps *otg_caps = &ci->platdata->ci_otg_caps; |
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return ci->is_otg && ci->roles[CI_ROLE_HOST] && |
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ci->roles[CI_ROLE_GADGET] && (otg_caps->srp_support || |
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otg_caps->hnp_support || otg_caps->adp_support); |
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#else |
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return false; |
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#endif |
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} |
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int ci_ulpi_init(struct ci_hdrc *ci); |
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void ci_ulpi_exit(struct ci_hdrc *ci); |
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int ci_ulpi_resume(struct ci_hdrc *ci); |
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u32 hw_read_intr_enable(struct ci_hdrc *ci); |
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u32 hw_read_intr_status(struct ci_hdrc *ci); |
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int hw_device_reset(struct ci_hdrc *ci); |
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int hw_port_test_set(struct ci_hdrc *ci, u8 mode); |
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u8 hw_port_test_get(struct ci_hdrc *ci); |
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void hw_phymode_configure(struct ci_hdrc *ci); |
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void ci_platform_configure(struct ci_hdrc *ci); |
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void dbg_create_files(struct ci_hdrc *ci); |
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void dbg_remove_files(struct ci_hdrc *ci); |
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#endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
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