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542 lines
12 KiB
542 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for the serial port on the 21285 StrongArm-110 core logic chip. |
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* |
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* Based on drivers/char/serial.c |
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*/ |
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#include <linux/module.h> |
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#include <linux/tty.h> |
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#include <linux/ioport.h> |
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#include <linux/init.h> |
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#include <linux/console.h> |
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#include <linux/device.h> |
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#include <linux/tty_flip.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial.h> |
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#include <linux/io.h> |
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#include <asm/irq.h> |
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#include <asm/mach-types.h> |
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#include <asm/system_info.h> |
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#include <asm/hardware/dec21285.h> |
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#include <mach/hardware.h> |
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#define BAUD_BASE (mem_fclk_21285/64) |
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#define SERIAL_21285_NAME "ttyFB" |
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#define SERIAL_21285_MAJOR 204 |
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#define SERIAL_21285_MINOR 4 |
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#define RXSTAT_DUMMY_READ 0x80000000 |
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#define RXSTAT_FRAME (1 << 0) |
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#define RXSTAT_PARITY (1 << 1) |
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#define RXSTAT_OVERRUN (1 << 2) |
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#define RXSTAT_ANYERR (RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN) |
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#define H_UBRLCR_BREAK (1 << 0) |
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#define H_UBRLCR_PARENB (1 << 1) |
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#define H_UBRLCR_PAREVN (1 << 2) |
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#define H_UBRLCR_STOPB (1 << 3) |
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#define H_UBRLCR_FIFO (1 << 4) |
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static const char serial21285_name[] = "Footbridge UART"; |
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/* |
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* We only need 2 bits of data, so instead of creating a whole structure for |
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* this, use bits of the private_data pointer of the uart port structure. |
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*/ |
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#define tx_enabled_bit 0 |
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#define rx_enabled_bit 1 |
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static bool is_enabled(struct uart_port *port, int bit) |
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{ |
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unsigned long *private_data = (unsigned long *)&port->private_data; |
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if (test_bit(bit, private_data)) |
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return true; |
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return false; |
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} |
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static void enable(struct uart_port *port, int bit) |
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{ |
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unsigned long *private_data = (unsigned long *)&port->private_data; |
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set_bit(bit, private_data); |
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} |
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static void disable(struct uart_port *port, int bit) |
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{ |
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unsigned long *private_data = (unsigned long *)&port->private_data; |
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clear_bit(bit, private_data); |
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} |
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#define is_tx_enabled(port) is_enabled(port, tx_enabled_bit) |
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#define tx_enable(port) enable(port, tx_enabled_bit) |
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#define tx_disable(port) disable(port, tx_enabled_bit) |
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#define is_rx_enabled(port) is_enabled(port, rx_enabled_bit) |
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#define rx_enable(port) enable(port, rx_enabled_bit) |
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#define rx_disable(port) disable(port, rx_enabled_bit) |
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/* |
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* The documented expression for selecting the divisor is: |
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* BAUD_BASE / baud - 1 |
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* However, typically BAUD_BASE is not divisible by baud, so |
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* we want to select the divisor that gives us the minimum |
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* error. Therefore, we want: |
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* int(BAUD_BASE / baud - 0.5) -> |
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* int(BAUD_BASE / baud - (baud >> 1) / baud) -> |
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* int((BAUD_BASE - (baud >> 1)) / baud) |
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*/ |
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static void serial21285_stop_tx(struct uart_port *port) |
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{ |
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if (is_tx_enabled(port)) { |
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disable_irq_nosync(IRQ_CONTX); |
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tx_disable(port); |
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} |
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} |
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static void serial21285_start_tx(struct uart_port *port) |
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{ |
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if (!is_tx_enabled(port)) { |
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enable_irq(IRQ_CONTX); |
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tx_enable(port); |
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} |
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} |
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static void serial21285_stop_rx(struct uart_port *port) |
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{ |
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if (is_rx_enabled(port)) { |
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disable_irq_nosync(IRQ_CONRX); |
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rx_disable(port); |
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} |
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} |
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static irqreturn_t serial21285_rx_chars(int irq, void *dev_id) |
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{ |
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struct uart_port *port = dev_id; |
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unsigned int status, ch, flag, rxs, max_count = 256; |
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status = *CSR_UARTFLG; |
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while (!(status & 0x10) && max_count--) { |
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ch = *CSR_UARTDR; |
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flag = TTY_NORMAL; |
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port->icount.rx++; |
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rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ; |
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if (unlikely(rxs & RXSTAT_ANYERR)) { |
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if (rxs & RXSTAT_PARITY) |
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port->icount.parity++; |
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else if (rxs & RXSTAT_FRAME) |
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port->icount.frame++; |
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if (rxs & RXSTAT_OVERRUN) |
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port->icount.overrun++; |
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rxs &= port->read_status_mask; |
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if (rxs & RXSTAT_PARITY) |
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flag = TTY_PARITY; |
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else if (rxs & RXSTAT_FRAME) |
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flag = TTY_FRAME; |
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} |
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uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag); |
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status = *CSR_UARTFLG; |
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} |
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tty_flip_buffer_push(&port->state->port); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t serial21285_tx_chars(int irq, void *dev_id) |
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{ |
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struct uart_port *port = dev_id; |
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struct circ_buf *xmit = &port->state->xmit; |
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int count = 256; |
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if (port->x_char) { |
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*CSR_UARTDR = port->x_char; |
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port->icount.tx++; |
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port->x_char = 0; |
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goto out; |
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} |
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if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { |
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serial21285_stop_tx(port); |
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goto out; |
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} |
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do { |
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*CSR_UARTDR = xmit->buf[xmit->tail]; |
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
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port->icount.tx++; |
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if (uart_circ_empty(xmit)) |
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break; |
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} while (--count > 0 && !(*CSR_UARTFLG & 0x20)); |
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
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uart_write_wakeup(port); |
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if (uart_circ_empty(xmit)) |
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serial21285_stop_tx(port); |
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out: |
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return IRQ_HANDLED; |
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} |
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static unsigned int serial21285_tx_empty(struct uart_port *port) |
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{ |
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return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT; |
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} |
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/* no modem control lines */ |
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static unsigned int serial21285_get_mctrl(struct uart_port *port) |
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{ |
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return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
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} |
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static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl) |
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{ |
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} |
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static void serial21285_break_ctl(struct uart_port *port, int break_state) |
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{ |
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unsigned long flags; |
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unsigned int h_lcr; |
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spin_lock_irqsave(&port->lock, flags); |
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h_lcr = *CSR_H_UBRLCR; |
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if (break_state) |
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h_lcr |= H_UBRLCR_BREAK; |
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else |
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h_lcr &= ~H_UBRLCR_BREAK; |
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*CSR_H_UBRLCR = h_lcr; |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static int serial21285_startup(struct uart_port *port) |
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{ |
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int ret; |
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tx_enable(port); |
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rx_enable(port); |
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ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0, |
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serial21285_name, port); |
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if (ret == 0) { |
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ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0, |
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serial21285_name, port); |
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if (ret) |
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free_irq(IRQ_CONRX, port); |
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} |
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return ret; |
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} |
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static void serial21285_shutdown(struct uart_port *port) |
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{ |
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free_irq(IRQ_CONTX, port); |
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free_irq(IRQ_CONRX, port); |
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} |
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static void |
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serial21285_set_termios(struct uart_port *port, struct ktermios *termios, |
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struct ktermios *old) |
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{ |
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unsigned long flags; |
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unsigned int baud, quot, h_lcr, b; |
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/* |
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* We don't support modem control lines. |
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*/ |
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termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); |
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termios->c_cflag |= CLOCAL; |
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/* |
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* We don't support BREAK character recognition. |
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*/ |
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termios->c_iflag &= ~(IGNBRK | BRKINT); |
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/* |
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* Ask the core to calculate the divisor for us. |
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*/ |
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baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); |
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quot = uart_get_divisor(port, baud); |
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b = port->uartclk / (16 * quot); |
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tty_termios_encode_baud_rate(termios, b, b); |
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switch (termios->c_cflag & CSIZE) { |
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case CS5: |
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h_lcr = 0x00; |
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break; |
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case CS6: |
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h_lcr = 0x20; |
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break; |
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case CS7: |
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h_lcr = 0x40; |
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break; |
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default: /* CS8 */ |
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h_lcr = 0x60; |
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break; |
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} |
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if (termios->c_cflag & CSTOPB) |
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h_lcr |= H_UBRLCR_STOPB; |
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if (termios->c_cflag & PARENB) { |
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h_lcr |= H_UBRLCR_PARENB; |
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if (!(termios->c_cflag & PARODD)) |
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h_lcr |= H_UBRLCR_PAREVN; |
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} |
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if (port->fifosize) |
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h_lcr |= H_UBRLCR_FIFO; |
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spin_lock_irqsave(&port->lock, flags); |
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/* |
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* Update the per-port timeout. |
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*/ |
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uart_update_timeout(port, termios->c_cflag, baud); |
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/* |
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* Which character status flags are we interested in? |
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*/ |
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port->read_status_mask = RXSTAT_OVERRUN; |
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if (termios->c_iflag & INPCK) |
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port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; |
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/* |
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* Which character status flags should we ignore? |
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*/ |
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port->ignore_status_mask = 0; |
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if (termios->c_iflag & IGNPAR) |
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port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY; |
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if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) |
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port->ignore_status_mask |= RXSTAT_OVERRUN; |
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/* |
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* Ignore all characters if CREAD is not set. |
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*/ |
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if ((termios->c_cflag & CREAD) == 0) |
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port->ignore_status_mask |= RXSTAT_DUMMY_READ; |
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quot -= 1; |
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*CSR_UARTCON = 0; |
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*CSR_L_UBRLCR = quot & 0xff; |
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*CSR_M_UBRLCR = (quot >> 8) & 0x0f; |
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*CSR_H_UBRLCR = h_lcr; |
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*CSR_UARTCON = 1; |
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spin_unlock_irqrestore(&port->lock, flags); |
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} |
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static const char *serial21285_type(struct uart_port *port) |
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{ |
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return port->type == PORT_21285 ? "DC21285" : NULL; |
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} |
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static void serial21285_release_port(struct uart_port *port) |
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{ |
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release_mem_region(port->mapbase, 32); |
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} |
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static int serial21285_request_port(struct uart_port *port) |
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{ |
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return request_mem_region(port->mapbase, 32, serial21285_name) |
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!= NULL ? 0 : -EBUSY; |
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} |
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static void serial21285_config_port(struct uart_port *port, int flags) |
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{ |
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if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0) |
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port->type = PORT_21285; |
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} |
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/* |
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* verify the new serial_struct (for TIOCSSERIAL). |
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*/ |
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static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser) |
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{ |
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int ret = 0; |
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if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285) |
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ret = -EINVAL; |
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if (ser->irq <= 0) |
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ret = -EINVAL; |
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if (ser->baud_base != port->uartclk / 16) |
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ret = -EINVAL; |
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return ret; |
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} |
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static const struct uart_ops serial21285_ops = { |
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.tx_empty = serial21285_tx_empty, |
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.get_mctrl = serial21285_get_mctrl, |
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.set_mctrl = serial21285_set_mctrl, |
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.stop_tx = serial21285_stop_tx, |
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.start_tx = serial21285_start_tx, |
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.stop_rx = serial21285_stop_rx, |
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.break_ctl = serial21285_break_ctl, |
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.startup = serial21285_startup, |
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.shutdown = serial21285_shutdown, |
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.set_termios = serial21285_set_termios, |
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.type = serial21285_type, |
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.release_port = serial21285_release_port, |
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.request_port = serial21285_request_port, |
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.config_port = serial21285_config_port, |
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.verify_port = serial21285_verify_port, |
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}; |
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static struct uart_port serial21285_port = { |
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.mapbase = 0x42000160, |
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.iotype = UPIO_MEM, |
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.irq = 0, |
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.fifosize = 16, |
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.ops = &serial21285_ops, |
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.flags = UPF_BOOT_AUTOCONF, |
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}; |
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static void serial21285_setup_ports(void) |
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{ |
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serial21285_port.uartclk = mem_fclk_21285 / 4; |
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} |
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#ifdef CONFIG_SERIAL_21285_CONSOLE |
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static void serial21285_console_putchar(struct uart_port *port, int ch) |
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{ |
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while (*CSR_UARTFLG & 0x20) |
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barrier(); |
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*CSR_UARTDR = ch; |
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} |
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static void |
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serial21285_console_write(struct console *co, const char *s, |
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unsigned int count) |
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{ |
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uart_console_write(&serial21285_port, s, count, serial21285_console_putchar); |
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} |
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static void __init |
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serial21285_get_options(struct uart_port *port, int *baud, |
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int *parity, int *bits) |
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{ |
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if (*CSR_UARTCON == 1) { |
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unsigned int tmp; |
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tmp = *CSR_H_UBRLCR; |
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switch (tmp & 0x60) { |
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case 0x00: |
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*bits = 5; |
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break; |
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case 0x20: |
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*bits = 6; |
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break; |
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case 0x40: |
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*bits = 7; |
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break; |
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default: |
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case 0x60: |
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*bits = 8; |
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break; |
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} |
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if (tmp & H_UBRLCR_PARENB) { |
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*parity = 'o'; |
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if (tmp & H_UBRLCR_PAREVN) |
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*parity = 'e'; |
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} |
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tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8); |
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*baud = port->uartclk / (16 * (tmp + 1)); |
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} |
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} |
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static int __init serial21285_console_setup(struct console *co, char *options) |
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{ |
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struct uart_port *port = &serial21285_port; |
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int baud = 9600; |
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int bits = 8; |
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int parity = 'n'; |
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int flow = 'n'; |
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if (machine_is_personal_server()) |
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baud = 57600; |
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/* |
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* Check whether an invalid uart number has been specified, and |
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* if so, search for the first available port that does have |
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* console support. |
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*/ |
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if (options) |
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uart_parse_options(options, &baud, &parity, &bits, &flow); |
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else |
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serial21285_get_options(port, &baud, &parity, &bits); |
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return uart_set_options(port, co, baud, parity, bits, flow); |
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} |
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static struct uart_driver serial21285_reg; |
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static struct console serial21285_console = |
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{ |
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.name = SERIAL_21285_NAME, |
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.write = serial21285_console_write, |
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.device = uart_console_device, |
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.setup = serial21285_console_setup, |
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.flags = CON_PRINTBUFFER, |
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.index = -1, |
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.data = &serial21285_reg, |
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}; |
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static int __init rs285_console_init(void) |
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{ |
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serial21285_setup_ports(); |
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register_console(&serial21285_console); |
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return 0; |
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} |
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console_initcall(rs285_console_init); |
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#define SERIAL_21285_CONSOLE &serial21285_console |
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#else |
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#define SERIAL_21285_CONSOLE NULL |
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#endif |
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static struct uart_driver serial21285_reg = { |
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.owner = THIS_MODULE, |
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.driver_name = "ttyFB", |
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.dev_name = "ttyFB", |
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.major = SERIAL_21285_MAJOR, |
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.minor = SERIAL_21285_MINOR, |
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.nr = 1, |
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.cons = SERIAL_21285_CONSOLE, |
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}; |
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static int __init serial21285_init(void) |
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{ |
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int ret; |
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printk(KERN_INFO "Serial: 21285 driver\n"); |
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serial21285_setup_ports(); |
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ret = uart_register_driver(&serial21285_reg); |
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if (ret == 0) |
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uart_add_one_port(&serial21285_reg, &serial21285_port); |
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return ret; |
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} |
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static void __exit serial21285_exit(void) |
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{ |
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uart_remove_one_port(&serial21285_reg, &serial21285_port); |
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uart_unregister_driver(&serial21285_reg); |
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} |
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module_init(serial21285_init); |
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module_exit(serial21285_exit); |
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MODULE_LICENSE("GPL"); |
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MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver"); |
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MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
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