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880 lines
21 KiB
880 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for the Diolan DLN-2 USB-SPI adapter |
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* |
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* Copyright (c) 2014 Intel Corporation |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/mfd/dln2.h> |
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#include <linux/spi/spi.h> |
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#include <linux/pm_runtime.h> |
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#include <asm/unaligned.h> |
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#define DLN2_SPI_MODULE_ID 0x02 |
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#define DLN2_SPI_CMD(cmd) DLN2_CMD(cmd, DLN2_SPI_MODULE_ID) |
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/* SPI commands */ |
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#define DLN2_SPI_GET_PORT_COUNT DLN2_SPI_CMD(0x00) |
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#define DLN2_SPI_ENABLE DLN2_SPI_CMD(0x11) |
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#define DLN2_SPI_DISABLE DLN2_SPI_CMD(0x12) |
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#define DLN2_SPI_IS_ENABLED DLN2_SPI_CMD(0x13) |
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#define DLN2_SPI_SET_MODE DLN2_SPI_CMD(0x14) |
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#define DLN2_SPI_GET_MODE DLN2_SPI_CMD(0x15) |
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#define DLN2_SPI_SET_FRAME_SIZE DLN2_SPI_CMD(0x16) |
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#define DLN2_SPI_GET_FRAME_SIZE DLN2_SPI_CMD(0x17) |
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#define DLN2_SPI_SET_FREQUENCY DLN2_SPI_CMD(0x18) |
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#define DLN2_SPI_GET_FREQUENCY DLN2_SPI_CMD(0x19) |
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#define DLN2_SPI_READ_WRITE DLN2_SPI_CMD(0x1A) |
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#define DLN2_SPI_READ DLN2_SPI_CMD(0x1B) |
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#define DLN2_SPI_WRITE DLN2_SPI_CMD(0x1C) |
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#define DLN2_SPI_SET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x20) |
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#define DLN2_SPI_GET_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x21) |
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#define DLN2_SPI_SET_DELAY_AFTER_SS DLN2_SPI_CMD(0x22) |
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#define DLN2_SPI_GET_DELAY_AFTER_SS DLN2_SPI_CMD(0x23) |
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#define DLN2_SPI_SET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x24) |
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#define DLN2_SPI_GET_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x25) |
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#define DLN2_SPI_SET_SS DLN2_SPI_CMD(0x26) |
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#define DLN2_SPI_GET_SS DLN2_SPI_CMD(0x27) |
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#define DLN2_SPI_RELEASE_SS DLN2_SPI_CMD(0x28) |
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#define DLN2_SPI_SS_VARIABLE_ENABLE DLN2_SPI_CMD(0x2B) |
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#define DLN2_SPI_SS_VARIABLE_DISABLE DLN2_SPI_CMD(0x2C) |
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#define DLN2_SPI_SS_VARIABLE_IS_ENABLED DLN2_SPI_CMD(0x2D) |
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#define DLN2_SPI_SS_AAT_ENABLE DLN2_SPI_CMD(0x2E) |
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#define DLN2_SPI_SS_AAT_DISABLE DLN2_SPI_CMD(0x2F) |
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#define DLN2_SPI_SS_AAT_IS_ENABLED DLN2_SPI_CMD(0x30) |
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#define DLN2_SPI_SS_BETWEEN_FRAMES_ENABLE DLN2_SPI_CMD(0x31) |
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#define DLN2_SPI_SS_BETWEEN_FRAMES_DISABLE DLN2_SPI_CMD(0x32) |
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#define DLN2_SPI_SS_BETWEEN_FRAMES_IS_ENABLED DLN2_SPI_CMD(0x33) |
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#define DLN2_SPI_SET_CPHA DLN2_SPI_CMD(0x34) |
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#define DLN2_SPI_GET_CPHA DLN2_SPI_CMD(0x35) |
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#define DLN2_SPI_SET_CPOL DLN2_SPI_CMD(0x36) |
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#define DLN2_SPI_GET_CPOL DLN2_SPI_CMD(0x37) |
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#define DLN2_SPI_SS_MULTI_ENABLE DLN2_SPI_CMD(0x38) |
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#define DLN2_SPI_SS_MULTI_DISABLE DLN2_SPI_CMD(0x39) |
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#define DLN2_SPI_SS_MULTI_IS_ENABLED DLN2_SPI_CMD(0x3A) |
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#define DLN2_SPI_GET_SUPPORTED_MODES DLN2_SPI_CMD(0x40) |
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#define DLN2_SPI_GET_SUPPORTED_CPHA_VALUES DLN2_SPI_CMD(0x41) |
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#define DLN2_SPI_GET_SUPPORTED_CPOL_VALUES DLN2_SPI_CMD(0x42) |
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#define DLN2_SPI_GET_SUPPORTED_FRAME_SIZES DLN2_SPI_CMD(0x43) |
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#define DLN2_SPI_GET_SS_COUNT DLN2_SPI_CMD(0x44) |
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#define DLN2_SPI_GET_MIN_FREQUENCY DLN2_SPI_CMD(0x45) |
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#define DLN2_SPI_GET_MAX_FREQUENCY DLN2_SPI_CMD(0x46) |
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#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x47) |
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#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_SS DLN2_SPI_CMD(0x48) |
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#define DLN2_SPI_GET_MIN_DELAY_AFTER_SS DLN2_SPI_CMD(0x49) |
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#define DLN2_SPI_GET_MAX_DELAY_AFTER_SS DLN2_SPI_CMD(0x4A) |
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#define DLN2_SPI_GET_MIN_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4B) |
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#define DLN2_SPI_GET_MAX_DELAY_BETWEEN_FRAMES DLN2_SPI_CMD(0x4C) |
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#define DLN2_SPI_MAX_XFER_SIZE 256 |
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#define DLN2_SPI_BUF_SIZE (DLN2_SPI_MAX_XFER_SIZE + 16) |
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#define DLN2_SPI_ATTR_LEAVE_SS_LOW BIT(0) |
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#define DLN2_TRANSFERS_WAIT_COMPLETE 1 |
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#define DLN2_TRANSFERS_CANCEL 0 |
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#define DLN2_RPM_AUTOSUSPEND_TIMEOUT 2000 |
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struct dln2_spi { |
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struct platform_device *pdev; |
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struct spi_master *master; |
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u8 port; |
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/* |
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* This buffer will be used mainly for read/write operations. Since |
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* they're quite large, we cannot use the stack. Protection is not |
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* needed because all SPI communication is serialized by the SPI core. |
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*/ |
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void *buf; |
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u8 bpw; |
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u32 speed; |
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u16 mode; |
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u8 cs; |
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}; |
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/* |
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* Enable/Disable SPI module. The disable command will wait for transfers to |
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* complete first. |
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*/ |
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static int dln2_spi_enable(struct dln2_spi *dln2, bool enable) |
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{ |
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u16 cmd; |
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struct { |
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u8 port; |
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u8 wait_for_completion; |
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} tx; |
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unsigned len = sizeof(tx); |
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tx.port = dln2->port; |
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if (enable) { |
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cmd = DLN2_SPI_ENABLE; |
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len -= sizeof(tx.wait_for_completion); |
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} else { |
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tx.wait_for_completion = DLN2_TRANSFERS_WAIT_COMPLETE; |
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cmd = DLN2_SPI_DISABLE; |
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} |
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return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); |
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} |
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/* |
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* Select/unselect multiple CS lines. The selected lines will be automatically |
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* toggled LOW/HIGH by the board firmware during transfers, provided they're |
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* enabled first. |
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* |
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* Ex: cs_mask = 0x03 -> CS0 & CS1 will be selected and the next WR/RD operation |
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* will toggle the lines LOW/HIGH automatically. |
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*/ |
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static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask) |
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{ |
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struct { |
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u8 port; |
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u8 cs; |
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} tx; |
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tx.port = dln2->port; |
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/* |
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* According to Diolan docs, "a slave device can be selected by changing |
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* the corresponding bit value to 0". The rest must be set to 1. Hence |
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* the bitwise NOT in front. |
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*/ |
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tx.cs = ~cs_mask; |
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return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx)); |
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} |
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/* |
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* Select one CS line. The other lines will be un-selected. |
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*/ |
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static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs) |
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{ |
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return dln2_spi_cs_set(dln2, BIT(cs)); |
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} |
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/* |
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* Enable/disable CS lines for usage. The module has to be disabled first. |
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*/ |
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static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable) |
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{ |
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struct { |
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u8 port; |
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u8 cs; |
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} tx; |
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u16 cmd; |
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tx.port = dln2->port; |
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tx.cs = cs_mask; |
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cmd = enable ? DLN2_SPI_SS_MULTI_ENABLE : DLN2_SPI_SS_MULTI_DISABLE; |
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return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx)); |
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} |
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static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable) |
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{ |
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u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0); |
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return dln2_spi_cs_enable(dln2, cs_mask, enable); |
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} |
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static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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} tx; |
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struct { |
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__le16 cs_count; |
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} rx; |
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unsigned rx_len = sizeof(rx); |
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tx.port = dln2->port; |
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ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx), |
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&rx, &rx_len); |
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if (ret < 0) |
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return ret; |
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if (rx_len < sizeof(rx)) |
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return -EPROTO; |
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*cs_num = le16_to_cpu(rx.cs_count); |
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dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num); |
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return 0; |
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} |
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static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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} tx; |
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struct { |
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__le32 speed; |
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} rx; |
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unsigned rx_len = sizeof(rx); |
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tx.port = dln2->port; |
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ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len); |
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if (ret < 0) |
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return ret; |
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if (rx_len < sizeof(rx)) |
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return -EPROTO; |
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*freq = le32_to_cpu(rx.speed); |
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return 0; |
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} |
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/* |
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* Get bus min/max frequencies. |
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*/ |
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static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax) |
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{ |
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int ret; |
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ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin); |
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if (ret < 0) |
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return ret; |
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ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax); |
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if (ret < 0) |
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return ret; |
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dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n", |
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*fmin, *fmax); |
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return 0; |
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} |
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/* |
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* Set the bus speed. The module will automatically round down to the closest |
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* available frequency and returns it. The module has to be disabled first. |
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*/ |
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static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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__le32 speed; |
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} __packed tx; |
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struct { |
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__le32 speed; |
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} rx; |
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int rx_len = sizeof(rx); |
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tx.port = dln2->port; |
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tx.speed = cpu_to_le32(speed); |
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ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx), |
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&rx, &rx_len); |
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if (ret < 0) |
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return ret; |
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if (rx_len < sizeof(rx)) |
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return -EPROTO; |
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return 0; |
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} |
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/* |
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* Change CPOL & CPHA. The module has to be disabled first. |
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*/ |
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static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode) |
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{ |
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struct { |
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u8 port; |
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u8 mode; |
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} tx; |
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tx.port = dln2->port; |
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tx.mode = mode; |
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return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx)); |
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} |
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/* |
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* Change frame size. The module has to be disabled first. |
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*/ |
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static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw) |
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{ |
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struct { |
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u8 port; |
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u8 bpw; |
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} tx; |
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tx.port = dln2->port; |
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tx.bpw = bpw; |
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return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE, |
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&tx, sizeof(tx)); |
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} |
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static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2, |
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u32 *bpw_mask) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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} tx; |
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struct { |
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u8 count; |
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u8 frame_sizes[36]; |
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} *rx = dln2->buf; |
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unsigned rx_len = sizeof(*rx); |
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int i; |
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tx.port = dln2->port; |
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ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES, |
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&tx, sizeof(tx), rx, &rx_len); |
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if (ret < 0) |
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return ret; |
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if (rx_len < sizeof(*rx)) |
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return -EPROTO; |
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if (rx->count > ARRAY_SIZE(rx->frame_sizes)) |
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return -EPROTO; |
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*bpw_mask = 0; |
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for (i = 0; i < rx->count; i++) |
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*bpw_mask |= BIT(rx->frame_sizes[i] - 1); |
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dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask); |
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return 0; |
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} |
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/* |
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* Copy the data to DLN2 buffer and change the byte order to LE, requested by |
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* DLN2 module. SPI core makes sure that the data length is a multiple of word |
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* size. |
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*/ |
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static int dln2_spi_copy_to_buf(u8 *dln2_buf, const u8 *src, u16 len, u8 bpw) |
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{ |
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#ifdef __LITTLE_ENDIAN |
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memcpy(dln2_buf, src, len); |
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#else |
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if (bpw <= 8) { |
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memcpy(dln2_buf, src, len); |
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} else if (bpw <= 16) { |
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__le16 *d = (__le16 *)dln2_buf; |
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u16 *s = (u16 *)src; |
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len = len / 2; |
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while (len--) |
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*d++ = cpu_to_le16p(s++); |
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} else { |
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__le32 *d = (__le32 *)dln2_buf; |
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u32 *s = (u32 *)src; |
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len = len / 4; |
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while (len--) |
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*d++ = cpu_to_le32p(s++); |
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} |
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#endif |
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return 0; |
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} |
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/* |
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* Copy the data from DLN2 buffer and convert to CPU byte order since the DLN2 |
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* buffer is LE ordered. SPI core makes sure that the data length is a multiple |
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* of word size. The RX dln2_buf is 2 byte aligned so, for BE, we have to make |
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* sure we avoid unaligned accesses for 32 bit case. |
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*/ |
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static int dln2_spi_copy_from_buf(u8 *dest, const u8 *dln2_buf, u16 len, u8 bpw) |
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{ |
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#ifdef __LITTLE_ENDIAN |
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memcpy(dest, dln2_buf, len); |
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#else |
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if (bpw <= 8) { |
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memcpy(dest, dln2_buf, len); |
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} else if (bpw <= 16) { |
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u16 *d = (u16 *)dest; |
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__le16 *s = (__le16 *)dln2_buf; |
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len = len / 2; |
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while (len--) |
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*d++ = le16_to_cpup(s++); |
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} else { |
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u32 *d = (u32 *)dest; |
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__le32 *s = (__le32 *)dln2_buf; |
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len = len / 4; |
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while (len--) |
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*d++ = get_unaligned_le32(s++); |
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} |
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#endif |
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return 0; |
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} |
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/* |
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* Perform one write operation. |
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*/ |
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static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data, |
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u16 data_len, u8 attr) |
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{ |
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struct { |
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u8 port; |
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__le16 size; |
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u8 attr; |
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u8 buf[DLN2_SPI_MAX_XFER_SIZE]; |
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} __packed *tx = dln2->buf; |
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unsigned tx_len; |
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BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE); |
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if (data_len > DLN2_SPI_MAX_XFER_SIZE) |
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return -EINVAL; |
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tx->port = dln2->port; |
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tx->size = cpu_to_le16(data_len); |
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tx->attr = attr; |
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dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw); |
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tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; |
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return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len); |
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} |
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/* |
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* Perform one read operation. |
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*/ |
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static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data, |
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u16 data_len, u8 attr) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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__le16 size; |
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u8 attr; |
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} __packed tx; |
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struct { |
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__le16 size; |
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u8 buf[DLN2_SPI_MAX_XFER_SIZE]; |
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} __packed *rx = dln2->buf; |
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unsigned rx_len = sizeof(*rx); |
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BUILD_BUG_ON(sizeof(*rx) > DLN2_SPI_BUF_SIZE); |
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if (data_len > DLN2_SPI_MAX_XFER_SIZE) |
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return -EINVAL; |
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tx.port = dln2->port; |
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tx.size = cpu_to_le16(data_len); |
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tx.attr = attr; |
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ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx), |
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rx, &rx_len); |
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if (ret < 0) |
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return ret; |
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if (rx_len < sizeof(rx->size) + data_len) |
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return -EPROTO; |
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if (le16_to_cpu(rx->size) != data_len) |
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return -EPROTO; |
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dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw); |
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return 0; |
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} |
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/* |
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* Perform one write & read operation. |
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*/ |
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static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data, |
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u8 *rx_data, u16 data_len, u8 attr) |
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{ |
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int ret; |
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struct { |
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u8 port; |
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__le16 size; |
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u8 attr; |
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u8 buf[DLN2_SPI_MAX_XFER_SIZE]; |
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} __packed *tx; |
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struct { |
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__le16 size; |
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u8 buf[DLN2_SPI_MAX_XFER_SIZE]; |
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} __packed *rx; |
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unsigned tx_len, rx_len; |
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BUILD_BUG_ON(sizeof(*tx) > DLN2_SPI_BUF_SIZE || |
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sizeof(*rx) > DLN2_SPI_BUF_SIZE); |
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if (data_len > DLN2_SPI_MAX_XFER_SIZE) |
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return -EINVAL; |
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/* |
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* Since this is a pseudo full-duplex communication, we're perfectly |
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* safe to use the same buffer for both tx and rx. When DLN2 sends the |
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* response back, with the rx data, we don't need the tx buffer anymore. |
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*/ |
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tx = dln2->buf; |
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rx = dln2->buf; |
|
|
|
tx->port = dln2->port; |
|
tx->size = cpu_to_le16(data_len); |
|
tx->attr = attr; |
|
|
|
dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw); |
|
|
|
tx_len = sizeof(*tx) + data_len - DLN2_SPI_MAX_XFER_SIZE; |
|
rx_len = sizeof(*rx); |
|
|
|
ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len, |
|
rx, &rx_len); |
|
if (ret < 0) |
|
return ret; |
|
if (rx_len < sizeof(rx->size) + data_len) |
|
return -EPROTO; |
|
if (le16_to_cpu(rx->size) != data_len) |
|
return -EPROTO; |
|
|
|
dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw); |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Read/Write wrapper. It will automatically split an operation into multiple |
|
* single ones due to device buffer constraints. |
|
*/ |
|
static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data, |
|
u8 *rx_data, u16 data_len, u8 attr) { |
|
int ret; |
|
u16 len; |
|
u8 temp_attr; |
|
u16 remaining = data_len; |
|
u16 offset; |
|
|
|
do { |
|
if (remaining > DLN2_SPI_MAX_XFER_SIZE) { |
|
len = DLN2_SPI_MAX_XFER_SIZE; |
|
temp_attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; |
|
} else { |
|
len = remaining; |
|
temp_attr = attr; |
|
} |
|
|
|
offset = data_len - remaining; |
|
|
|
if (tx_data && rx_data) { |
|
ret = dln2_spi_read_write_one(dln2, |
|
tx_data + offset, |
|
rx_data + offset, |
|
len, temp_attr); |
|
} else if (tx_data) { |
|
ret = dln2_spi_write_one(dln2, |
|
tx_data + offset, |
|
len, temp_attr); |
|
} else if (rx_data) { |
|
ret = dln2_spi_read_one(dln2, |
|
rx_data + offset, |
|
len, temp_attr); |
|
} else { |
|
return -EINVAL; |
|
} |
|
|
|
if (ret < 0) |
|
return ret; |
|
|
|
remaining -= len; |
|
} while (remaining); |
|
|
|
return 0; |
|
} |
|
|
|
static int dln2_spi_prepare_message(struct spi_master *master, |
|
struct spi_message *message) |
|
{ |
|
int ret; |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
struct spi_device *spi = message->spi; |
|
|
|
if (dln2->cs != spi->chip_select) { |
|
ret = dln2_spi_cs_set_one(dln2, spi->chip_select); |
|
if (ret < 0) |
|
return ret; |
|
|
|
dln2->cs = spi->chip_select; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed, |
|
u8 bpw, u8 mode) |
|
{ |
|
int ret; |
|
bool bus_setup_change; |
|
|
|
bus_setup_change = dln2->speed != speed || dln2->mode != mode || |
|
dln2->bpw != bpw; |
|
|
|
if (!bus_setup_change) |
|
return 0; |
|
|
|
ret = dln2_spi_enable(dln2, false); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (dln2->speed != speed) { |
|
ret = dln2_spi_set_speed(dln2, speed); |
|
if (ret < 0) |
|
return ret; |
|
|
|
dln2->speed = speed; |
|
} |
|
|
|
if (dln2->mode != mode) { |
|
ret = dln2_spi_set_mode(dln2, mode & 0x3); |
|
if (ret < 0) |
|
return ret; |
|
|
|
dln2->mode = mode; |
|
} |
|
|
|
if (dln2->bpw != bpw) { |
|
ret = dln2_spi_set_bpw(dln2, bpw); |
|
if (ret < 0) |
|
return ret; |
|
|
|
dln2->bpw = bpw; |
|
} |
|
|
|
return dln2_spi_enable(dln2, true); |
|
} |
|
|
|
static int dln2_spi_transfer_one(struct spi_master *master, |
|
struct spi_device *spi, |
|
struct spi_transfer *xfer) |
|
{ |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
int status; |
|
u8 attr = 0; |
|
|
|
status = dln2_spi_transfer_setup(dln2, xfer->speed_hz, |
|
xfer->bits_per_word, |
|
spi->mode); |
|
if (status < 0) { |
|
dev_err(&dln2->pdev->dev, "Cannot setup transfer\n"); |
|
return status; |
|
} |
|
|
|
if (!xfer->cs_change && !spi_transfer_is_last(master, xfer)) |
|
attr = DLN2_SPI_ATTR_LEAVE_SS_LOW; |
|
|
|
status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf, |
|
xfer->len, attr); |
|
if (status < 0) |
|
dev_err(&dln2->pdev->dev, "write/read failed!\n"); |
|
|
|
return status; |
|
} |
|
|
|
static int dln2_spi_probe(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master; |
|
struct dln2_spi *dln2; |
|
struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev); |
|
struct device *dev = &pdev->dev; |
|
int ret; |
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*dln2)); |
|
if (!master) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, master); |
|
|
|
dln2 = spi_master_get_devdata(master); |
|
|
|
dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL); |
|
if (!dln2->buf) { |
|
ret = -ENOMEM; |
|
goto exit_free_master; |
|
} |
|
|
|
dln2->master = master; |
|
dln2->master->dev.of_node = dev->of_node; |
|
dln2->pdev = pdev; |
|
dln2->port = pdata->port; |
|
/* cs/mode can never be 0xff, so the first transfer will set them */ |
|
dln2->cs = 0xff; |
|
dln2->mode = 0xff; |
|
|
|
/* disable SPI module before continuing with the setup */ |
|
ret = dln2_spi_enable(dln2, false); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to disable SPI module\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to get number of CS pins\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
ret = dln2_spi_get_speed_range(dln2, |
|
&master->min_speed_hz, |
|
&master->max_speed_hz); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to read bus min/max freqs\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
ret = dln2_spi_get_supported_frame_sizes(dln2, |
|
&master->bits_per_word_mask); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to read supported frame sizes\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
ret = dln2_spi_cs_enable_all(dln2, true); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to enable CS pins\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
master->bus_num = -1; |
|
master->mode_bits = SPI_CPOL | SPI_CPHA; |
|
master->prepare_message = dln2_spi_prepare_message; |
|
master->transfer_one = dln2_spi_transfer_one; |
|
master->auto_runtime_pm = true; |
|
|
|
/* enable SPI module, we're good to go */ |
|
ret = dln2_spi_enable(dln2, true); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to enable SPI module\n"); |
|
goto exit_free_master; |
|
} |
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, |
|
DLN2_RPM_AUTOSUSPEND_TIMEOUT); |
|
pm_runtime_use_autosuspend(&pdev->dev); |
|
pm_runtime_set_active(&pdev->dev); |
|
pm_runtime_enable(&pdev->dev); |
|
|
|
ret = devm_spi_register_master(&pdev->dev, master); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "Failed to register master\n"); |
|
goto exit_register; |
|
} |
|
|
|
return ret; |
|
|
|
exit_register: |
|
pm_runtime_disable(&pdev->dev); |
|
pm_runtime_set_suspended(&pdev->dev); |
|
|
|
if (dln2_spi_enable(dln2, false) < 0) |
|
dev_err(&pdev->dev, "Failed to disable SPI module\n"); |
|
exit_free_master: |
|
spi_master_put(master); |
|
|
|
return ret; |
|
} |
|
|
|
static int dln2_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master = platform_get_drvdata(pdev); |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
|
|
pm_runtime_disable(&pdev->dev); |
|
|
|
if (dln2_spi_enable(dln2, false) < 0) |
|
dev_err(&pdev->dev, "Failed to disable SPI module\n"); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int dln2_spi_suspend(struct device *dev) |
|
{ |
|
int ret; |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
|
|
ret = spi_master_suspend(master); |
|
if (ret < 0) |
|
return ret; |
|
|
|
if (!pm_runtime_suspended(dev)) { |
|
ret = dln2_spi_enable(dln2, false); |
|
if (ret < 0) |
|
return ret; |
|
} |
|
|
|
/* |
|
* USB power may be cut off during sleep. Resetting the following |
|
* parameters will force the board to be set up before first transfer. |
|
*/ |
|
dln2->cs = 0xff; |
|
dln2->speed = 0; |
|
dln2->bpw = 0; |
|
dln2->mode = 0xff; |
|
|
|
return 0; |
|
} |
|
|
|
static int dln2_spi_resume(struct device *dev) |
|
{ |
|
int ret; |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
|
|
if (!pm_runtime_suspended(dev)) { |
|
ret = dln2_spi_cs_enable_all(dln2, true); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = dln2_spi_enable(dln2, true); |
|
if (ret < 0) |
|
return ret; |
|
} |
|
|
|
return spi_master_resume(master); |
|
} |
|
#endif /* CONFIG_PM_SLEEP */ |
|
|
|
#ifdef CONFIG_PM |
|
static int dln2_spi_runtime_suspend(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
|
|
return dln2_spi_enable(dln2, false); |
|
} |
|
|
|
static int dln2_spi_runtime_resume(struct device *dev) |
|
{ |
|
struct spi_master *master = dev_get_drvdata(dev); |
|
struct dln2_spi *dln2 = spi_master_get_devdata(master); |
|
|
|
return dln2_spi_enable(dln2, true); |
|
} |
|
#endif /* CONFIG_PM */ |
|
|
|
static const struct dev_pm_ops dln2_spi_pm = { |
|
SET_SYSTEM_SLEEP_PM_OPS(dln2_spi_suspend, dln2_spi_resume) |
|
SET_RUNTIME_PM_OPS(dln2_spi_runtime_suspend, |
|
dln2_spi_runtime_resume, NULL) |
|
}; |
|
|
|
static struct platform_driver spi_dln2_driver = { |
|
.driver = { |
|
.name = "dln2-spi", |
|
.pm = &dln2_spi_pm, |
|
}, |
|
.probe = dln2_spi_probe, |
|
.remove = dln2_spi_remove, |
|
}; |
|
module_platform_driver(spi_dln2_driver); |
|
|
|
MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface"); |
|
MODULE_AUTHOR("Laurentiu Palcu <[email protected]>"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_ALIAS("platform:dln2-spi");
|
|
|