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359 lines
9.4 KiB
359 lines
9.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
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* |
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* Authors: Shlomi Gridish <[email protected]> |
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* Li Yang <[email protected]> |
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* |
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* Description: |
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* QE UCC Slow API Set - UCC Slow specific routines implementations. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/slab.h> |
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#include <linux/stddef.h> |
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#include <linux/interrupt.h> |
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#include <linux/err.h> |
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#include <linux/export.h> |
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#include <asm/io.h> |
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#include <soc/fsl/qe/immap_qe.h> |
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#include <soc/fsl/qe/qe.h> |
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#include <soc/fsl/qe/ucc.h> |
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#include <soc/fsl/qe/ucc_slow.h> |
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u32 ucc_slow_get_qe_cr_subblock(int uccs_num) |
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{ |
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switch (uccs_num) { |
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case 0: return QE_CR_SUBBLOCK_UCCSLOW1; |
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case 1: return QE_CR_SUBBLOCK_UCCSLOW2; |
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case 2: return QE_CR_SUBBLOCK_UCCSLOW3; |
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case 3: return QE_CR_SUBBLOCK_UCCSLOW4; |
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case 4: return QE_CR_SUBBLOCK_UCCSLOW5; |
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case 5: return QE_CR_SUBBLOCK_UCCSLOW6; |
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case 6: return QE_CR_SUBBLOCK_UCCSLOW7; |
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case 7: return QE_CR_SUBBLOCK_UCCSLOW8; |
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default: return QE_CR_SUBBLOCK_INVALID; |
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} |
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} |
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EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock); |
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void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs) |
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{ |
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struct ucc_slow_info *us_info = uccs->us_info; |
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u32 id; |
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id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); |
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qe_issue_cmd(QE_GRACEFUL_STOP_TX, id, |
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QE_CR_PROTOCOL_UNSPECIFIED, 0); |
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} |
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EXPORT_SYMBOL(ucc_slow_graceful_stop_tx); |
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void ucc_slow_stop_tx(struct ucc_slow_private * uccs) |
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{ |
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struct ucc_slow_info *us_info = uccs->us_info; |
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u32 id; |
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id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); |
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qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); |
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} |
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EXPORT_SYMBOL(ucc_slow_stop_tx); |
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void ucc_slow_restart_tx(struct ucc_slow_private * uccs) |
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{ |
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struct ucc_slow_info *us_info = uccs->us_info; |
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u32 id; |
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id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); |
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qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); |
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} |
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EXPORT_SYMBOL(ucc_slow_restart_tx); |
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void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) |
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{ |
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struct ucc_slow __iomem *us_regs; |
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u32 gumr_l; |
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us_regs = uccs->us_regs; |
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/* Enable reception and/or transmission on this UCC. */ |
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gumr_l = ioread32be(&us_regs->gumr_l); |
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if (mode & COMM_DIR_TX) { |
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gumr_l |= UCC_SLOW_GUMR_L_ENT; |
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uccs->enabled_tx = 1; |
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} |
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if (mode & COMM_DIR_RX) { |
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gumr_l |= UCC_SLOW_GUMR_L_ENR; |
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uccs->enabled_rx = 1; |
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} |
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iowrite32be(gumr_l, &us_regs->gumr_l); |
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} |
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EXPORT_SYMBOL(ucc_slow_enable); |
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void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) |
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{ |
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struct ucc_slow __iomem *us_regs; |
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u32 gumr_l; |
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us_regs = uccs->us_regs; |
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/* Disable reception and/or transmission on this UCC. */ |
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gumr_l = ioread32be(&us_regs->gumr_l); |
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if (mode & COMM_DIR_TX) { |
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gumr_l &= ~UCC_SLOW_GUMR_L_ENT; |
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uccs->enabled_tx = 0; |
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} |
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if (mode & COMM_DIR_RX) { |
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gumr_l &= ~UCC_SLOW_GUMR_L_ENR; |
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uccs->enabled_rx = 0; |
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} |
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iowrite32be(gumr_l, &us_regs->gumr_l); |
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} |
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EXPORT_SYMBOL(ucc_slow_disable); |
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/* Initialize the UCC for Slow operations |
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* |
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* The caller should initialize the following us_info |
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*/ |
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int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret) |
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{ |
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struct ucc_slow_private *uccs; |
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u32 i; |
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struct ucc_slow __iomem *us_regs; |
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u32 gumr; |
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struct qe_bd __iomem *bd; |
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u32 id; |
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u32 command; |
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int ret = 0; |
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if (!us_info) |
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return -EINVAL; |
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/* check if the UCC port number is in range. */ |
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if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { |
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printk(KERN_ERR "%s: illegal UCC number\n", __func__); |
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return -EINVAL; |
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} |
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/* |
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* Set mrblr |
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* Check that 'max_rx_buf_length' is properly aligned (4), unless |
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* rfw is 1, meaning that QE accepts one byte at a time, unlike normal |
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* case when QE accepts 32 bits at a time. |
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*/ |
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if ((!us_info->rfw) && |
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(us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) { |
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printk(KERN_ERR "max_rx_buf_length not aligned.\n"); |
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return -EINVAL; |
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} |
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uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL); |
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if (!uccs) { |
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printk(KERN_ERR "%s: Cannot allocate private data\n", |
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__func__); |
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return -ENOMEM; |
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} |
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uccs->rx_base_offset = -1; |
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uccs->tx_base_offset = -1; |
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uccs->us_pram_offset = -1; |
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/* Fill slow UCC structure */ |
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uccs->us_info = us_info; |
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/* Set the PHY base address */ |
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uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); |
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if (uccs->us_regs == NULL) { |
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printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__); |
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kfree(uccs); |
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return -ENOMEM; |
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} |
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us_regs = uccs->us_regs; |
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uccs->p_ucce = &us_regs->ucce; |
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uccs->p_uccm = &us_regs->uccm; |
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/* Get PRAM base */ |
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uccs->us_pram_offset = |
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qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM); |
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if (uccs->us_pram_offset < 0) { |
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printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__); |
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ucc_slow_free(uccs); |
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return -ENOMEM; |
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} |
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id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); |
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qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol, |
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uccs->us_pram_offset); |
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uccs->us_pram = qe_muram_addr(uccs->us_pram_offset); |
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/* Set UCC to slow type */ |
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ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW); |
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if (ret) { |
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printk(KERN_ERR "%s: cannot set UCC type", __func__); |
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ucc_slow_free(uccs); |
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return ret; |
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} |
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iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr); |
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INIT_LIST_HEAD(&uccs->confQ); |
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/* Allocate BDs. */ |
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uccs->rx_base_offset = |
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qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), |
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QE_ALIGNMENT_OF_BD); |
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if (uccs->rx_base_offset < 0) { |
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printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__, |
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us_info->rx_bd_ring_len); |
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ucc_slow_free(uccs); |
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return -ENOMEM; |
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} |
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uccs->tx_base_offset = |
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qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd), |
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QE_ALIGNMENT_OF_BD); |
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if (uccs->tx_base_offset < 0) { |
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printk(KERN_ERR "%s: cannot allocate TX BDs", __func__); |
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ucc_slow_free(uccs); |
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return -ENOMEM; |
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} |
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/* Init Tx bds */ |
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bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset); |
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for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) { |
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/* clear bd buffer */ |
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iowrite32be(0, &bd->buf); |
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/* set bd status and length */ |
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iowrite32be(0, (u32 __iomem *)bd); |
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bd++; |
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} |
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/* for last BD set Wrap bit */ |
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iowrite32be(0, &bd->buf); |
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iowrite32be(T_W, (u32 __iomem *)bd); |
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/* Init Rx bds */ |
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bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset); |
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for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) { |
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/* set bd status and length */ |
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iowrite32be(0, (u32 __iomem *)bd); |
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/* clear bd buffer */ |
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iowrite32be(0, &bd->buf); |
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bd++; |
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} |
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/* for last BD set Wrap bit */ |
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iowrite32be(R_W, (u32 __iomem *)bd); |
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iowrite32be(0, &bd->buf); |
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/* Set GUMR (For more details see the hardware spec.). */ |
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/* gumr_h */ |
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gumr = us_info->tcrc; |
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if (us_info->cdp) |
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gumr |= UCC_SLOW_GUMR_H_CDP; |
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if (us_info->ctsp) |
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gumr |= UCC_SLOW_GUMR_H_CTSP; |
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if (us_info->cds) |
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gumr |= UCC_SLOW_GUMR_H_CDS; |
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if (us_info->ctss) |
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gumr |= UCC_SLOW_GUMR_H_CTSS; |
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if (us_info->tfl) |
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gumr |= UCC_SLOW_GUMR_H_TFL; |
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if (us_info->rfw) |
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gumr |= UCC_SLOW_GUMR_H_RFW; |
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if (us_info->txsy) |
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gumr |= UCC_SLOW_GUMR_H_TXSY; |
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if (us_info->rtsm) |
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gumr |= UCC_SLOW_GUMR_H_RTSM; |
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iowrite32be(gumr, &us_regs->gumr_h); |
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/* gumr_l */ |
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gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc | |
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(u32)us_info->renc | (u32)us_info->diag | (u32)us_info->mode; |
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if (us_info->tci) |
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gumr |= UCC_SLOW_GUMR_L_TCI; |
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if (us_info->rinv) |
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gumr |= UCC_SLOW_GUMR_L_RINV; |
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if (us_info->tinv) |
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gumr |= UCC_SLOW_GUMR_L_TINV; |
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if (us_info->tend) |
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gumr |= UCC_SLOW_GUMR_L_TEND; |
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iowrite32be(gumr, &us_regs->gumr_l); |
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/* Function code registers */ |
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/* if the data is in cachable memory, the 'global' */ |
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/* in the function code should be set. */ |
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iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr); |
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iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr); |
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/* rbase, tbase are offsets from MURAM base */ |
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iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase); |
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iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase); |
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/* Mux clocking */ |
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/* Grant Support */ |
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ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support); |
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/* Breakpoint Support */ |
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ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support); |
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/* Set Tsa or NMSI mode. */ |
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ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa); |
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/* If NMSI (not Tsa), set Tx and Rx clock. */ |
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if (!us_info->tsa) { |
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/* Rx clock routing */ |
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if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, |
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COMM_DIR_RX)) { |
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printk(KERN_ERR "%s: illegal value for RX clock\n", |
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__func__); |
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ucc_slow_free(uccs); |
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return -EINVAL; |
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} |
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/* Tx clock routing */ |
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if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, |
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COMM_DIR_TX)) { |
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printk(KERN_ERR "%s: illegal value for TX clock\n", |
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__func__); |
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ucc_slow_free(uccs); |
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return -EINVAL; |
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} |
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} |
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/* Set interrupt mask register at UCC level. */ |
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iowrite16be(us_info->uccm_mask, &us_regs->uccm); |
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/* First, clear anything pending at UCC level, |
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* otherwise, old garbage may come through |
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* as soon as the dam is opened. */ |
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/* Writing '1' clears */ |
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iowrite16be(0xffff, &us_regs->ucce); |
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/* Issue QE Init command */ |
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if (us_info->init_tx && us_info->init_rx) |
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command = QE_INIT_TX_RX; |
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else if (us_info->init_tx) |
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command = QE_INIT_TX; |
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else |
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command = QE_INIT_RX; /* We know at least one is TRUE */ |
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qe_issue_cmd(command, id, us_info->protocol, 0); |
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*uccs_ret = uccs; |
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return 0; |
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} |
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EXPORT_SYMBOL(ucc_slow_init); |
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void ucc_slow_free(struct ucc_slow_private * uccs) |
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{ |
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if (!uccs) |
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return; |
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qe_muram_free(uccs->rx_base_offset); |
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qe_muram_free(uccs->tx_base_offset); |
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qe_muram_free(uccs->us_pram_offset); |
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if (uccs->us_regs) |
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iounmap(uccs->us_regs); |
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kfree(uccs); |
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} |
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EXPORT_SYMBOL(ucc_slow_free); |
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