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455 lines
11 KiB
455 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Dove PMU support |
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*/ |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_domain.h> |
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#include <linux/reset.h> |
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#include <linux/reset-controller.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <linux/soc/dove/pmu.h> |
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#include <linux/spinlock.h> |
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#define NR_PMU_IRQS 7 |
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#define PMC_SW_RST 0x30 |
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#define PMC_IRQ_CAUSE 0x50 |
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#define PMC_IRQ_MASK 0x54 |
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#define PMU_PWR 0x10 |
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#define PMU_ISO 0x58 |
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struct pmu_data { |
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spinlock_t lock; |
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struct device_node *of_node; |
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void __iomem *pmc_base; |
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void __iomem *pmu_base; |
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struct irq_chip_generic *irq_gc; |
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struct irq_domain *irq_domain; |
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#ifdef CONFIG_RESET_CONTROLLER |
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struct reset_controller_dev reset; |
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#endif |
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}; |
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/* |
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* The PMU contains a register to reset various subsystems within the |
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* SoC. Export this as a reset controller. |
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*/ |
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#ifdef CONFIG_RESET_CONTROLLER |
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#define rcdev_to_pmu(rcdev) container_of(rcdev, struct pmu_data, reset) |
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static int pmu_reset_reset(struct reset_controller_dev *rc, unsigned long id) |
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{ |
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struct pmu_data *pmu = rcdev_to_pmu(rc); |
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unsigned long flags; |
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u32 val; |
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spin_lock_irqsave(&pmu->lock, flags); |
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val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); |
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writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); |
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writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); |
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spin_unlock_irqrestore(&pmu->lock, flags); |
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return 0; |
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} |
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static int pmu_reset_assert(struct reset_controller_dev *rc, unsigned long id) |
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{ |
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struct pmu_data *pmu = rcdev_to_pmu(rc); |
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unsigned long flags; |
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u32 val = ~BIT(id); |
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spin_lock_irqsave(&pmu->lock, flags); |
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val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST); |
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writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); |
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spin_unlock_irqrestore(&pmu->lock, flags); |
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return 0; |
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} |
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static int pmu_reset_deassert(struct reset_controller_dev *rc, unsigned long id) |
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{ |
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struct pmu_data *pmu = rcdev_to_pmu(rc); |
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unsigned long flags; |
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u32 val = BIT(id); |
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spin_lock_irqsave(&pmu->lock, flags); |
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val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST); |
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writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); |
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spin_unlock_irqrestore(&pmu->lock, flags); |
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return 0; |
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} |
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static const struct reset_control_ops pmu_reset_ops = { |
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.reset = pmu_reset_reset, |
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.assert = pmu_reset_assert, |
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.deassert = pmu_reset_deassert, |
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}; |
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static struct reset_controller_dev pmu_reset __initdata = { |
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.ops = &pmu_reset_ops, |
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.owner = THIS_MODULE, |
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.nr_resets = 32, |
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}; |
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static void __init pmu_reset_init(struct pmu_data *pmu) |
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{ |
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int ret; |
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pmu->reset = pmu_reset; |
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pmu->reset.of_node = pmu->of_node; |
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ret = reset_controller_register(&pmu->reset); |
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if (ret) |
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pr_err("pmu: %s failed: %d\n", "reset_controller_register", ret); |
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} |
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#else |
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static void __init pmu_reset_init(struct pmu_data *pmu) |
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{ |
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} |
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#endif |
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struct pmu_domain { |
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struct pmu_data *pmu; |
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u32 pwr_mask; |
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u32 rst_mask; |
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u32 iso_mask; |
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struct generic_pm_domain base; |
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}; |
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#define to_pmu_domain(dom) container_of(dom, struct pmu_domain, base) |
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/* |
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* This deals with the "old" Marvell sequence of bringing a power domain |
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* down/up, which is: apply power, release reset, disable isolators. |
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* |
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* Later devices apparantly use a different sequence: power up, disable |
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* isolators, assert repair signal, enable SRMA clock, enable AXI clock, |
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* enable module clock, deassert reset. |
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* |
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* Note: reading the assembly, it seems that the IO accessors have an |
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* unfortunate side-effect - they cause memory already read into registers |
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* for the if () to be re-read for the bit-set or bit-clear operation. |
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* The code is written to avoid this. |
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*/ |
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static int pmu_domain_power_off(struct generic_pm_domain *domain) |
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{ |
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struct pmu_domain *pmu_dom = to_pmu_domain(domain); |
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struct pmu_data *pmu = pmu_dom->pmu; |
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unsigned long flags; |
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unsigned int val; |
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void __iomem *pmu_base = pmu->pmu_base; |
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void __iomem *pmc_base = pmu->pmc_base; |
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spin_lock_irqsave(&pmu->lock, flags); |
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/* Enable isolators */ |
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if (pmu_dom->iso_mask) { |
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val = ~pmu_dom->iso_mask; |
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val &= readl_relaxed(pmu_base + PMU_ISO); |
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writel_relaxed(val, pmu_base + PMU_ISO); |
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} |
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/* Reset unit */ |
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if (pmu_dom->rst_mask) { |
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val = ~pmu_dom->rst_mask; |
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val &= readl_relaxed(pmc_base + PMC_SW_RST); |
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writel_relaxed(val, pmc_base + PMC_SW_RST); |
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} |
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/* Power down */ |
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val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask; |
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writel_relaxed(val, pmu_base + PMU_PWR); |
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spin_unlock_irqrestore(&pmu->lock, flags); |
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return 0; |
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} |
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static int pmu_domain_power_on(struct generic_pm_domain *domain) |
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{ |
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struct pmu_domain *pmu_dom = to_pmu_domain(domain); |
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struct pmu_data *pmu = pmu_dom->pmu; |
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unsigned long flags; |
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unsigned int val; |
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void __iomem *pmu_base = pmu->pmu_base; |
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void __iomem *pmc_base = pmu->pmc_base; |
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spin_lock_irqsave(&pmu->lock, flags); |
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/* Power on */ |
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val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR); |
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writel_relaxed(val, pmu_base + PMU_PWR); |
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/* Release reset */ |
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if (pmu_dom->rst_mask) { |
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val = pmu_dom->rst_mask; |
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val |= readl_relaxed(pmc_base + PMC_SW_RST); |
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writel_relaxed(val, pmc_base + PMC_SW_RST); |
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} |
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/* Disable isolators */ |
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if (pmu_dom->iso_mask) { |
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val = pmu_dom->iso_mask; |
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val |= readl_relaxed(pmu_base + PMU_ISO); |
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writel_relaxed(val, pmu_base + PMU_ISO); |
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} |
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spin_unlock_irqrestore(&pmu->lock, flags); |
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return 0; |
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} |
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static void __pmu_domain_register(struct pmu_domain *domain, |
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struct device_node *np) |
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{ |
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unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR); |
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domain->base.power_off = pmu_domain_power_off; |
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domain->base.power_on = pmu_domain_power_on; |
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pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask)); |
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if (np) |
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of_genpd_add_provider_simple(np, &domain->base); |
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} |
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/* PMU IRQ controller */ |
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static void pmu_irq_handler(struct irq_desc *desc) |
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{ |
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struct pmu_data *pmu = irq_desc_get_handler_data(desc); |
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struct irq_chip_generic *gc = pmu->irq_gc; |
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struct irq_domain *domain = pmu->irq_domain; |
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void __iomem *base = gc->reg_base; |
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u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache; |
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u32 done = ~0; |
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if (stat == 0) { |
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handle_bad_irq(desc); |
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return; |
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} |
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while (stat) { |
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u32 hwirq = fls(stat) - 1; |
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stat &= ~(1 << hwirq); |
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done &= ~(1 << hwirq); |
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generic_handle_irq(irq_find_mapping(domain, hwirq)); |
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} |
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/* |
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* The PMU mask register is not RW0C: it is RW. This means that |
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* the bits take whatever value is written to them; if you write |
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* a '1', you will set the interrupt. |
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* |
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* Unfortunately this means there is NO race free way to clear |
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* these interrupts. |
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* |
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* So, let's structure the code so that the window is as small as |
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* possible. |
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*/ |
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irq_gc_lock(gc); |
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done &= readl_relaxed(base + PMC_IRQ_CAUSE); |
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writel_relaxed(done, base + PMC_IRQ_CAUSE); |
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irq_gc_unlock(gc); |
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} |
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static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq) |
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{ |
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const char *name = "pmu_irq"; |
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struct irq_chip_generic *gc; |
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struct irq_domain *domain; |
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int ret; |
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/* mask and clear all interrupts */ |
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writel(0, pmu->pmc_base + PMC_IRQ_MASK); |
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writel(0, pmu->pmc_base + PMC_IRQ_CAUSE); |
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domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS, |
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&irq_generic_chip_ops, NULL); |
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if (!domain) { |
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pr_err("%s: unable to add irq domain\n", name); |
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return -ENOMEM; |
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} |
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ret = irq_alloc_domain_generic_chips(domain, NR_PMU_IRQS, 1, name, |
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handle_level_irq, |
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IRQ_NOREQUEST | IRQ_NOPROBE, 0, |
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IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_err("%s: unable to alloc irq domain gc: %d\n", name, ret); |
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irq_domain_remove(domain); |
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return ret; |
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} |
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gc = irq_get_domain_generic_chip(domain, 0); |
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gc->reg_base = pmu->pmc_base; |
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gc->chip_types[0].regs.mask = PMC_IRQ_MASK; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; |
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pmu->irq_domain = domain; |
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pmu->irq_gc = gc; |
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irq_set_handler_data(irq, pmu); |
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irq_set_chained_handler(irq, pmu_irq_handler); |
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return 0; |
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} |
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int __init dove_init_pmu_legacy(const struct dove_pmu_initdata *initdata) |
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{ |
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const struct dove_pmu_domain_initdata *domain_initdata; |
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struct pmu_data *pmu; |
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int ret; |
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pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); |
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if (!pmu) |
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return -ENOMEM; |
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spin_lock_init(&pmu->lock); |
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pmu->pmc_base = initdata->pmc_base; |
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pmu->pmu_base = initdata->pmu_base; |
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pmu_reset_init(pmu); |
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for (domain_initdata = initdata->domains; domain_initdata->name; |
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domain_initdata++) { |
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struct pmu_domain *domain; |
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domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
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if (domain) { |
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domain->pmu = pmu; |
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domain->pwr_mask = domain_initdata->pwr_mask; |
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domain->rst_mask = domain_initdata->rst_mask; |
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domain->iso_mask = domain_initdata->iso_mask; |
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domain->base.name = domain_initdata->name; |
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__pmu_domain_register(domain, NULL); |
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} |
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} |
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ret = dove_init_pmu_irq(pmu, initdata->irq); |
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if (ret) |
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pr_err("dove_init_pmu_irq() failed: %d\n", ret); |
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if (pmu->irq_domain) |
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irq_domain_associate_many(pmu->irq_domain, |
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initdata->irq_domain_start, |
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0, NR_PMU_IRQS); |
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return 0; |
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} |
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/* |
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* pmu: power-manager@d0000 { |
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* compatible = "marvell,dove-pmu"; |
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* reg = <0xd0000 0x8000> <0xd8000 0x8000>; |
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* interrupts = <33>; |
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* interrupt-controller; |
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* #reset-cells = 1; |
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* vpu_domain: vpu-domain { |
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* #power-domain-cells = <0>; |
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* marvell,pmu_pwr_mask = <0x00000008>; |
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* marvell,pmu_iso_mask = <0x00000001>; |
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* resets = <&pmu 16>; |
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* }; |
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* gpu_domain: gpu-domain { |
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* #power-domain-cells = <0>; |
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* marvell,pmu_pwr_mask = <0x00000004>; |
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* marvell,pmu_iso_mask = <0x00000002>; |
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* resets = <&pmu 18>; |
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* }; |
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* }; |
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*/ |
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int __init dove_init_pmu(void) |
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{ |
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struct device_node *np_pmu, *domains_node, *np; |
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struct pmu_data *pmu; |
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int ret, parent_irq; |
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/* Lookup the PMU node */ |
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np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu"); |
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if (!np_pmu) |
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return 0; |
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domains_node = of_get_child_by_name(np_pmu, "domains"); |
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if (!domains_node) { |
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pr_err("%pOFn: failed to find domains sub-node\n", np_pmu); |
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return 0; |
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} |
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pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); |
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if (!pmu) |
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return -ENOMEM; |
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spin_lock_init(&pmu->lock); |
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pmu->of_node = np_pmu; |
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pmu->pmc_base = of_iomap(pmu->of_node, 0); |
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pmu->pmu_base = of_iomap(pmu->of_node, 1); |
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if (!pmu->pmc_base || !pmu->pmu_base) { |
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pr_err("%pOFn: failed to map PMU\n", np_pmu); |
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iounmap(pmu->pmu_base); |
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iounmap(pmu->pmc_base); |
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kfree(pmu); |
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return -ENOMEM; |
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} |
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pmu_reset_init(pmu); |
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for_each_available_child_of_node(domains_node, np) { |
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struct of_phandle_args args; |
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struct pmu_domain *domain; |
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domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
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if (!domain) |
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break; |
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domain->pmu = pmu; |
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domain->base.name = kasprintf(GFP_KERNEL, "%pOFn", np); |
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if (!domain->base.name) { |
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kfree(domain); |
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break; |
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} |
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of_property_read_u32(np, "marvell,pmu_pwr_mask", |
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&domain->pwr_mask); |
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of_property_read_u32(np, "marvell,pmu_iso_mask", |
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&domain->iso_mask); |
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/* |
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* We parse the reset controller property directly here |
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* to ensure that we can operate when the reset controller |
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* support is not configured into the kernel. |
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*/ |
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ret = of_parse_phandle_with_args(np, "resets", "#reset-cells", |
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0, &args); |
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if (ret == 0) { |
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if (args.np == pmu->of_node) |
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domain->rst_mask = BIT(args.args[0]); |
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of_node_put(args.np); |
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} |
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__pmu_domain_register(domain, np); |
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} |
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/* Loss of the interrupt controller is not a fatal error. */ |
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parent_irq = irq_of_parse_and_map(pmu->of_node, 0); |
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if (!parent_irq) { |
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pr_err("%pOFn: no interrupt specified\n", np_pmu); |
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} else { |
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ret = dove_init_pmu_irq(pmu, parent_irq); |
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if (ret) |
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pr_err("dove_init_pmu_irq() failed: %d\n", ret); |
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} |
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return 0; |
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}
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