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512 lines
14 KiB
512 lines
14 KiB
/* |
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* This file is part of the Chelsio FCoE driver for Linux. |
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* |
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* Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the |
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* OpenIB.org BSD license below: |
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* |
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* Redistribution and use in source and binary forms, with or |
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* without modification, are permitted provided that the following |
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* conditions are met: |
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* |
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* - Redistributions of source code must retain the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer. |
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* |
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* - Redistributions in binary form must reproduce the above |
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* copyright notice, this list of conditions and the following |
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* disclaimer in the documentation and/or other materials |
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* provided with the distribution. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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* SOFTWARE. |
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*/ |
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#ifndef __CSIO_WR_H__ |
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#define __CSIO_WR_H__ |
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#include <linux/cache.h> |
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#include "csio_defs.h" |
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#include "t4fw_api.h" |
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#include "t4fw_api_stor.h" |
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/* |
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* SGE register field values. |
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*/ |
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#define X_INGPCIEBOUNDARY_32B 0 |
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#define X_INGPCIEBOUNDARY_64B 1 |
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#define X_INGPCIEBOUNDARY_128B 2 |
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#define X_INGPCIEBOUNDARY_256B 3 |
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#define X_INGPCIEBOUNDARY_512B 4 |
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#define X_INGPCIEBOUNDARY_1024B 5 |
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#define X_INGPCIEBOUNDARY_2048B 6 |
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#define X_INGPCIEBOUNDARY_4096B 7 |
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/* GTS register */ |
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#define X_TIMERREG_COUNTER0 0 |
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#define X_TIMERREG_COUNTER1 1 |
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#define X_TIMERREG_COUNTER2 2 |
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#define X_TIMERREG_COUNTER3 3 |
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#define X_TIMERREG_COUNTER4 4 |
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#define X_TIMERREG_COUNTER5 5 |
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#define X_TIMERREG_RESTART_COUNTER 6 |
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#define X_TIMERREG_UPDATE_CIDX 7 |
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/* |
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* Egress Context field values |
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*/ |
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#define X_FETCHBURSTMIN_16B 0 |
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#define X_FETCHBURSTMIN_32B 1 |
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#define X_FETCHBURSTMIN_64B 2 |
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#define X_FETCHBURSTMIN_128B 3 |
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#define X_FETCHBURSTMAX_64B 0 |
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#define X_FETCHBURSTMAX_128B 1 |
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#define X_FETCHBURSTMAX_256B 2 |
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#define X_FETCHBURSTMAX_512B 3 |
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#define X_HOSTFCMODE_NONE 0 |
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#define X_HOSTFCMODE_INGRESS_QUEUE 1 |
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#define X_HOSTFCMODE_STATUS_PAGE 2 |
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#define X_HOSTFCMODE_BOTH 3 |
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/* |
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* Ingress Context field values |
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*/ |
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#define X_UPDATESCHEDULING_TIMER 0 |
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#define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 |
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#define X_UPDATEDELIVERY_NONE 0 |
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#define X_UPDATEDELIVERY_INTERRUPT 1 |
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#define X_UPDATEDELIVERY_STATUS_PAGE 2 |
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#define X_UPDATEDELIVERY_BOTH 3 |
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#define X_INTERRUPTDESTINATION_PCIE 0 |
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#define X_INTERRUPTDESTINATION_IQ 1 |
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#define X_RSPD_TYPE_FLBUF 0 |
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#define X_RSPD_TYPE_CPL 1 |
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#define X_RSPD_TYPE_INTR 2 |
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/* WR status is at the same position as retval in a CMD header */ |
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#define csio_wr_status(_wr) \ |
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(FW_CMD_RETVAL_G(ntohl(((struct fw_cmd_hdr *)(_wr))->lo))) |
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struct csio_hw; |
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extern int csio_intr_coalesce_cnt; |
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extern int csio_intr_coalesce_time; |
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/* Ingress queue params */ |
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struct csio_iq_params { |
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uint8_t iq_start:1; |
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uint8_t iq_stop:1; |
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uint8_t pfn:3; |
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uint8_t vfn; |
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uint16_t physiqid; |
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uint16_t iqid; |
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uint16_t fl0id; |
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uint16_t fl1id; |
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uint8_t viid; |
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uint8_t type; |
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uint8_t iqasynch; |
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uint8_t reserved4; |
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uint8_t iqandst; |
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uint8_t iqanus; |
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uint8_t iqanud; |
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uint16_t iqandstindex; |
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uint8_t iqdroprss; |
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uint8_t iqpciech; |
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uint8_t iqdcaen; |
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uint8_t iqdcacpu; |
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uint8_t iqintcntthresh; |
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uint8_t iqo; |
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uint8_t iqcprio; |
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uint8_t iqesize; |
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uint16_t iqsize; |
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uint64_t iqaddr; |
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uint8_t iqflintiqhsen; |
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uint8_t reserved5; |
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uint8_t iqflintcongen; |
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uint8_t iqflintcngchmap; |
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uint32_t reserved6; |
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uint8_t fl0hostfcmode; |
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uint8_t fl0cprio; |
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uint8_t fl0paden; |
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uint8_t fl0packen; |
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uint8_t fl0congen; |
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uint8_t fl0dcaen; |
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uint8_t fl0dcacpu; |
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uint8_t fl0fbmin; |
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uint8_t fl0fbmax; |
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uint8_t fl0cidxfthresho; |
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uint8_t fl0cidxfthresh; |
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uint16_t fl0size; |
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uint64_t fl0addr; |
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uint64_t reserved7; |
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uint8_t fl1hostfcmode; |
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uint8_t fl1cprio; |
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uint8_t fl1paden; |
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uint8_t fl1packen; |
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uint8_t fl1congen; |
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uint8_t fl1dcaen; |
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uint8_t fl1dcacpu; |
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uint8_t fl1fbmin; |
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uint8_t fl1fbmax; |
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uint8_t fl1cidxfthresho; |
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uint8_t fl1cidxfthresh; |
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uint16_t fl1size; |
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uint64_t fl1addr; |
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}; |
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/* Egress queue params */ |
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struct csio_eq_params { |
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uint8_t pfn; |
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uint8_t vfn; |
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uint8_t eqstart:1; |
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uint8_t eqstop:1; |
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uint16_t physeqid; |
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uint32_t eqid; |
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uint8_t hostfcmode:2; |
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uint8_t cprio:1; |
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uint8_t pciechn:3; |
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uint16_t iqid; |
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uint8_t dcaen:1; |
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uint8_t dcacpu:5; |
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uint8_t fbmin:3; |
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uint8_t fbmax:3; |
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uint8_t cidxfthresho:1; |
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uint8_t cidxfthresh:3; |
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uint16_t eqsize; |
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uint64_t eqaddr; |
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}; |
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struct csio_dma_buf { |
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struct list_head list; |
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void *vaddr; /* Virtual address */ |
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dma_addr_t paddr; /* Physical address */ |
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uint32_t len; /* Buffer size */ |
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}; |
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/* Generic I/O request structure */ |
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struct csio_ioreq { |
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struct csio_sm sm; /* SM, List |
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* should be the first member |
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*/ |
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int iq_idx; /* Ingress queue index */ |
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int eq_idx; /* Egress queue index */ |
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uint32_t nsge; /* Number of SG elements */ |
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uint32_t tmo; /* Driver timeout */ |
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uint32_t datadir; /* Data direction */ |
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struct csio_dma_buf dma_buf; /* Req/resp DMA buffers */ |
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uint16_t wr_status; /* WR completion status */ |
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int16_t drv_status; /* Driver internal status */ |
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struct csio_lnode *lnode; /* Owner lnode */ |
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struct csio_rnode *rnode; /* Src/destination rnode */ |
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void (*io_cbfn) (struct csio_hw *, struct csio_ioreq *); |
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/* completion callback */ |
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void *scratch1; /* Scratch area 1. |
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*/ |
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void *scratch2; /* Scratch area 2. */ |
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struct list_head gen_list; /* Any list associated with |
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* this ioreq. |
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*/ |
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uint64_t fw_handle; /* Unique handle passed |
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* to FW |
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*/ |
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uint8_t dcopy; /* Data copy required */ |
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uint8_t reserved1; |
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uint16_t reserved2; |
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struct completion cmplobj; /* ioreq completion object */ |
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} ____cacheline_aligned_in_smp; |
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/* |
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* Egress status page for egress cidx updates |
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*/ |
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struct csio_qstatus_page { |
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__be32 qid; |
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__be16 cidx; |
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__be16 pidx; |
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}; |
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enum { |
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CSIO_MAX_FLBUF_PER_IQWR = 4, |
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CSIO_QCREDIT_SZ = 64, /* pidx/cidx increments |
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* in bytes |
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*/ |
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CSIO_MAX_QID = 0xFFFF, |
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CSIO_MAX_IQ = 128, |
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CSIO_SGE_NTIMERS = 6, |
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CSIO_SGE_NCOUNTERS = 4, |
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CSIO_SGE_FL_SIZE_REGS = 16, |
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}; |
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/* Defines for type */ |
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enum { |
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CSIO_EGRESS = 1, |
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CSIO_INGRESS = 2, |
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CSIO_FREELIST = 3, |
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}; |
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/* |
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* Structure for footer (last 2 flits) of Ingress Queue Entry. |
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*/ |
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struct csio_iqwr_footer { |
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__be32 hdrbuflen_pidx; |
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__be32 pldbuflen_qid; |
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union { |
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u8 type_gen; |
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__be64 last_flit; |
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} u; |
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}; |
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#define IQWRF_NEWBUF (1 << 31) |
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#define IQWRF_LEN_GET(x) (((x) >> 0) & 0x7fffffffU) |
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#define IQWRF_GEN_SHIFT 7 |
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#define IQWRF_TYPE_GET(x) (((x) >> 4) & 0x3U) |
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/* |
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* WR pair: |
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* ======== |
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* A WR can start towards the end of a queue, and then continue at the |
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* beginning, since the queue is considered to be circular. This will |
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* require a pair of address/len to be passed back to the caller - |
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* hence the Work request pair structure. |
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*/ |
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struct csio_wr_pair { |
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void *addr1; |
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uint32_t size1; |
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void *addr2; |
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uint32_t size2; |
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}; |
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/* |
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* The following structure is used by ingress processing to return the |
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* free list buffers to consumers. |
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*/ |
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struct csio_fl_dma_buf { |
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struct csio_dma_buf flbufs[CSIO_MAX_FLBUF_PER_IQWR]; |
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/* Freelist DMA buffers */ |
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int offset; /* Offset within the |
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* first FL buf. |
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*/ |
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uint32_t totlen; /* Total length */ |
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uint8_t defer_free; /* Free of buffer can |
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* deferred |
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*/ |
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}; |
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/* Data-types */ |
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typedef void (*iq_handler_t)(struct csio_hw *, void *, uint32_t, |
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struct csio_fl_dma_buf *, void *); |
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struct csio_iq { |
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uint16_t iqid; /* Queue ID */ |
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uint16_t physiqid; /* Physical Queue ID */ |
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uint16_t genbit; /* Generation bit, |
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* initially set to 1 |
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*/ |
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int flq_idx; /* Freelist queue index */ |
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iq_handler_t iq_intx_handler; /* IQ INTx handler routine */ |
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}; |
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struct csio_eq { |
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uint16_t eqid; /* Qid */ |
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uint16_t physeqid; /* Physical Queue ID */ |
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uint8_t wrap[512]; /* Temp area for q-wrap around*/ |
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}; |
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struct csio_fl { |
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uint16_t flid; /* Qid */ |
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uint16_t packen; /* Packing enabled? */ |
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int offset; /* Offset within FL buf */ |
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int sreg; /* Size register */ |
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struct csio_dma_buf *bufs; /* Free list buffer ptr array |
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* indexed using flq->cidx/pidx |
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*/ |
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}; |
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struct csio_qstats { |
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uint32_t n_tot_reqs; /* Total no. of Requests */ |
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uint32_t n_tot_rsps; /* Total no. of responses */ |
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uint32_t n_qwrap; /* Queue wraps */ |
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uint32_t n_eq_wr_split; /* Number of split EQ WRs */ |
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uint32_t n_qentry; /* Queue entry */ |
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uint32_t n_qempty; /* Queue empty */ |
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uint32_t n_qfull; /* Queue fulls */ |
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uint32_t n_rsp_unknown; /* Unknown response type */ |
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uint32_t n_stray_comp; /* Stray completion intr */ |
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uint32_t n_flq_refill; /* Number of FL refills */ |
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}; |
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/* Queue metadata */ |
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struct csio_q { |
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uint16_t type; /* Type: Ingress/Egress/FL */ |
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uint16_t pidx; /* producer index */ |
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uint16_t cidx; /* consumer index */ |
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uint16_t inc_idx; /* Incremental index */ |
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uint32_t wr_sz; /* Size of all WRs in this q |
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* if fixed |
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*/ |
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void *vstart; /* Base virtual address |
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* of queue |
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*/ |
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void *vwrap; /* Virtual end address to |
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* wrap around at |
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*/ |
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uint32_t credits; /* Size of queue in credits */ |
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void *owner; /* Owner */ |
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union { /* Queue contexts */ |
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struct csio_iq iq; |
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struct csio_eq eq; |
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struct csio_fl fl; |
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} un; |
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dma_addr_t pstart; /* Base physical address of |
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* queue |
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*/ |
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uint32_t portid; /* PCIE Channel */ |
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uint32_t size; /* Size of queue in bytes */ |
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struct csio_qstats stats; /* Statistics */ |
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} ____cacheline_aligned_in_smp; |
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struct csio_sge { |
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uint32_t csio_fl_align; /* Calculated and cached |
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* for fast path |
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*/ |
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uint32_t sge_control; /* padding, boundaries, |
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* lengths, etc. |
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*/ |
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uint32_t sge_host_page_size; /* Host page size */ |
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uint32_t sge_fl_buf_size[CSIO_SGE_FL_SIZE_REGS]; |
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/* free list buffer sizes */ |
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uint16_t timer_val[CSIO_SGE_NTIMERS]; |
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uint8_t counter_val[CSIO_SGE_NCOUNTERS]; |
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}; |
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/* Work request module */ |
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struct csio_wrm { |
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int num_q; /* Number of queues */ |
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struct csio_q **q_arr; /* Array of queue pointers |
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* allocated dynamically |
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* based on configured values |
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*/ |
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uint32_t fw_iq_start; /* Start ID of IQ for this fn*/ |
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uint32_t fw_eq_start; /* Start ID of EQ for this fn*/ |
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struct csio_q *intr_map[CSIO_MAX_IQ]; |
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/* IQ-id to IQ map table. */ |
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int free_qidx; /* queue idx of free queue */ |
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struct csio_sge sge; /* SGE params */ |
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}; |
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#define csio_get_q(__hw, __idx) ((__hw)->wrm.q_arr[__idx]) |
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#define csio_q_type(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->type) |
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#define csio_q_pidx(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->pidx) |
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#define csio_q_cidx(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->cidx) |
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#define csio_q_inc_idx(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->inc_idx) |
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#define csio_q_vstart(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->vstart) |
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#define csio_q_pstart(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->pstart) |
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#define csio_q_size(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->size) |
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#define csio_q_credits(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->credits) |
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#define csio_q_portid(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->portid) |
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#define csio_q_wr_sz(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->wr_sz) |
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#define csio_q_iqid(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->un.iq.iqid) |
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#define csio_q_physiqid(__hw, __idx) \ |
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((__hw)->wrm.q_arr[(__idx)]->un.iq.physiqid) |
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#define csio_q_iq_flq_idx(__hw, __idx) \ |
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((__hw)->wrm.q_arr[(__idx)]->un.iq.flq_idx) |
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#define csio_q_eqid(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->un.eq.eqid) |
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#define csio_q_flid(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->un.fl.flid) |
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#define csio_q_physeqid(__hw, __idx) \ |
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((__hw)->wrm.q_arr[(__idx)]->un.eq.physeqid) |
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#define csio_iq_has_fl(__iq) ((__iq)->un.iq.flq_idx != -1) |
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#define csio_q_iq_to_flid(__hw, __iq_idx) \ |
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csio_q_flid((__hw), (__hw)->wrm.q_arr[(__iq_qidx)]->un.iq.flq_idx) |
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#define csio_q_set_intr_map(__hw, __iq_idx, __rel_iq_id) \ |
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(__hw)->wrm.intr_map[__rel_iq_id] = csio_get_q(__hw, __iq_idx) |
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#define csio_q_eq_wrap(__hw, __idx) ((__hw)->wrm.q_arr[(__idx)]->un.eq.wrap) |
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struct csio_mb; |
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int csio_wr_alloc_q(struct csio_hw *, uint32_t, uint32_t, |
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uint16_t, void *, uint32_t, int, iq_handler_t); |
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int csio_wr_iq_create(struct csio_hw *, void *, int, |
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uint32_t, uint8_t, bool, |
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void (*)(struct csio_hw *, struct csio_mb *)); |
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int csio_wr_eq_create(struct csio_hw *, void *, int, int, uint8_t, |
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void (*)(struct csio_hw *, struct csio_mb *)); |
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int csio_wr_destroy_queues(struct csio_hw *, bool cmd); |
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int csio_wr_get(struct csio_hw *, int, uint32_t, |
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struct csio_wr_pair *); |
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void csio_wr_copy_to_wrp(void *, struct csio_wr_pair *, uint32_t, uint32_t); |
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int csio_wr_issue(struct csio_hw *, int, bool); |
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int csio_wr_process_iq(struct csio_hw *, struct csio_q *, |
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void (*)(struct csio_hw *, void *, |
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uint32_t, struct csio_fl_dma_buf *, |
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void *), |
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void *); |
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int csio_wr_process_iq_idx(struct csio_hw *, int, |
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void (*)(struct csio_hw *, void *, |
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uint32_t, struct csio_fl_dma_buf *, |
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void *), |
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void *); |
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void csio_wr_sge_init(struct csio_hw *); |
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int csio_wrm_init(struct csio_wrm *, struct csio_hw *); |
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void csio_wrm_exit(struct csio_wrm *, struct csio_hw *); |
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#endif /* ifndef __CSIO_WR_H__ */
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