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748 lines
19 KiB
748 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips |
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* |
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* Copyright (C) 2008 David Brownell |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/bcd.h> |
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#include <linux/slab.h> |
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#include <linux/rtc.h> |
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#include <linux/workqueue.h> |
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|
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#include <linux/spi/spi.h> |
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#include <linux/spi/ds1305.h> |
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#include <linux/module.h> |
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|
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/* |
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* Registers ... mask DS1305_WRITE into register address to write, |
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* otherwise you're reading it. All non-bitmask values are BCD. |
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*/ |
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#define DS1305_WRITE 0x80 |
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|
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/* RTC date/time ... the main special cases are that we: |
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* - Need fancy "hours" encoding in 12hour mode |
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* - Don't rely on the "day-of-week" field (or tm_wday) |
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* - Are a 21st-century clock (2000 <= year < 2100) |
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*/ |
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#define DS1305_RTC_LEN 7 /* bytes for RTC regs */ |
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|
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#define DS1305_SEC 0x00 /* register addresses */ |
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#define DS1305_MIN 0x01 |
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#define DS1305_HOUR 0x02 |
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# define DS1305_HR_12 0x40 /* set == 12 hr mode */ |
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# define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */ |
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#define DS1305_WDAY 0x03 |
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#define DS1305_MDAY 0x04 |
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#define DS1305_MON 0x05 |
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#define DS1305_YEAR 0x06 |
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|
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/* The two alarms have only sec/min/hour/wday fields (ALM_LEN). |
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* DS1305_ALM_DISABLE disables a match field (some combos are bad). |
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* |
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* NOTE that since we don't use WDAY, we limit ourselves to alarms |
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* only one day into the future (vs potentially up to a week). |
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* |
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* NOTE ALSO that while we could generate once-a-second IRQs (UIE), we |
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* don't currently support them. We'd either need to do it only when |
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* no alarm is pending (not the standard model), or to use the second |
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* alarm (implying that this is a DS1305 not DS1306, *and* that either |
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* it's wired up a second IRQ we know, or that INTCN is set) |
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*/ |
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#define DS1305_ALM_LEN 4 /* bytes for ALM regs */ |
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#define DS1305_ALM_DISABLE 0x80 |
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#define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */ |
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#define DS1305_ALM1(r) (0x0b + (r)) |
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/* three control registers */ |
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#define DS1305_CONTROL_LEN 3 /* bytes of control regs */ |
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|
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#define DS1305_CONTROL 0x0f /* register addresses */ |
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# define DS1305_nEOSC 0x80 /* low enables oscillator */ |
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# define DS1305_WP 0x40 /* write protect */ |
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# define DS1305_INTCN 0x04 /* clear == only int0 used */ |
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# define DS1306_1HZ 0x04 /* enable 1Hz output */ |
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# define DS1305_AEI1 0x02 /* enable ALM1 IRQ */ |
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# define DS1305_AEI0 0x01 /* enable ALM0 IRQ */ |
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#define DS1305_STATUS 0x10 |
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/* status has just AEIx bits, mirrored as IRQFx */ |
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#define DS1305_TRICKLE 0x11 |
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/* trickle bits are defined in <linux/spi/ds1305.h> */ |
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|
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/* a bunch of NVRAM */ |
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#define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */ |
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#define DS1305_NVRAM 0x20 /* register addresses */ |
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struct ds1305 { |
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struct spi_device *spi; |
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struct rtc_device *rtc; |
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struct work_struct work; |
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unsigned long flags; |
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#define FLAG_EXITING 0 |
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bool hr12; |
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u8 ctrl[DS1305_CONTROL_LEN]; |
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}; |
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/*----------------------------------------------------------------------*/ |
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/* |
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* Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux |
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* software (like a bootloader) which may require it. |
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*/ |
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static unsigned bcd2hour(u8 bcd) |
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{ |
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if (bcd & DS1305_HR_12) { |
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unsigned hour = 0; |
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bcd &= ~DS1305_HR_12; |
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if (bcd & DS1305_HR_PM) { |
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hour = 12; |
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bcd &= ~DS1305_HR_PM; |
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} |
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hour += bcd2bin(bcd); |
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return hour - 1; |
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} |
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return bcd2bin(bcd); |
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} |
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static u8 hour2bcd(bool hr12, int hour) |
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{ |
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if (hr12) { |
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hour++; |
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if (hour <= 12) |
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return DS1305_HR_12 | bin2bcd(hour); |
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hour -= 12; |
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return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour); |
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} |
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return bin2bcd(hour); |
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} |
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/*----------------------------------------------------------------------*/ |
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|
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/* |
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* Interface to RTC framework |
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*/ |
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static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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u8 buf[2]; |
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long err = -EINVAL; |
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buf[0] = DS1305_WRITE | DS1305_CONTROL; |
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buf[1] = ds1305->ctrl[0]; |
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if (enabled) { |
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if (ds1305->ctrl[0] & DS1305_AEI0) |
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goto done; |
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buf[1] |= DS1305_AEI0; |
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} else { |
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if (!(buf[1] & DS1305_AEI0)) |
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goto done; |
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buf[1] &= ~DS1305_AEI0; |
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} |
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err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0); |
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if (err >= 0) |
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ds1305->ctrl[0] = buf[1]; |
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done: |
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return err; |
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} |
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/* |
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* Get/set of date and time is pretty normal. |
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*/ |
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static int ds1305_get_time(struct device *dev, struct rtc_time *time) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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u8 addr = DS1305_SEC; |
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u8 buf[DS1305_RTC_LEN]; |
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int status; |
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/* Use write-then-read to get all the date/time registers |
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* since dma from stack is nonportable |
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*/ |
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status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr), |
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buf, sizeof(buf)); |
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if (status < 0) |
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return status; |
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dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]); |
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/* Decode the registers */ |
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time->tm_sec = bcd2bin(buf[DS1305_SEC]); |
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time->tm_min = bcd2bin(buf[DS1305_MIN]); |
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time->tm_hour = bcd2hour(buf[DS1305_HOUR]); |
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time->tm_wday = buf[DS1305_WDAY] - 1; |
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time->tm_mday = bcd2bin(buf[DS1305_MDAY]); |
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time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1; |
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time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100; |
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dev_vdbg(dev, "%s secs=%d, mins=%d, " |
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"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", |
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"read", time->tm_sec, time->tm_min, |
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time->tm_hour, time->tm_mday, |
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time->tm_mon, time->tm_year, time->tm_wday); |
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return 0; |
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} |
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static int ds1305_set_time(struct device *dev, struct rtc_time *time) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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u8 buf[1 + DS1305_RTC_LEN]; |
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u8 *bp = buf; |
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dev_vdbg(dev, "%s secs=%d, mins=%d, " |
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"hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n", |
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"write", time->tm_sec, time->tm_min, |
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time->tm_hour, time->tm_mday, |
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time->tm_mon, time->tm_year, time->tm_wday); |
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/* Write registers starting at the first time/date address. */ |
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*bp++ = DS1305_WRITE | DS1305_SEC; |
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*bp++ = bin2bcd(time->tm_sec); |
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*bp++ = bin2bcd(time->tm_min); |
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*bp++ = hour2bcd(ds1305->hr12, time->tm_hour); |
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*bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1; |
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*bp++ = bin2bcd(time->tm_mday); |
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*bp++ = bin2bcd(time->tm_mon + 1); |
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*bp++ = bin2bcd(time->tm_year - 100); |
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dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]); |
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/* use write-then-read since dma from stack is nonportable */ |
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return spi_write_then_read(ds1305->spi, buf, sizeof(buf), |
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NULL, 0); |
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} |
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/* |
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* Get/set of alarm is a bit funky: |
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* |
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* - First there's the inherent raciness of getting the (partitioned) |
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* status of an alarm that could trigger while we're reading parts |
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* of that status. |
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* |
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* - Second there's its limited range (we could increase it a bit by |
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* relying on WDAY), which means it will easily roll over. |
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* |
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* - Third there's the choice of two alarms and alarm signals. |
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* Here we use ALM0 and expect that nINT0 (open drain) is used; |
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* that's the only real option for DS1306 runtime alarms, and is |
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* natural on DS1305. |
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* |
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* - Fourth, there's also ALM1, and a second interrupt signal: |
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* + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0; |
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* + On DS1306 ALM1 only uses INT1 (an active high pulse) |
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* and it won't work when VCC1 is active. |
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* |
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* So to be most general, we should probably set both alarms to the |
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* same value, letting ALM1 be the wakeup event source on DS1306 |
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* and handling several wiring options on DS1305. |
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* |
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* - Fifth, we support the polled mode (as well as possible; why not?) |
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* even when no interrupt line is wired to an IRQ. |
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*/ |
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/* |
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* Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) |
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*/ |
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static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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struct spi_device *spi = ds1305->spi; |
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u8 addr; |
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int status; |
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u8 buf[DS1305_ALM_LEN]; |
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/* Refresh control register cache BEFORE reading ALM0 registers, |
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* since reading alarm registers acks any pending IRQ. That |
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* makes returning "pending" status a bit of a lie, but that bit |
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* of EFI status is at best fragile anyway (given IRQ handlers). |
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*/ |
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addr = DS1305_CONTROL; |
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status = spi_write_then_read(spi, &addr, sizeof(addr), |
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ds1305->ctrl, sizeof(ds1305->ctrl)); |
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if (status < 0) |
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return status; |
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alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0); |
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alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0); |
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/* get and check ALM0 registers */ |
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addr = DS1305_ALM0(DS1305_SEC); |
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status = spi_write_then_read(spi, &addr, sizeof(addr), |
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buf, sizeof(buf)); |
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if (status < 0) |
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return status; |
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dev_vdbg(dev, "%s: %02x %02x %02x %02x\n", |
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"alm0 read", buf[DS1305_SEC], buf[DS1305_MIN], |
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buf[DS1305_HOUR], buf[DS1305_WDAY]); |
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if ((DS1305_ALM_DISABLE & buf[DS1305_SEC]) |
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|| (DS1305_ALM_DISABLE & buf[DS1305_MIN]) |
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|| (DS1305_ALM_DISABLE & buf[DS1305_HOUR])) |
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return -EIO; |
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/* Stuff these values into alm->time and let RTC framework code |
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* fill in the rest ... and also handle rollover to tomorrow when |
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* that's needed. |
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*/ |
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alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]); |
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alm->time.tm_min = bcd2bin(buf[DS1305_MIN]); |
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alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]); |
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return 0; |
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} |
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/* |
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* Context: caller holds rtc->ops_lock (to protect ds1305->ctrl) |
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*/ |
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static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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struct spi_device *spi = ds1305->spi; |
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unsigned long now, later; |
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struct rtc_time tm; |
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int status; |
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u8 buf[1 + DS1305_ALM_LEN]; |
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|
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/* convert desired alarm to time_t */ |
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later = rtc_tm_to_time64(&alm->time); |
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|
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/* Read current time as time_t */ |
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status = ds1305_get_time(dev, &tm); |
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if (status < 0) |
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return status; |
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now = rtc_tm_to_time64(&tm); |
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/* make sure alarm fires within the next 24 hours */ |
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if (later <= now) |
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return -EINVAL; |
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if ((later - now) > 24 * 60 * 60) |
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return -EDOM; |
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|
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/* disable alarm if needed */ |
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if (ds1305->ctrl[0] & DS1305_AEI0) { |
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ds1305->ctrl[0] &= ~DS1305_AEI0; |
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|
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buf[0] = DS1305_WRITE | DS1305_CONTROL; |
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buf[1] = ds1305->ctrl[0]; |
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status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); |
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if (status < 0) |
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return status; |
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} |
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/* write alarm */ |
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buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC); |
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buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec); |
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buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min); |
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buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour); |
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buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE; |
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dev_dbg(dev, "%s: %02x %02x %02x %02x\n", |
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"alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN], |
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buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]); |
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|
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status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
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if (status < 0) |
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return status; |
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|
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/* enable alarm if requested */ |
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if (alm->enabled) { |
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ds1305->ctrl[0] |= DS1305_AEI0; |
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|
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buf[0] = DS1305_WRITE | DS1305_CONTROL; |
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buf[1] = ds1305->ctrl[0]; |
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status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0); |
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} |
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|
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return status; |
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} |
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#ifdef CONFIG_PROC_FS |
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|
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static int ds1305_proc(struct device *dev, struct seq_file *seq) |
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{ |
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struct ds1305 *ds1305 = dev_get_drvdata(dev); |
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char *diodes = "no"; |
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char *resistors = ""; |
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|
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/* ctrl[2] is treated as read-only; no locking needed */ |
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if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) { |
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switch (ds1305->ctrl[2] & 0x0c) { |
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case DS1305_TRICKLE_DS2: |
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diodes = "2 diodes, "; |
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break; |
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case DS1305_TRICKLE_DS1: |
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diodes = "1 diode, "; |
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break; |
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default: |
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goto done; |
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} |
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switch (ds1305->ctrl[2] & 0x03) { |
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case DS1305_TRICKLE_2K: |
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resistors = "2k Ohm"; |
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break; |
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case DS1305_TRICKLE_4K: |
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resistors = "4k Ohm"; |
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break; |
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case DS1305_TRICKLE_8K: |
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resistors = "8k Ohm"; |
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break; |
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default: |
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diodes = "no"; |
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break; |
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} |
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} |
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|
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done: |
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seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors); |
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|
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return 0; |
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} |
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|
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#else |
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#define ds1305_proc NULL |
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#endif |
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|
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static const struct rtc_class_ops ds1305_ops = { |
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.read_time = ds1305_get_time, |
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.set_time = ds1305_set_time, |
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.read_alarm = ds1305_get_alarm, |
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.set_alarm = ds1305_set_alarm, |
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.proc = ds1305_proc, |
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.alarm_irq_enable = ds1305_alarm_irq_enable, |
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}; |
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|
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static void ds1305_work(struct work_struct *work) |
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{ |
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struct ds1305 *ds1305 = container_of(work, struct ds1305, work); |
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struct spi_device *spi = ds1305->spi; |
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u8 buf[3]; |
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int status; |
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|
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/* lock to protect ds1305->ctrl */ |
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rtc_lock(ds1305->rtc); |
|
|
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/* Disable the IRQ, and clear its status ... for now, we "know" |
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* that if more than one alarm is active, they're in sync. |
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* Note that reading ALM data registers also clears IRQ status. |
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*/ |
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ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0); |
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ds1305->ctrl[1] = 0; |
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|
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buf[0] = DS1305_WRITE | DS1305_CONTROL; |
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buf[1] = ds1305->ctrl[0]; |
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buf[2] = 0; |
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|
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status = spi_write_then_read(spi, buf, sizeof(buf), |
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NULL, 0); |
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if (status < 0) |
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dev_dbg(&spi->dev, "clear irq --> %d\n", status); |
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|
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rtc_unlock(ds1305->rtc); |
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|
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if (!test_bit(FLAG_EXITING, &ds1305->flags)) |
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enable_irq(spi->irq); |
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|
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rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF); |
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} |
|
|
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/* |
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* This "real" IRQ handler hands off to a workqueue mostly to allow |
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* mutex locking for ds1305->ctrl ... unlike I2C, we could issue async |
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* I/O requests in IRQ context (to clear the IRQ status). |
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*/ |
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static irqreturn_t ds1305_irq(int irq, void *p) |
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{ |
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struct ds1305 *ds1305 = p; |
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|
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disable_irq(irq); |
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schedule_work(&ds1305->work); |
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return IRQ_HANDLED; |
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} |
|
|
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/*----------------------------------------------------------------------*/ |
|
|
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/* |
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* Interface for NVRAM |
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*/ |
|
|
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static void msg_init(struct spi_message *m, struct spi_transfer *x, |
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u8 *addr, size_t count, char *tx, char *rx) |
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{ |
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spi_message_init(m); |
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memset(x, 0, 2 * sizeof(*x)); |
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|
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x->tx_buf = addr; |
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x->len = 1; |
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spi_message_add_tail(x, m); |
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|
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x++; |
|
|
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x->tx_buf = tx; |
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x->rx_buf = rx; |
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x->len = count; |
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spi_message_add_tail(x, m); |
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} |
|
|
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static int ds1305_nvram_read(void *priv, unsigned int off, void *buf, |
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size_t count) |
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{ |
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struct ds1305 *ds1305 = priv; |
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struct spi_device *spi = ds1305->spi; |
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u8 addr; |
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struct spi_message m; |
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struct spi_transfer x[2]; |
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|
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addr = DS1305_NVRAM + off; |
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msg_init(&m, x, &addr, count, NULL, buf); |
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|
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return spi_sync(spi, &m); |
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} |
|
|
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static int ds1305_nvram_write(void *priv, unsigned int off, void *buf, |
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size_t count) |
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{ |
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struct ds1305 *ds1305 = priv; |
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struct spi_device *spi = ds1305->spi; |
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u8 addr; |
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struct spi_message m; |
|
struct spi_transfer x[2]; |
|
|
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addr = (DS1305_WRITE | DS1305_NVRAM) + off; |
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msg_init(&m, x, &addr, count, buf, NULL); |
|
|
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return spi_sync(spi, &m); |
|
} |
|
|
|
/*----------------------------------------------------------------------*/ |
|
|
|
/* |
|
* Interface to SPI stack |
|
*/ |
|
|
|
static int ds1305_probe(struct spi_device *spi) |
|
{ |
|
struct ds1305 *ds1305; |
|
int status; |
|
u8 addr, value; |
|
struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev); |
|
bool write_ctrl = false; |
|
struct nvmem_config ds1305_nvmem_cfg = { |
|
.name = "ds1305_nvram", |
|
.word_size = 1, |
|
.stride = 1, |
|
.size = DS1305_NVRAM_LEN, |
|
.reg_read = ds1305_nvram_read, |
|
.reg_write = ds1305_nvram_write, |
|
}; |
|
|
|
/* Sanity check board setup data. This may be hooked up |
|
* in 3wire mode, but we don't care. Note that unless |
|
* there's an inverter in place, this needs SPI_CS_HIGH! |
|
*/ |
|
if ((spi->bits_per_word && spi->bits_per_word != 8) |
|
|| (spi->max_speed_hz > 2000000) |
|
|| !(spi->mode & SPI_CPHA)) |
|
return -EINVAL; |
|
|
|
/* set up driver data */ |
|
ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL); |
|
if (!ds1305) |
|
return -ENOMEM; |
|
ds1305->spi = spi; |
|
spi_set_drvdata(spi, ds1305); |
|
|
|
/* read and cache control registers */ |
|
addr = DS1305_CONTROL; |
|
status = spi_write_then_read(spi, &addr, sizeof(addr), |
|
ds1305->ctrl, sizeof(ds1305->ctrl)); |
|
if (status < 0) { |
|
dev_dbg(&spi->dev, "can't %s, %d\n", |
|
"read", status); |
|
return status; |
|
} |
|
|
|
dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl); |
|
|
|
/* Sanity check register values ... partially compensating for the |
|
* fact that SPI has no device handshake. A pullup on MISO would |
|
* make these tests fail; but not all systems will have one. If |
|
* some register is neither 0x00 nor 0xff, a chip is likely there. |
|
*/ |
|
if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) { |
|
dev_dbg(&spi->dev, "RTC chip is not present\n"); |
|
return -ENODEV; |
|
} |
|
if (ds1305->ctrl[2] == 0) |
|
dev_dbg(&spi->dev, "chip may not be present\n"); |
|
|
|
/* enable writes if needed ... if we were paranoid it would |
|
* make sense to enable them only when absolutely necessary. |
|
*/ |
|
if (ds1305->ctrl[0] & DS1305_WP) { |
|
u8 buf[2]; |
|
|
|
ds1305->ctrl[0] &= ~DS1305_WP; |
|
|
|
buf[0] = DS1305_WRITE | DS1305_CONTROL; |
|
buf[1] = ds1305->ctrl[0]; |
|
status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
|
|
|
dev_dbg(&spi->dev, "clear WP --> %d\n", status); |
|
if (status < 0) |
|
return status; |
|
} |
|
|
|
/* on DS1305, maybe start oscillator; like most low power |
|
* oscillators, it may take a second to stabilize |
|
*/ |
|
if (ds1305->ctrl[0] & DS1305_nEOSC) { |
|
ds1305->ctrl[0] &= ~DS1305_nEOSC; |
|
write_ctrl = true; |
|
dev_warn(&spi->dev, "SET TIME!\n"); |
|
} |
|
|
|
/* ack any pending IRQs */ |
|
if (ds1305->ctrl[1]) { |
|
ds1305->ctrl[1] = 0; |
|
write_ctrl = true; |
|
} |
|
|
|
/* this may need one-time (re)init */ |
|
if (pdata) { |
|
/* maybe enable trickle charge */ |
|
if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) { |
|
ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC |
|
| pdata->trickle; |
|
write_ctrl = true; |
|
} |
|
|
|
/* on DS1306, configure 1 Hz signal */ |
|
if (pdata->is_ds1306) { |
|
if (pdata->en_1hz) { |
|
if (!(ds1305->ctrl[0] & DS1306_1HZ)) { |
|
ds1305->ctrl[0] |= DS1306_1HZ; |
|
write_ctrl = true; |
|
} |
|
} else { |
|
if (ds1305->ctrl[0] & DS1306_1HZ) { |
|
ds1305->ctrl[0] &= ~DS1306_1HZ; |
|
write_ctrl = true; |
|
} |
|
} |
|
} |
|
} |
|
|
|
if (write_ctrl) { |
|
u8 buf[4]; |
|
|
|
buf[0] = DS1305_WRITE | DS1305_CONTROL; |
|
buf[1] = ds1305->ctrl[0]; |
|
buf[2] = ds1305->ctrl[1]; |
|
buf[3] = ds1305->ctrl[2]; |
|
status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0); |
|
if (status < 0) { |
|
dev_dbg(&spi->dev, "can't %s, %d\n", |
|
"write", status); |
|
return status; |
|
} |
|
|
|
dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl); |
|
} |
|
|
|
/* see if non-Linux software set up AM/PM mode */ |
|
addr = DS1305_HOUR; |
|
status = spi_write_then_read(spi, &addr, sizeof(addr), |
|
&value, sizeof(value)); |
|
if (status < 0) { |
|
dev_dbg(&spi->dev, "read HOUR --> %d\n", status); |
|
return status; |
|
} |
|
|
|
ds1305->hr12 = (DS1305_HR_12 & value) != 0; |
|
if (ds1305->hr12) |
|
dev_dbg(&spi->dev, "AM/PM\n"); |
|
|
|
/* register RTC ... from here on, ds1305->ctrl needs locking */ |
|
ds1305->rtc = devm_rtc_allocate_device(&spi->dev); |
|
if (IS_ERR(ds1305->rtc)) |
|
return PTR_ERR(ds1305->rtc); |
|
|
|
ds1305->rtc->ops = &ds1305_ops; |
|
ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000; |
|
ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099; |
|
|
|
ds1305_nvmem_cfg.priv = ds1305; |
|
status = devm_rtc_register_device(ds1305->rtc); |
|
if (status) |
|
return status; |
|
|
|
devm_rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg); |
|
|
|
/* Maybe set up alarm IRQ; be ready to handle it triggering right |
|
* away. NOTE that we don't share this. The signal is active low, |
|
* and we can't ack it before a SPI message delay. We temporarily |
|
* disable the IRQ until it's acked, which lets us work with more |
|
* IRQ trigger modes (not all IRQ controllers can do falling edge). |
|
*/ |
|
if (spi->irq) { |
|
INIT_WORK(&ds1305->work, ds1305_work); |
|
status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq, |
|
0, dev_name(&ds1305->rtc->dev), ds1305); |
|
if (status < 0) { |
|
dev_err(&spi->dev, "request_irq %d --> %d\n", |
|
spi->irq, status); |
|
} else { |
|
device_set_wakeup_capable(&spi->dev, 1); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int ds1305_remove(struct spi_device *spi) |
|
{ |
|
struct ds1305 *ds1305 = spi_get_drvdata(spi); |
|
|
|
/* carefully shut down irq and workqueue, if present */ |
|
if (spi->irq) { |
|
set_bit(FLAG_EXITING, &ds1305->flags); |
|
devm_free_irq(&spi->dev, spi->irq, ds1305); |
|
cancel_work_sync(&ds1305->work); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static struct spi_driver ds1305_driver = { |
|
.driver.name = "rtc-ds1305", |
|
.probe = ds1305_probe, |
|
.remove = ds1305_remove, |
|
/* REVISIT add suspend/resume */ |
|
}; |
|
|
|
module_spi_driver(ds1305_driver); |
|
|
|
MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("spi:rtc-ds1305");
|
|
|