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340 lines
8.9 KiB
340 lines
8.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2016 Oleksij Rempel <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/rtc.h> |
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/* Miscellaneous registers */ |
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/* Interrupt Location Register */ |
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#define HW_ILR 0x00 |
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#define BM_RTCALF BIT(1) |
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#define BM_RTCCIF BIT(0) |
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/* Clock Control Register */ |
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#define HW_CCR 0x08 |
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/* Calibration counter disable */ |
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#define BM_CCALOFF BIT(4) |
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/* Reset internal oscillator divider */ |
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#define BM_CTCRST BIT(1) |
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/* Clock Enable */ |
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#define BM_CLKEN BIT(0) |
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/* Counter Increment Interrupt Register */ |
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#define HW_CIIR 0x0C |
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#define BM_CIIR_IMYEAR BIT(7) |
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#define BM_CIIR_IMMON BIT(6) |
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#define BM_CIIR_IMDOY BIT(5) |
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#define BM_CIIR_IMDOW BIT(4) |
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#define BM_CIIR_IMDOM BIT(3) |
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#define BM_CIIR_IMHOUR BIT(2) |
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#define BM_CIIR_IMMIN BIT(1) |
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#define BM_CIIR_IMSEC BIT(0) |
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/* Alarm Mask Register */ |
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#define HW_AMR 0x10 |
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#define BM_AMR_IMYEAR BIT(7) |
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#define BM_AMR_IMMON BIT(6) |
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#define BM_AMR_IMDOY BIT(5) |
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#define BM_AMR_IMDOW BIT(4) |
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#define BM_AMR_IMDOM BIT(3) |
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#define BM_AMR_IMHOUR BIT(2) |
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#define BM_AMR_IMMIN BIT(1) |
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#define BM_AMR_IMSEC BIT(0) |
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#define BM_AMR_OFF 0xff |
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/* Consolidated time registers */ |
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#define HW_CTIME0 0x14 |
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#define BM_CTIME0_DOW_S 24 |
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#define BM_CTIME0_DOW_M 0x7 |
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#define BM_CTIME0_HOUR_S 16 |
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#define BM_CTIME0_HOUR_M 0x1f |
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#define BM_CTIME0_MIN_S 8 |
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#define BM_CTIME0_MIN_M 0x3f |
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#define BM_CTIME0_SEC_S 0 |
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#define BM_CTIME0_SEC_M 0x3f |
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#define HW_CTIME1 0x18 |
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#define BM_CTIME1_YEAR_S 16 |
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#define BM_CTIME1_YEAR_M 0xfff |
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#define BM_CTIME1_MON_S 8 |
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#define BM_CTIME1_MON_M 0xf |
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#define BM_CTIME1_DOM_S 0 |
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#define BM_CTIME1_DOM_M 0x1f |
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#define HW_CTIME2 0x1C |
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#define BM_CTIME2_DOY_S 0 |
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#define BM_CTIME2_DOY_M 0xfff |
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/* Time counter registers */ |
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#define HW_SEC 0x20 |
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#define HW_MIN 0x24 |
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#define HW_HOUR 0x28 |
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#define HW_DOM 0x2C |
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#define HW_DOW 0x30 |
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#define HW_DOY 0x34 |
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#define HW_MONTH 0x38 |
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#define HW_YEAR 0x3C |
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#define HW_CALIBRATION 0x40 |
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#define BM_CALDIR_BACK BIT(17) |
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#define BM_CALVAL_M 0x1ffff |
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/* General purpose registers */ |
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#define HW_GPREG0 0x44 |
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#define HW_GPREG1 0x48 |
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#define HW_GPREG2 0x4C |
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#define HW_GPREG3 0x50 |
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#define HW_GPREG4 0x54 |
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/* Alarm register group */ |
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#define HW_ALSEC 0x60 |
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#define HW_ALMIN 0x64 |
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#define HW_ALHOUR 0x68 |
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#define HW_ALDOM 0x6C |
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#define HW_ALDOW 0x70 |
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#define HW_ALDOY 0x74 |
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#define HW_ALMON 0x78 |
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#define HW_ALYEAR 0x7C |
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struct asm9260_rtc_priv { |
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struct device *dev; |
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void __iomem *iobase; |
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struct rtc_device *rtc; |
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struct clk *clk; |
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}; |
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static irqreturn_t asm9260_rtc_irq(int irq, void *dev_id) |
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{ |
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struct asm9260_rtc_priv *priv = dev_id; |
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u32 isr; |
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unsigned long events = 0; |
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rtc_lock(priv->rtc); |
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isr = ioread32(priv->iobase + HW_CIIR); |
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if (!isr) { |
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rtc_unlock(priv->rtc); |
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return IRQ_NONE; |
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} |
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iowrite32(0, priv->iobase + HW_CIIR); |
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rtc_unlock(priv->rtc); |
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events |= RTC_AF | RTC_IRQF; |
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rtc_update_irq(priv->rtc, 1, events); |
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return IRQ_HANDLED; |
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} |
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static int asm9260_rtc_read_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); |
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u32 ctime0, ctime1, ctime2; |
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ctime0 = ioread32(priv->iobase + HW_CTIME0); |
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ctime1 = ioread32(priv->iobase + HW_CTIME1); |
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ctime2 = ioread32(priv->iobase + HW_CTIME2); |
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if (ctime1 != ioread32(priv->iobase + HW_CTIME1)) { |
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/* |
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* woops, counter flipped right now. Now we are safe |
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* to reread. |
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*/ |
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ctime0 = ioread32(priv->iobase + HW_CTIME0); |
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ctime1 = ioread32(priv->iobase + HW_CTIME1); |
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ctime2 = ioread32(priv->iobase + HW_CTIME2); |
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} |
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tm->tm_sec = (ctime0 >> BM_CTIME0_SEC_S) & BM_CTIME0_SEC_M; |
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tm->tm_min = (ctime0 >> BM_CTIME0_MIN_S) & BM_CTIME0_MIN_M; |
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tm->tm_hour = (ctime0 >> BM_CTIME0_HOUR_S) & BM_CTIME0_HOUR_M; |
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tm->tm_wday = (ctime0 >> BM_CTIME0_DOW_S) & BM_CTIME0_DOW_M; |
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tm->tm_mday = (ctime1 >> BM_CTIME1_DOM_S) & BM_CTIME1_DOM_M; |
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tm->tm_mon = (ctime1 >> BM_CTIME1_MON_S) & BM_CTIME1_MON_M; |
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tm->tm_year = (ctime1 >> BM_CTIME1_YEAR_S) & BM_CTIME1_YEAR_M; |
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tm->tm_yday = (ctime2 >> BM_CTIME2_DOY_S) & BM_CTIME2_DOY_M; |
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return 0; |
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} |
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static int asm9260_rtc_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); |
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/* |
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* make sure SEC counter will not flip other counter on write time, |
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* real value will be written at the enf of sequence. |
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*/ |
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iowrite32(0, priv->iobase + HW_SEC); |
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iowrite32(tm->tm_year, priv->iobase + HW_YEAR); |
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iowrite32(tm->tm_mon, priv->iobase + HW_MONTH); |
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iowrite32(tm->tm_mday, priv->iobase + HW_DOM); |
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iowrite32(tm->tm_wday, priv->iobase + HW_DOW); |
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iowrite32(tm->tm_yday, priv->iobase + HW_DOY); |
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iowrite32(tm->tm_hour, priv->iobase + HW_HOUR); |
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iowrite32(tm->tm_min, priv->iobase + HW_MIN); |
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iowrite32(tm->tm_sec, priv->iobase + HW_SEC); |
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return 0; |
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} |
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static int asm9260_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); |
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alrm->time.tm_year = ioread32(priv->iobase + HW_ALYEAR); |
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alrm->time.tm_mon = ioread32(priv->iobase + HW_ALMON); |
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alrm->time.tm_mday = ioread32(priv->iobase + HW_ALDOM); |
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alrm->time.tm_wday = ioread32(priv->iobase + HW_ALDOW); |
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alrm->time.tm_yday = ioread32(priv->iobase + HW_ALDOY); |
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alrm->time.tm_hour = ioread32(priv->iobase + HW_ALHOUR); |
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alrm->time.tm_min = ioread32(priv->iobase + HW_ALMIN); |
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alrm->time.tm_sec = ioread32(priv->iobase + HW_ALSEC); |
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alrm->enabled = ioread32(priv->iobase + HW_AMR) ? 1 : 0; |
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alrm->pending = ioread32(priv->iobase + HW_CIIR) ? 1 : 0; |
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return rtc_valid_tm(&alrm->time); |
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} |
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static int asm9260_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
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{ |
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struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); |
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iowrite32(alrm->time.tm_year, priv->iobase + HW_ALYEAR); |
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iowrite32(alrm->time.tm_mon, priv->iobase + HW_ALMON); |
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iowrite32(alrm->time.tm_mday, priv->iobase + HW_ALDOM); |
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iowrite32(alrm->time.tm_wday, priv->iobase + HW_ALDOW); |
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iowrite32(alrm->time.tm_yday, priv->iobase + HW_ALDOY); |
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iowrite32(alrm->time.tm_hour, priv->iobase + HW_ALHOUR); |
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iowrite32(alrm->time.tm_min, priv->iobase + HW_ALMIN); |
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iowrite32(alrm->time.tm_sec, priv->iobase + HW_ALSEC); |
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iowrite32(alrm->enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR); |
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return 0; |
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} |
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static int asm9260_alarm_irq_enable(struct device *dev, unsigned int enabled) |
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{ |
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struct asm9260_rtc_priv *priv = dev_get_drvdata(dev); |
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iowrite32(enabled ? 0 : BM_AMR_OFF, priv->iobase + HW_AMR); |
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return 0; |
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} |
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static const struct rtc_class_ops asm9260_rtc_ops = { |
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.read_time = asm9260_rtc_read_time, |
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.set_time = asm9260_rtc_set_time, |
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.read_alarm = asm9260_rtc_read_alarm, |
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.set_alarm = asm9260_rtc_set_alarm, |
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.alarm_irq_enable = asm9260_alarm_irq_enable, |
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}; |
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static int asm9260_rtc_probe(struct platform_device *pdev) |
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{ |
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struct asm9260_rtc_priv *priv; |
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struct device *dev = &pdev->dev; |
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int irq_alarm, ret; |
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u32 ccr; |
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priv = devm_kzalloc(dev, sizeof(struct asm9260_rtc_priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->dev = &pdev->dev; |
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platform_set_drvdata(pdev, priv); |
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irq_alarm = platform_get_irq(pdev, 0); |
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if (irq_alarm < 0) |
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return irq_alarm; |
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priv->iobase = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(priv->iobase)) |
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return PTR_ERR(priv->iobase); |
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priv->clk = devm_clk_get(dev, "ahb"); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) { |
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dev_err(dev, "Failed to enable clk!\n"); |
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return ret; |
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} |
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ccr = ioread32(priv->iobase + HW_CCR); |
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/* if dev is not enabled, reset it */ |
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if ((ccr & (BM_CLKEN | BM_CTCRST)) != BM_CLKEN) { |
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iowrite32(BM_CTCRST, priv->iobase + HW_CCR); |
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ccr = 0; |
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} |
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iowrite32(BM_CLKEN | ccr, priv->iobase + HW_CCR); |
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iowrite32(0, priv->iobase + HW_CIIR); |
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iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR); |
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priv->rtc = devm_rtc_device_register(dev, dev_name(dev), |
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&asm9260_rtc_ops, THIS_MODULE); |
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if (IS_ERR(priv->rtc)) { |
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ret = PTR_ERR(priv->rtc); |
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dev_err(dev, "Failed to register RTC device: %d\n", ret); |
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goto err_return; |
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} |
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ret = devm_request_threaded_irq(dev, irq_alarm, NULL, |
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asm9260_rtc_irq, IRQF_ONESHOT, |
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dev_name(dev), priv); |
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if (ret < 0) { |
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dev_err(dev, "can't get irq %i, err %d\n", |
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irq_alarm, ret); |
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goto err_return; |
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} |
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return 0; |
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err_return: |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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static int asm9260_rtc_remove(struct platform_device *pdev) |
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{ |
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struct asm9260_rtc_priv *priv = platform_get_drvdata(pdev); |
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/* Disable alarm matching */ |
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iowrite32(BM_AMR_OFF, priv->iobase + HW_AMR); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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static const struct of_device_id asm9260_dt_ids[] = { |
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{ .compatible = "alphascale,asm9260-rtc", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, asm9260_dt_ids); |
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static struct platform_driver asm9260_rtc_driver = { |
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.probe = asm9260_rtc_probe, |
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.remove = asm9260_rtc_remove, |
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.driver = { |
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.name = "asm9260-rtc", |
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.of_match_table = asm9260_dt_ids, |
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}, |
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}; |
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module_platform_driver(asm9260_rtc_driver); |
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MODULE_AUTHOR("Oleksij Rempel <[email protected]>"); |
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MODULE_DESCRIPTION("Alphascale asm9260 SoC Realtime Clock Driver (RTC)"); |
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MODULE_LICENSE("GPL");
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