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490 lines
12 KiB
490 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* IDT CPS Gen.2 Serial RapidIO switch family support |
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* |
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* Copyright 2010 Integrated Device Technology, Inc. |
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* Alexandre Bounine <[email protected]> |
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*/ |
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#include <linux/stat.h> |
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#include <linux/module.h> |
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#include <linux/rio.h> |
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#include <linux/rio_drv.h> |
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#include <linux/rio_ids.h> |
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#include <linux/delay.h> |
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#include <asm/page.h> |
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#include "../rio.h" |
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#define LOCAL_RTE_CONF_DESTID_SEL 0x010070 |
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#define LOCAL_RTE_CONF_DESTID_SEL_PSEL 0x0000001f |
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#define IDT_LT_ERR_REPORT_EN 0x03100c |
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#define IDT_PORT_ERR_REPORT_EN(n) (0x031044 + (n)*0x40) |
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#define IDT_PORT_ERR_REPORT_EN_BC 0x03ff04 |
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#define IDT_PORT_ISERR_REPORT_EN(n) (0x03104C + (n)*0x40) |
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#define IDT_PORT_ISERR_REPORT_EN_BC 0x03ff0c |
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#define IDT_PORT_INIT_TX_ACQUIRED 0x00000020 |
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#define IDT_LANE_ERR_REPORT_EN(n) (0x038010 + (n)*0x100) |
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#define IDT_LANE_ERR_REPORT_EN_BC 0x03ff10 |
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#define IDT_DEV_CTRL_1 0xf2000c |
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#define IDT_DEV_CTRL_1_GENPW 0x02000000 |
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#define IDT_DEV_CTRL_1_PRSTBEH 0x00000001 |
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#define IDT_CFGBLK_ERR_CAPTURE_EN 0x020008 |
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#define IDT_CFGBLK_ERR_REPORT 0xf20014 |
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#define IDT_CFGBLK_ERR_REPORT_GENPW 0x00000002 |
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#define IDT_AUX_PORT_ERR_CAP_EN 0x020000 |
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#define IDT_AUX_ERR_REPORT_EN 0xf20018 |
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#define IDT_AUX_PORT_ERR_LOG_I2C 0x00000002 |
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#define IDT_AUX_PORT_ERR_LOG_JTAG 0x00000001 |
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#define IDT_ISLTL_ADDRESS_CAP 0x021014 |
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#define IDT_RIO_DOMAIN 0xf20020 |
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#define IDT_RIO_DOMAIN_MASK 0x000000ff |
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#define IDT_PW_INFO_CSR 0xf20024 |
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#define IDT_SOFT_RESET 0xf20040 |
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#define IDT_SOFT_RESET_REQ 0x00030097 |
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#define IDT_I2C_MCTRL 0xf20050 |
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#define IDT_I2C_MCTRL_GENPW 0x04000000 |
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#define IDT_JTAG_CTRL 0xf2005c |
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#define IDT_JTAG_CTRL_GENPW 0x00000002 |
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#define IDT_LANE_CTRL(n) (0xff8000 + (n)*0x100) |
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#define IDT_LANE_CTRL_BC 0xffff00 |
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#define IDT_LANE_CTRL_GENPW 0x00200000 |
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#define IDT_LANE_DFE_1_BC 0xffff18 |
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#define IDT_LANE_DFE_2_BC 0xffff1c |
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#define IDT_PORT_OPS(n) (0xf40004 + (n)*0x100) |
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#define IDT_PORT_OPS_GENPW 0x08000000 |
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#define IDT_PORT_OPS_PL_ELOG 0x00000040 |
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#define IDT_PORT_OPS_LL_ELOG 0x00000020 |
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#define IDT_PORT_OPS_LT_ELOG 0x00000010 |
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#define IDT_PORT_OPS_BC 0xf4ff04 |
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#define IDT_PORT_ISERR_DET(n) (0xf40008 + (n)*0x100) |
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#define IDT_ERR_CAP 0xfd0000 |
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#define IDT_ERR_CAP_LOG_OVERWR 0x00000004 |
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#define IDT_ERR_RD 0xfd0004 |
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#define IDT_DEFAULT_ROUTE 0xde |
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#define IDT_NO_ROUTE 0xdf |
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static int |
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idtg2_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount, |
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u16 table, u16 route_destid, u8 route_port) |
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{ |
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/* |
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* Select routing table to update |
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*/ |
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if (table == RIO_GLOBAL_TABLE) |
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table = 0; |
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else |
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table++; |
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if (route_port == RIO_INVALID_ROUTE) |
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route_port = IDT_DEFAULT_ROUTE; |
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rio_mport_write_config_32(mport, destid, hopcount, |
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LOCAL_RTE_CONF_DESTID_SEL, table); |
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/* |
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* Program destination port for the specified destID |
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*/ |
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rio_mport_write_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_DESTID_SEL_CSR, |
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(u32)route_destid); |
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rio_mport_write_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_PORT_SEL_CSR, |
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(u32)route_port); |
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udelay(10); |
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return 0; |
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} |
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static int |
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idtg2_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount, |
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u16 table, u16 route_destid, u8 *route_port) |
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{ |
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u32 result; |
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/* |
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* Select routing table to read |
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*/ |
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if (table == RIO_GLOBAL_TABLE) |
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table = 0; |
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else |
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table++; |
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rio_mport_write_config_32(mport, destid, hopcount, |
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LOCAL_RTE_CONF_DESTID_SEL, table); |
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rio_mport_write_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_DESTID_SEL_CSR, |
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route_destid); |
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rio_mport_read_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_PORT_SEL_CSR, &result); |
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if (IDT_DEFAULT_ROUTE == (u8)result || IDT_NO_ROUTE == (u8)result) |
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*route_port = RIO_INVALID_ROUTE; |
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else |
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*route_port = (u8)result; |
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return 0; |
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} |
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static int |
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idtg2_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount, |
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u16 table) |
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{ |
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u32 i; |
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/* |
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* Select routing table to read |
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*/ |
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if (table == RIO_GLOBAL_TABLE) |
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table = 0; |
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else |
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table++; |
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rio_mport_write_config_32(mport, destid, hopcount, |
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LOCAL_RTE_CONF_DESTID_SEL, table); |
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for (i = RIO_STD_RTE_CONF_EXTCFGEN; |
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i <= (RIO_STD_RTE_CONF_EXTCFGEN | 0xff);) { |
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rio_mport_write_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_DESTID_SEL_CSR, i); |
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rio_mport_write_config_32(mport, destid, hopcount, |
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RIO_STD_RTE_CONF_PORT_SEL_CSR, |
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(IDT_DEFAULT_ROUTE << 24) | (IDT_DEFAULT_ROUTE << 16) | |
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(IDT_DEFAULT_ROUTE << 8) | IDT_DEFAULT_ROUTE); |
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i += 4; |
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} |
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return 0; |
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} |
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static int |
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idtg2_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount, |
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u8 sw_domain) |
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{ |
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/* |
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* Switch domain configuration operates only at global level |
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*/ |
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rio_mport_write_config_32(mport, destid, hopcount, |
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IDT_RIO_DOMAIN, (u32)sw_domain); |
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return 0; |
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} |
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static int |
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idtg2_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount, |
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u8 *sw_domain) |
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{ |
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u32 regval; |
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/* |
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* Switch domain configuration operates only at global level |
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*/ |
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rio_mport_read_config_32(mport, destid, hopcount, |
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IDT_RIO_DOMAIN, ®val); |
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*sw_domain = (u8)(regval & 0xff); |
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return 0; |
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} |
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static int |
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idtg2_em_init(struct rio_dev *rdev) |
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{ |
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u32 regval; |
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int i, tmp; |
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/* |
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* This routine performs device-specific initialization only. |
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* All standard EM configuration should be performed at upper level. |
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*/ |
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pr_debug("RIO: %s [%d:%d]\n", __func__, rdev->destid, rdev->hopcount); |
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/* Set Port-Write info CSR: PRIO=3 and CRF=1 */ |
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rio_write_config_32(rdev, IDT_PW_INFO_CSR, 0x0000e000); |
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/* |
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* Configure LT LAYER error reporting. |
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*/ |
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/* Enable standard (RIO.p8) error reporting */ |
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rio_write_config_32(rdev, IDT_LT_ERR_REPORT_EN, |
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REM_LTL_ERR_ILLTRAN | REM_LTL_ERR_UNSOLR | |
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REM_LTL_ERR_UNSUPTR); |
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/* Use Port-Writes for LT layer error reporting. |
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* Enable per-port reset |
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*/ |
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rio_read_config_32(rdev, IDT_DEV_CTRL_1, ®val); |
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rio_write_config_32(rdev, IDT_DEV_CTRL_1, |
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regval | IDT_DEV_CTRL_1_GENPW | IDT_DEV_CTRL_1_PRSTBEH); |
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/* |
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* Configure PORT error reporting. |
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*/ |
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/* Report all RIO.p8 errors supported by device */ |
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rio_write_config_32(rdev, IDT_PORT_ERR_REPORT_EN_BC, 0x807e8037); |
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/* Configure reporting of implementation specific errors/events */ |
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rio_write_config_32(rdev, IDT_PORT_ISERR_REPORT_EN_BC, |
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IDT_PORT_INIT_TX_ACQUIRED); |
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/* Use Port-Writes for port error reporting and enable error logging */ |
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tmp = RIO_GET_TOTAL_PORTS(rdev->swpinfo); |
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for (i = 0; i < tmp; i++) { |
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rio_read_config_32(rdev, IDT_PORT_OPS(i), ®val); |
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rio_write_config_32(rdev, |
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IDT_PORT_OPS(i), regval | IDT_PORT_OPS_GENPW | |
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IDT_PORT_OPS_PL_ELOG | |
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IDT_PORT_OPS_LL_ELOG | |
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IDT_PORT_OPS_LT_ELOG); |
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} |
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/* Overwrite error log if full */ |
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rio_write_config_32(rdev, IDT_ERR_CAP, IDT_ERR_CAP_LOG_OVERWR); |
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/* |
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* Configure LANE error reporting. |
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*/ |
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/* Disable line error reporting */ |
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rio_write_config_32(rdev, IDT_LANE_ERR_REPORT_EN_BC, 0); |
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/* Use Port-Writes for lane error reporting (when enabled) |
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* (do per-lane update because lanes may have different configuration) |
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*/ |
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tmp = (rdev->did == RIO_DID_IDTCPS1848) ? 48 : 16; |
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for (i = 0; i < tmp; i++) { |
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rio_read_config_32(rdev, IDT_LANE_CTRL(i), ®val); |
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rio_write_config_32(rdev, IDT_LANE_CTRL(i), |
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regval | IDT_LANE_CTRL_GENPW); |
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} |
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/* |
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* Configure AUX error reporting. |
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*/ |
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/* Disable JTAG and I2C Error capture */ |
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rio_write_config_32(rdev, IDT_AUX_PORT_ERR_CAP_EN, 0); |
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/* Disable JTAG and I2C Error reporting/logging */ |
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rio_write_config_32(rdev, IDT_AUX_ERR_REPORT_EN, 0); |
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/* Disable Port-Write notification from JTAG */ |
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rio_write_config_32(rdev, IDT_JTAG_CTRL, 0); |
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/* Disable Port-Write notification from I2C */ |
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rio_read_config_32(rdev, IDT_I2C_MCTRL, ®val); |
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rio_write_config_32(rdev, IDT_I2C_MCTRL, regval & ~IDT_I2C_MCTRL_GENPW); |
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/* |
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* Configure CFG_BLK error reporting. |
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*/ |
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/* Disable Configuration Block error capture */ |
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rio_write_config_32(rdev, IDT_CFGBLK_ERR_CAPTURE_EN, 0); |
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/* Disable Port-Writes for Configuration Block error reporting */ |
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rio_read_config_32(rdev, IDT_CFGBLK_ERR_REPORT, ®val); |
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rio_write_config_32(rdev, IDT_CFGBLK_ERR_REPORT, |
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regval & ~IDT_CFGBLK_ERR_REPORT_GENPW); |
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/* set TVAL = ~50us */ |
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rio_write_config_32(rdev, |
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rdev->phys_efptr + RIO_PORT_LINKTO_CTL_CSR, 0x8e << 8); |
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return 0; |
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} |
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static int |
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idtg2_em_handler(struct rio_dev *rdev, u8 portnum) |
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{ |
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u32 regval, em_perrdet, em_ltlerrdet; |
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rio_read_config_32(rdev, |
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rdev->em_efptr + RIO_EM_LTL_ERR_DETECT, &em_ltlerrdet); |
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if (em_ltlerrdet) { |
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/* Service Logical/Transport Layer Error(s) */ |
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if (em_ltlerrdet & REM_LTL_ERR_IMPSPEC) { |
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/* Implementation specific error reported */ |
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rio_read_config_32(rdev, |
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IDT_ISLTL_ADDRESS_CAP, ®val); |
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pr_debug("RIO: %s Implementation Specific LTL errors" \ |
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" 0x%x @(0x%x)\n", |
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rio_name(rdev), em_ltlerrdet, regval); |
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/* Clear implementation specific address capture CSR */ |
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rio_write_config_32(rdev, IDT_ISLTL_ADDRESS_CAP, 0); |
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} |
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} |
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rio_read_config_32(rdev, |
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rdev->em_efptr + RIO_EM_PN_ERR_DETECT(portnum), &em_perrdet); |
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if (em_perrdet) { |
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/* Service Port-Level Error(s) */ |
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if (em_perrdet & REM_PED_IMPL_SPEC) { |
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/* Implementation Specific port error reported */ |
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/* Get IS errors reported */ |
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rio_read_config_32(rdev, |
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IDT_PORT_ISERR_DET(portnum), ®val); |
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pr_debug("RIO: %s Implementation Specific Port" \ |
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" errors 0x%x\n", rio_name(rdev), regval); |
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/* Clear all implementation specific events */ |
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rio_write_config_32(rdev, |
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IDT_PORT_ISERR_DET(portnum), 0); |
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} |
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} |
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return 0; |
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} |
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static ssize_t |
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idtg2_show_errlog(struct device *dev, struct device_attribute *attr, char *buf) |
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{ |
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struct rio_dev *rdev = to_rio_dev(dev); |
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ssize_t len = 0; |
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u32 regval; |
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while (!rio_read_config_32(rdev, IDT_ERR_RD, ®val)) { |
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if (!regval) /* 0 = end of log */ |
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break; |
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len += snprintf(buf + len, PAGE_SIZE - len, |
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"%08x\n", regval); |
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if (len >= (PAGE_SIZE - 10)) |
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break; |
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} |
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return len; |
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} |
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static DEVICE_ATTR(errlog, S_IRUGO, idtg2_show_errlog, NULL); |
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static int idtg2_sysfs(struct rio_dev *rdev, bool create) |
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{ |
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struct device *dev = &rdev->dev; |
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int err = 0; |
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if (create) { |
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/* Initialize sysfs entries */ |
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err = device_create_file(dev, &dev_attr_errlog); |
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if (err) |
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dev_err(dev, "Unable create sysfs errlog file\n"); |
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} else |
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device_remove_file(dev, &dev_attr_errlog); |
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return err; |
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} |
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static struct rio_switch_ops idtg2_switch_ops = { |
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.owner = THIS_MODULE, |
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.add_entry = idtg2_route_add_entry, |
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.get_entry = idtg2_route_get_entry, |
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.clr_table = idtg2_route_clr_table, |
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.set_domain = idtg2_set_domain, |
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.get_domain = idtg2_get_domain, |
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.em_init = idtg2_em_init, |
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.em_handle = idtg2_em_handler, |
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}; |
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static int idtg2_probe(struct rio_dev *rdev, const struct rio_device_id *id) |
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{ |
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pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); |
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spin_lock(&rdev->rswitch->lock); |
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if (rdev->rswitch->ops) { |
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spin_unlock(&rdev->rswitch->lock); |
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return -EINVAL; |
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} |
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rdev->rswitch->ops = &idtg2_switch_ops; |
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if (rdev->do_enum) { |
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/* Ensure that default routing is disabled on startup */ |
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rio_write_config_32(rdev, |
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RIO_STD_RTE_DEFAULT_PORT, IDT_NO_ROUTE); |
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} |
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spin_unlock(&rdev->rswitch->lock); |
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/* Create device-specific sysfs attributes */ |
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idtg2_sysfs(rdev, true); |
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return 0; |
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} |
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static void idtg2_remove(struct rio_dev *rdev) |
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{ |
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pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev)); |
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spin_lock(&rdev->rswitch->lock); |
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if (rdev->rswitch->ops != &idtg2_switch_ops) { |
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spin_unlock(&rdev->rswitch->lock); |
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return; |
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} |
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rdev->rswitch->ops = NULL; |
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spin_unlock(&rdev->rswitch->lock); |
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/* Remove device-specific sysfs attributes */ |
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idtg2_sysfs(rdev, false); |
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} |
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static const struct rio_device_id idtg2_id_table[] = { |
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{RIO_DEVICE(RIO_DID_IDTCPS1848, RIO_VID_IDT)}, |
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{RIO_DEVICE(RIO_DID_IDTCPS1616, RIO_VID_IDT)}, |
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{RIO_DEVICE(RIO_DID_IDTVPS1616, RIO_VID_IDT)}, |
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{RIO_DEVICE(RIO_DID_IDTSPS1616, RIO_VID_IDT)}, |
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{RIO_DEVICE(RIO_DID_IDTCPS1432, RIO_VID_IDT)}, |
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{ 0, } /* terminate list */ |
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}; |
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static struct rio_driver idtg2_driver = { |
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.name = "idt_gen2", |
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.id_table = idtg2_id_table, |
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.probe = idtg2_probe, |
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.remove = idtg2_remove, |
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}; |
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static int __init idtg2_init(void) |
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{ |
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return rio_register_driver(&idtg2_driver); |
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} |
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static void __exit idtg2_exit(void) |
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{ |
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pr_debug("RIO: %s\n", __func__); |
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rio_unregister_driver(&idtg2_driver); |
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pr_debug("RIO: %s done\n", __func__); |
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} |
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device_initcall(idtg2_init); |
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module_exit(idtg2_exit); |
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MODULE_DESCRIPTION("IDT CPS Gen.2 Serial RapidIO switch family driver"); |
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MODULE_AUTHOR("Integrated Device Technology, Inc."); |
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MODULE_LICENSE("GPL");
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