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715 lines
19 KiB
715 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) STMicroelectronics 2016 |
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* |
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* Author: Gerald Baeza <[email protected]> |
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* |
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* Inspired by timer-stm32.c from Maxime Coquelin |
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* pwm-atmel.c from Bo Shen |
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*/ |
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|
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#include <linux/bitfield.h> |
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#include <linux/mfd/stm32-timers.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#define CCMR_CHANNEL_SHIFT 8 |
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#define CCMR_CHANNEL_MASK 0xFF |
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#define MAX_BREAKINPUT 2 |
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struct stm32_breakinput { |
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u32 index; |
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u32 level; |
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u32 filter; |
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}; |
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struct stm32_pwm { |
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struct pwm_chip chip; |
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struct mutex lock; /* protect pwm config/enable */ |
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struct clk *clk; |
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struct regmap *regmap; |
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u32 max_arr; |
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bool have_complementary_output; |
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struct stm32_breakinput breakinputs[MAX_BREAKINPUT]; |
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unsigned int num_breakinputs; |
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u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ |
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}; |
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static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct stm32_pwm, chip); |
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} |
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static u32 active_channels(struct stm32_pwm *dev) |
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{ |
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u32 ccer; |
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regmap_read(dev->regmap, TIM_CCER, &ccer); |
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return ccer & TIM_CCER_CCXE; |
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} |
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static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value) |
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{ |
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switch (ch) { |
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case 0: |
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return regmap_write(dev->regmap, TIM_CCR1, value); |
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case 1: |
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return regmap_write(dev->regmap, TIM_CCR2, value); |
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case 2: |
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return regmap_write(dev->regmap, TIM_CCR3, value); |
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case 3: |
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return regmap_write(dev->regmap, TIM_CCR4, value); |
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} |
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return -EINVAL; |
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} |
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#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) |
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#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) |
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#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) |
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#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) |
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/* |
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* Capture using PWM input mode: |
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* ___ ___ |
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* TI[1, 2, 3 or 4]: ........._| |________| |
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* ^0 ^1 ^2 |
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* . . . |
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* . . XXXXX |
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* . . XXXXX | |
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* . XXXXX . | |
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* XXXXX . . | |
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* COUNTER: ______XXXXX . . . |_XXX |
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* start^ . . . ^stop |
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* . . . . |
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* v v . v |
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* v |
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* CCR1/CCR3: tx..........t0...........t2 |
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* CCR2/CCR4: tx..............t1......... |
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* |
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* DMA burst transfer: | | |
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* v v |
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* DMA buffer: { t0, tx } { t2, t1 } |
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* DMA done: ^ |
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* |
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* 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
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* + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) |
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* 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 |
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* 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 |
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* + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) |
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* |
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* DMA done, compute: |
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* - Period = t2 - t0 |
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* - Duty cycle = t1 - t0 |
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*/ |
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static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm, |
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unsigned long tmo_ms, u32 *raw_prd, |
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u32 *raw_dty) |
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{ |
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struct device *parent = priv->chip.dev->parent; |
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enum stm32_timers_dmas dma_id; |
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u32 ccen, ccr; |
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int ret; |
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/* Ensure registers have been updated, enable counter and capture */ |
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); |
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); |
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/* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ |
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dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; |
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ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; |
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ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; |
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regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen); |
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/* |
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* Timer DMA burst mode. Request 2 registers, 2 bursts, to get both |
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* CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. |
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* We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } |
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* or { CCR3, CCR4 }, { CCR3, CCR4 } |
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*/ |
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ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, |
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2, tmo_ms); |
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if (ret) |
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goto stop; |
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/* Period: t2 - t0 (take care of counter overflow) */ |
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if (priv->capture[0] <= priv->capture[2]) |
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*raw_prd = priv->capture[2] - priv->capture[0]; |
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else |
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*raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; |
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/* Duty cycle capture requires at least two capture units */ |
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if (pwm->chip->npwm < 2) |
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*raw_dty = 0; |
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else if (priv->capture[0] <= priv->capture[3]) |
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*raw_dty = priv->capture[3] - priv->capture[0]; |
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else |
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*raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; |
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if (*raw_dty > *raw_prd) { |
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/* |
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* Race beetween PWM input and DMA: it may happen |
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* falling edge triggers new capture on TI2/4 before DMA |
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* had a chance to read CCR2/4. It means capture[1] |
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* contains period + duty_cycle. So, subtract period. |
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*/ |
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*raw_dty -= *raw_prd; |
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} |
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stop: |
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regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0); |
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); |
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return ret; |
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} |
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static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
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struct pwm_capture *result, unsigned long tmo_ms) |
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{ |
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
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unsigned long long prd, div, dty; |
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unsigned long rate; |
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unsigned int psc = 0, icpsc, scale; |
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u32 raw_prd = 0, raw_dty = 0; |
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int ret = 0; |
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mutex_lock(&priv->lock); |
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if (active_channels(priv)) { |
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ret = -EBUSY; |
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goto unlock; |
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} |
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ret = clk_enable(priv->clk); |
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if (ret) { |
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dev_err(priv->chip.dev, "failed to enable counter clock\n"); |
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goto unlock; |
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} |
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rate = clk_get_rate(priv->clk); |
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if (!rate) { |
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ret = -EINVAL; |
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goto clk_dis; |
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} |
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/* prescaler: fit timeout window provided by upper layer */ |
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div = (unsigned long long)rate * (unsigned long long)tmo_ms; |
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do_div(div, MSEC_PER_SEC); |
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prd = div; |
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while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { |
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psc++; |
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div = prd; |
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do_div(div, psc + 1); |
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} |
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regmap_write(priv->regmap, TIM_ARR, priv->max_arr); |
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regmap_write(priv->regmap, TIM_PSC, psc); |
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/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ |
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regmap_update_bits(priv->regmap, |
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pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
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TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? |
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TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : |
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TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); |
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/* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ |
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regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? |
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TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? |
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TIM_CCER_CC2P : TIM_CCER_CC4P); |
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ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); |
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if (ret) |
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goto stop; |
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/* |
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* Got a capture. Try to improve accuracy at high rates: |
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* - decrease counter clock prescaler, scale up to max rate. |
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* - use input prescaler, capture once every /2 /4 or /8 edges. |
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*/ |
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if (raw_prd) { |
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u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ |
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scale = max_arr / min(max_arr, raw_prd); |
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} else { |
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scale = priv->max_arr; /* bellow resolution, use max scale */ |
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} |
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if (psc && scale > 1) { |
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/* 2nd measure with new scale */ |
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psc /= scale; |
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regmap_write(priv->regmap, TIM_PSC, psc); |
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ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, |
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&raw_dty); |
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if (ret) |
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goto stop; |
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} |
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/* Compute intermediate period not to exceed timeout at low rates */ |
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prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
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do_div(prd, rate); |
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for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { |
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/* input prescaler: also keep arbitrary margin */ |
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if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) |
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break; |
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if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) |
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break; |
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} |
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if (!icpsc) |
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goto done; |
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/* Last chance to improve period accuracy, using input prescaler */ |
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regmap_update_bits(priv->regmap, |
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pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, |
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TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, |
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FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | |
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FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); |
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ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); |
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if (ret) |
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goto stop; |
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if (raw_dty >= (raw_prd >> icpsc)) { |
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/* |
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* We may fall here using input prescaler, when input |
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* capture starts on high side (before falling edge). |
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* Example with icpsc to capture on each 4 events: |
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* |
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* start 1st capture 2nd capture |
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* v v v |
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* ___ _____ _____ _____ _____ ____ |
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* TI1..4 |__| |__| |__| |__| |__| |
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* v v . . . . . v v |
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* icpsc1/3: . 0 . 1 . 2 . 3 . 0 |
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* icpsc2/4: 0 1 2 3 0 |
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* v v v v |
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* CCR1/3 ......t0..............................t2 |
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* CCR2/4 ..t1..............................t1'... |
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* . . . |
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* Capture0: .<----------------------------->. |
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* Capture1: .<-------------------------->. . |
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* . . . |
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* Period: .<------> . . |
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* Low side: .<>. |
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* |
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* Result: |
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* - Period = Capture0 / icpsc |
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* - Duty = Period - Low side = Period - (Capture0 - Capture1) |
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*/ |
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raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); |
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} |
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done: |
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prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; |
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result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); |
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dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; |
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result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); |
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stop: |
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regmap_write(priv->regmap, TIM_CCER, 0); |
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regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); |
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regmap_write(priv->regmap, TIM_PSC, 0); |
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clk_dis: |
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clk_disable(priv->clk); |
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unlock: |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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static int stm32_pwm_config(struct stm32_pwm *priv, int ch, |
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int duty_ns, int period_ns) |
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{ |
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unsigned long long prd, div, dty; |
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unsigned int prescaler = 0; |
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u32 ccmr, mask, shift; |
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/* Period and prescaler values depends on clock rate */ |
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div = (unsigned long long)clk_get_rate(priv->clk) * period_ns; |
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do_div(div, NSEC_PER_SEC); |
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prd = div; |
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while (div > priv->max_arr) { |
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prescaler++; |
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div = prd; |
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do_div(div, prescaler + 1); |
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} |
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prd = div; |
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if (prescaler > MAX_TIM_PSC) |
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return -EINVAL; |
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/* |
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* All channels share the same prescaler and counter so when two |
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* channels are active at the same time we can't change them |
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*/ |
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if (active_channels(priv) & ~(1 << ch * 4)) { |
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u32 psc, arr; |
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regmap_read(priv->regmap, TIM_PSC, &psc); |
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regmap_read(priv->regmap, TIM_ARR, &arr); |
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if ((psc != prescaler) || (arr != prd - 1)) |
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return -EBUSY; |
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} |
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regmap_write(priv->regmap, TIM_PSC, prescaler); |
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regmap_write(priv->regmap, TIM_ARR, prd - 1); |
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); |
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/* Calculate the duty cycles */ |
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dty = prd * duty_ns; |
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do_div(dty, period_ns); |
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write_ccrx(priv, ch, dty); |
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/* Configure output mode */ |
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shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT; |
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ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift; |
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mask = CCMR_CHANNEL_MASK << shift; |
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if (ch < 2) |
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regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr); |
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else |
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regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr); |
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regmap_update_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE, TIM_BDTR_MOE); |
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return 0; |
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} |
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static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch, |
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enum pwm_polarity polarity) |
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{ |
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u32 mask; |
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mask = TIM_CCER_CC1P << (ch * 4); |
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if (priv->have_complementary_output) |
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mask |= TIM_CCER_CC1NP << (ch * 4); |
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regmap_update_bits(priv->regmap, TIM_CCER, mask, |
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polarity == PWM_POLARITY_NORMAL ? 0 : mask); |
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return 0; |
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} |
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static int stm32_pwm_enable(struct stm32_pwm *priv, int ch) |
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{ |
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u32 mask; |
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int ret; |
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ret = clk_enable(priv->clk); |
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if (ret) |
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return ret; |
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/* Enable channel */ |
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mask = TIM_CCER_CC1E << (ch * 4); |
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if (priv->have_complementary_output) |
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mask |= TIM_CCER_CC1NE << (ch * 4); |
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regmap_update_bits(priv->regmap, TIM_CCER, mask, mask); |
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/* Make sure that registers are updated */ |
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); |
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/* Enable controller */ |
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); |
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return 0; |
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} |
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static void stm32_pwm_disable(struct stm32_pwm *priv, int ch) |
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{ |
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u32 mask; |
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/* Disable channel */ |
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mask = TIM_CCER_CC1E << (ch * 4); |
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if (priv->have_complementary_output) |
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mask |= TIM_CCER_CC1NE << (ch * 4); |
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regmap_update_bits(priv->regmap, TIM_CCER, mask, 0); |
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/* When all channels are disabled, we can disable the controller */ |
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if (!active_channels(priv)) |
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); |
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clk_disable(priv->clk); |
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} |
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static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
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const struct pwm_state *state) |
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{ |
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bool enabled; |
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
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int ret; |
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enabled = pwm->state.enabled; |
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if (enabled && !state->enabled) { |
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stm32_pwm_disable(priv, pwm->hwpwm); |
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return 0; |
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} |
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if (state->polarity != pwm->state.polarity) |
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stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity); |
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ret = stm32_pwm_config(priv, pwm->hwpwm, |
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state->duty_cycle, state->period); |
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if (ret) |
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return ret; |
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if (!enabled && state->enabled) |
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ret = stm32_pwm_enable(priv, pwm->hwpwm); |
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return ret; |
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} |
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static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, |
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const struct pwm_state *state) |
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{ |
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struct stm32_pwm *priv = to_stm32_pwm_dev(chip); |
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int ret; |
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/* protect common prescaler for all active channels */ |
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mutex_lock(&priv->lock); |
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ret = stm32_pwm_apply(chip, pwm, state); |
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mutex_unlock(&priv->lock); |
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return ret; |
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} |
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static const struct pwm_ops stm32pwm_ops = { |
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.owner = THIS_MODULE, |
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.apply = stm32_pwm_apply_locked, |
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.capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL, |
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}; |
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static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, |
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const struct stm32_breakinput *bi) |
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{ |
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u32 shift = TIM_BDTR_BKF_SHIFT(bi->index); |
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u32 bke = TIM_BDTR_BKE(bi->index); |
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u32 bkp = TIM_BDTR_BKP(bi->index); |
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u32 bkf = TIM_BDTR_BKF(bi->index); |
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u32 mask = bkf | bkp | bke; |
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u32 bdtr; |
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bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke; |
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if (bi->level) |
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bdtr |= bkp; |
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regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr); |
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regmap_read(priv->regmap, TIM_BDTR, &bdtr); |
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return (bdtr & bke) ? 0 : -EINVAL; |
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} |
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static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv) |
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{ |
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unsigned int i; |
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int ret; |
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for (i = 0; i < priv->num_breakinputs; i++) { |
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ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]); |
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if (ret < 0) |
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return ret; |
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} |
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|
|
return 0; |
|
} |
|
|
|
static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv, |
|
struct device_node *np) |
|
{ |
|
int nb, ret, array_size; |
|
unsigned int i; |
|
|
|
nb = of_property_count_elems_of_size(np, "st,breakinput", |
|
sizeof(struct stm32_breakinput)); |
|
|
|
/* |
|
* Because "st,breakinput" parameter is optional do not make probe |
|
* failed if it doesn't exist. |
|
*/ |
|
if (nb <= 0) |
|
return 0; |
|
|
|
if (nb > MAX_BREAKINPUT) |
|
return -EINVAL; |
|
|
|
priv->num_breakinputs = nb; |
|
array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32); |
|
ret = of_property_read_u32_array(np, "st,breakinput", |
|
(u32 *)priv->breakinputs, array_size); |
|
if (ret) |
|
return ret; |
|
|
|
for (i = 0; i < priv->num_breakinputs; i++) { |
|
if (priv->breakinputs[i].index > 1 || |
|
priv->breakinputs[i].level > 1 || |
|
priv->breakinputs[i].filter > 15) |
|
return -EINVAL; |
|
} |
|
|
|
return stm32_pwm_apply_breakinputs(priv); |
|
} |
|
|
|
static void stm32_pwm_detect_complementary(struct stm32_pwm *priv) |
|
{ |
|
u32 ccer; |
|
|
|
/* |
|
* If complementary bit doesn't exist writing 1 will have no |
|
* effect so we can detect it. |
|
*/ |
|
regmap_update_bits(priv->regmap, |
|
TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE); |
|
regmap_read(priv->regmap, TIM_CCER, &ccer); |
|
regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0); |
|
|
|
priv->have_complementary_output = (ccer != 0); |
|
} |
|
|
|
static int stm32_pwm_detect_channels(struct stm32_pwm *priv) |
|
{ |
|
u32 ccer; |
|
int npwm = 0; |
|
|
|
/* |
|
* If channels enable bits don't exist writing 1 will have no |
|
* effect so we can detect and count them. |
|
*/ |
|
regmap_update_bits(priv->regmap, |
|
TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE); |
|
regmap_read(priv->regmap, TIM_CCER, &ccer); |
|
regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0); |
|
|
|
if (ccer & TIM_CCER_CC1E) |
|
npwm++; |
|
|
|
if (ccer & TIM_CCER_CC2E) |
|
npwm++; |
|
|
|
if (ccer & TIM_CCER_CC3E) |
|
npwm++; |
|
|
|
if (ccer & TIM_CCER_CC4E) |
|
npwm++; |
|
|
|
return npwm; |
|
} |
|
|
|
static int stm32_pwm_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct device_node *np = dev->of_node; |
|
struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); |
|
struct stm32_pwm *priv; |
|
int ret; |
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
mutex_init(&priv->lock); |
|
priv->regmap = ddata->regmap; |
|
priv->clk = ddata->clk; |
|
priv->max_arr = ddata->max_arr; |
|
|
|
if (!priv->regmap || !priv->clk) |
|
return -EINVAL; |
|
|
|
ret = stm32_pwm_probe_breakinputs(priv, np); |
|
if (ret) |
|
return ret; |
|
|
|
stm32_pwm_detect_complementary(priv); |
|
|
|
priv->chip.dev = dev; |
|
priv->chip.ops = &stm32pwm_ops; |
|
priv->chip.npwm = stm32_pwm_detect_channels(priv); |
|
|
|
ret = pwmchip_add(&priv->chip); |
|
if (ret < 0) |
|
return ret; |
|
|
|
platform_set_drvdata(pdev, priv); |
|
|
|
return 0; |
|
} |
|
|
|
static int stm32_pwm_remove(struct platform_device *pdev) |
|
{ |
|
struct stm32_pwm *priv = platform_get_drvdata(pdev); |
|
unsigned int i; |
|
|
|
for (i = 0; i < priv->chip.npwm; i++) |
|
pwm_disable(&priv->chip.pwms[i]); |
|
|
|
pwmchip_remove(&priv->chip); |
|
|
|
return 0; |
|
} |
|
|
|
static int __maybe_unused stm32_pwm_suspend(struct device *dev) |
|
{ |
|
struct stm32_pwm *priv = dev_get_drvdata(dev); |
|
unsigned int i; |
|
u32 ccer, mask; |
|
|
|
/* Look for active channels */ |
|
ccer = active_channels(priv); |
|
|
|
for (i = 0; i < priv->chip.npwm; i++) { |
|
mask = TIM_CCER_CC1E << (i * 4); |
|
if (ccer & mask) { |
|
dev_err(dev, "PWM %u still in use by consumer %s\n", |
|
i, priv->chip.pwms[i].label); |
|
return -EBUSY; |
|
} |
|
} |
|
|
|
return pinctrl_pm_select_sleep_state(dev); |
|
} |
|
|
|
static int __maybe_unused stm32_pwm_resume(struct device *dev) |
|
{ |
|
struct stm32_pwm *priv = dev_get_drvdata(dev); |
|
int ret; |
|
|
|
ret = pinctrl_pm_select_default_state(dev); |
|
if (ret) |
|
return ret; |
|
|
|
/* restore breakinput registers that may have been lost in low power */ |
|
return stm32_pwm_apply_breakinputs(priv); |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume); |
|
|
|
static const struct of_device_id stm32_pwm_of_match[] = { |
|
{ .compatible = "st,stm32-pwm", }, |
|
{ /* end node */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, stm32_pwm_of_match); |
|
|
|
static struct platform_driver stm32_pwm_driver = { |
|
.probe = stm32_pwm_probe, |
|
.remove = stm32_pwm_remove, |
|
.driver = { |
|
.name = "stm32-pwm", |
|
.of_match_table = stm32_pwm_of_match, |
|
.pm = &stm32_pwm_pm_ops, |
|
}, |
|
}; |
|
module_platform_driver(stm32_pwm_driver); |
|
|
|
MODULE_ALIAS("platform:stm32-pwm"); |
|
MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|