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205 lines
5.0 KiB
205 lines
5.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright 2014 Bart Tanghe <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#define PWM_CONTROL 0x000 |
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#define PWM_CONTROL_SHIFT(x) ((x) * 8) |
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#define PWM_CONTROL_MASK 0xff |
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#define PWM_MODE 0x80 /* set timer in PWM mode */ |
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#define PWM_ENABLE (1 << 0) |
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#define PWM_POLARITY (1 << 4) |
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#define PERIOD(x) (((x) * 0x10) + 0x10) |
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#define DUTY(x) (((x) * 0x10) + 0x14) |
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#define PERIOD_MIN 0x2 |
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struct bcm2835_pwm { |
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struct pwm_chip chip; |
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struct device *dev; |
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void __iomem *base; |
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struct clk *clk; |
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}; |
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static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct bcm2835_pwm, chip); |
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} |
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static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); |
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u32 value; |
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value = readl(pc->base + PWM_CONTROL); |
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value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); |
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value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); |
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writel(value, pc->base + PWM_CONTROL); |
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return 0; |
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} |
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static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); |
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u32 value; |
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value = readl(pc->base + PWM_CONTROL); |
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value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); |
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writel(value, pc->base + PWM_CONTROL); |
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} |
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static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
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const struct pwm_state *state) |
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{ |
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struct bcm2835_pwm *pc = to_bcm2835_pwm(chip); |
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unsigned long rate = clk_get_rate(pc->clk); |
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unsigned long long period_cycles; |
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u64 max_period; |
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u32 val; |
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if (!rate) { |
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dev_err(pc->dev, "failed to get clock rate\n"); |
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return -EINVAL; |
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} |
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/* |
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* period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC |
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* must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the |
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* multiplication period * rate doesn't overflow. |
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* To calculate the maximal possible period that guarantees the |
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* above inequality: |
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* |
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* round(period * rate / NSEC_PER_SEC) <= U32_MAX |
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* <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5 |
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* <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC |
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* <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate |
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* <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate |
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* <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1 |
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*/ |
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max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1; |
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if (state->period > max_period) |
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return -EINVAL; |
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/* set period */ |
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period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC); |
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/* don't accept a period that is too small */ |
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if (period_cycles < PERIOD_MIN) |
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return -EINVAL; |
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writel(period_cycles, pc->base + PERIOD(pwm->hwpwm)); |
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/* set duty cycle */ |
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val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC); |
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writel(val, pc->base + DUTY(pwm->hwpwm)); |
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/* set polarity */ |
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val = readl(pc->base + PWM_CONTROL); |
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if (state->polarity == PWM_POLARITY_NORMAL) |
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val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm)); |
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else |
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val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm); |
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/* enable/disable */ |
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if (state->enabled) |
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val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm); |
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else |
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val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm)); |
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writel(val, pc->base + PWM_CONTROL); |
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return 0; |
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} |
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static const struct pwm_ops bcm2835_pwm_ops = { |
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.request = bcm2835_pwm_request, |
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.free = bcm2835_pwm_free, |
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.apply = bcm2835_pwm_apply, |
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.owner = THIS_MODULE, |
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}; |
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static int bcm2835_pwm_probe(struct platform_device *pdev) |
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{ |
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struct bcm2835_pwm *pc; |
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int ret; |
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
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if (!pc) |
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return -ENOMEM; |
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pc->dev = &pdev->dev; |
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pc->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(pc->base)) |
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return PTR_ERR(pc->base); |
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pc->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(pc->clk)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), |
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"clock not found\n"); |
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ret = clk_prepare_enable(pc->clk); |
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if (ret) |
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return ret; |
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pc->chip.dev = &pdev->dev; |
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pc->chip.ops = &bcm2835_pwm_ops; |
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pc->chip.npwm = 2; |
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platform_set_drvdata(pdev, pc); |
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ret = pwmchip_add(&pc->chip); |
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if (ret < 0) |
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goto add_fail; |
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return 0; |
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add_fail: |
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clk_disable_unprepare(pc->clk); |
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return ret; |
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} |
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static int bcm2835_pwm_remove(struct platform_device *pdev) |
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{ |
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struct bcm2835_pwm *pc = platform_get_drvdata(pdev); |
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pwmchip_remove(&pc->chip); |
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clk_disable_unprepare(pc->clk); |
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return 0; |
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} |
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static const struct of_device_id bcm2835_pwm_of_match[] = { |
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{ .compatible = "brcm,bcm2835-pwm", }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match); |
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static struct platform_driver bcm2835_pwm_driver = { |
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.driver = { |
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.name = "bcm2835-pwm", |
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.of_match_table = bcm2835_pwm_of_match, |
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}, |
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.probe = bcm2835_pwm_probe, |
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.remove = bcm2835_pwm_remove, |
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}; |
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module_platform_driver(bcm2835_pwm_driver); |
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MODULE_AUTHOR("Bart Tanghe <[email protected]>"); |
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MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver"); |
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MODULE_LICENSE("GPL v2");
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