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710 lines
18 KiB
710 lines
18 KiB
/* |
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* SPEAr platform PLGPIO driver |
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* |
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* Copyright (C) 2012 ST Microelectronics |
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* Viresh Kumar <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/io.h> |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm.h> |
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#include <linux/spinlock.h> |
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|
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#define MAX_GPIO_PER_REG 32 |
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#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) |
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#define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \ |
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* sizeof(int *)) |
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|
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/* |
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* plgpio pins in all machines are not one to one mapped, bitwise with registers |
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* bits. These set of macros define register masks for which below functions |
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* (pin_to_offset and offset_to_pin) are required to be called. |
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*/ |
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#define PTO_ENB_REG 0x001 |
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#define PTO_WDATA_REG 0x002 |
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#define PTO_DIR_REG 0x004 |
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#define PTO_IE_REG 0x008 |
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#define PTO_RDATA_REG 0x010 |
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#define PTO_MIS_REG 0x020 |
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struct plgpio_regs { |
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u32 enb; /* enable register */ |
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u32 wdata; /* write data register */ |
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u32 dir; /* direction set register */ |
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u32 rdata; /* read data register */ |
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u32 ie; /* interrupt enable register */ |
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u32 mis; /* mask interrupt status register */ |
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u32 eit; /* edge interrupt type */ |
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}; |
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|
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/* |
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* struct plgpio: plgpio driver specific structure |
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* |
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* lock: lock for guarding gpio registers |
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* base: base address of plgpio block |
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* chip: gpio framework specific chip information structure |
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* p2o: function ptr for pin to offset conversion. This is required only for |
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* machines where mapping b/w pin and offset is not 1-to-1. |
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* o2p: function ptr for offset to pin conversion. This is required only for |
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* machines where mapping b/w pin and offset is not 1-to-1. |
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* p2o_regs: mask of registers for which p2o and o2p are applicable |
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* regs: register offsets |
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* csave_regs: context save registers for standby/sleep/hibernate cases |
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*/ |
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struct plgpio { |
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spinlock_t lock; |
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void __iomem *base; |
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struct clk *clk; |
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struct gpio_chip chip; |
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int (*p2o)(int pin); /* pin_to_offset */ |
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int (*o2p)(int offset); /* offset_to_pin */ |
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u32 p2o_regs; |
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struct plgpio_regs regs; |
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#ifdef CONFIG_PM_SLEEP |
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struct plgpio_regs *csave_regs; |
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#endif |
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}; |
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|
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/* register manipulation inline functions */ |
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static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg) |
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{ |
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u32 offset = PIN_OFFSET(pin); |
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void __iomem *reg_off = REG_OFFSET(base, reg, pin); |
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u32 val = readl_relaxed(reg_off); |
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return !!(val & (1 << offset)); |
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} |
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static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg) |
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{ |
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u32 offset = PIN_OFFSET(pin); |
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void __iomem *reg_off = REG_OFFSET(base, reg, pin); |
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u32 val = readl_relaxed(reg_off); |
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writel_relaxed(val | (1 << offset), reg_off); |
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} |
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static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg) |
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{ |
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u32 offset = PIN_OFFSET(pin); |
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void __iomem *reg_off = REG_OFFSET(base, reg, pin); |
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u32 val = readl_relaxed(reg_off); |
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writel_relaxed(val & ~(1 << offset), reg_off); |
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} |
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/* gpio framework specific routines */ |
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static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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unsigned long flags; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return -EINVAL; |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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return 0; |
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} |
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static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset, |
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int value) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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unsigned long flags; |
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unsigned dir_offset = offset, wdata_offset = offset, tmp; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) { |
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tmp = plgpio->p2o(offset); |
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if (tmp == -1) |
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return -EINVAL; |
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if (plgpio->p2o_regs & PTO_DIR_REG) |
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dir_offset = tmp; |
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if (plgpio->p2o_regs & PTO_WDATA_REG) |
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wdata_offset = tmp; |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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if (value) |
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plgpio_reg_set(plgpio->base, wdata_offset, |
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plgpio->regs.wdata); |
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else |
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plgpio_reg_reset(plgpio->base, wdata_offset, |
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plgpio->regs.wdata); |
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plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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return 0; |
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} |
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static int plgpio_get_value(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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if (offset >= chip->ngpio) |
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return -EINVAL; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return -EINVAL; |
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} |
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return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata); |
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} |
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static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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if (offset >= chip->ngpio) |
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return; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return; |
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} |
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if (value) |
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata); |
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else |
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata); |
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} |
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static int plgpio_request(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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int gpio = chip->base + offset; |
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unsigned long flags; |
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int ret = 0; |
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if (offset >= chip->ngpio) |
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return -EINVAL; |
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ret = pinctrl_gpio_request(gpio); |
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if (ret) |
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return ret; |
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if (!IS_ERR(plgpio->clk)) { |
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ret = clk_enable(plgpio->clk); |
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if (ret) |
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goto err0; |
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} |
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if (plgpio->regs.enb == -1) |
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return 0; |
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/* |
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* put gpio in IN mode before enabling it. This make enabling gpio safe |
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*/ |
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ret = plgpio_direction_input(chip, offset); |
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if (ret) |
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goto err1; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) { |
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ret = -EINVAL; |
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goto err1; |
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} |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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return 0; |
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err1: |
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if (!IS_ERR(plgpio->clk)) |
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clk_disable(plgpio->clk); |
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err0: |
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pinctrl_gpio_free(gpio); |
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return ret; |
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} |
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static void plgpio_free(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct plgpio *plgpio = gpiochip_get_data(chip); |
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int gpio = chip->base + offset; |
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unsigned long flags; |
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if (offset >= chip->ngpio) |
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return; |
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if (plgpio->regs.enb == -1) |
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goto disable_clk; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return; |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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disable_clk: |
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if (!IS_ERR(plgpio->clk)) |
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clk_disable(plgpio->clk); |
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pinctrl_gpio_free(gpio); |
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} |
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/* PLGPIO IRQ */ |
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static void plgpio_irq_disable(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct plgpio *plgpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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unsigned long flags; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return; |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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} |
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static void plgpio_irq_enable(struct irq_data *d) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct plgpio *plgpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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unsigned long flags; |
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/* get correct offset for "offset" pin */ |
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if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) { |
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offset = plgpio->p2o(offset); |
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if (offset == -1) |
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return; |
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} |
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spin_lock_irqsave(&plgpio->lock, flags); |
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plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie); |
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spin_unlock_irqrestore(&plgpio->lock, flags); |
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} |
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static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
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struct plgpio *plgpio = gpiochip_get_data(gc); |
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int offset = d->hwirq; |
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void __iomem *reg_off; |
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unsigned int supported_type = 0, val; |
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if (offset >= plgpio->chip.ngpio) |
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return -EINVAL; |
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if (plgpio->regs.eit == -1) |
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supported_type = IRQ_TYPE_LEVEL_HIGH; |
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else |
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supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
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if (!(trigger & supported_type)) |
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return -EINVAL; |
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if (plgpio->regs.eit == -1) |
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return 0; |
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reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); |
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val = readl_relaxed(reg_off); |
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offset = PIN_OFFSET(offset); |
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if (trigger & IRQ_TYPE_EDGE_RISING) |
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writel_relaxed(val | (1 << offset), reg_off); |
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else |
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writel_relaxed(val & ~(1 << offset), reg_off); |
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return 0; |
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} |
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static struct irq_chip plgpio_irqchip = { |
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.name = "PLGPIO", |
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.irq_enable = plgpio_irq_enable, |
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.irq_disable = plgpio_irq_disable, |
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.irq_set_type = plgpio_irq_set_type, |
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}; |
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static void plgpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
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struct plgpio *plgpio = gpiochip_get_data(gc); |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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int regs_count, count, pin, offset, i = 0; |
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unsigned long pending; |
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count = plgpio->chip.ngpio; |
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regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG); |
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chained_irq_enter(irqchip, desc); |
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/* check all plgpio MIS registers for a possible interrupt */ |
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for (; i < regs_count; i++) { |
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pending = readl_relaxed(plgpio->base + plgpio->regs.mis + |
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i * sizeof(int *)); |
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if (!pending) |
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continue; |
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/* clear interrupts */ |
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writel_relaxed(~pending, plgpio->base + plgpio->regs.mis + |
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i * sizeof(int *)); |
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/* |
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* clear extra bits in last register having gpios < MAX/REG |
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* ex: Suppose there are max 102 plgpios. then last register |
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* must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits |
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* so, we must not take other 28 bits into consideration for |
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* checking interrupt. so clear those bits. |
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*/ |
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count = count - i * MAX_GPIO_PER_REG; |
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if (count < MAX_GPIO_PER_REG) |
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pending &= (1 << count) - 1; |
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for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) { |
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/* get correct pin for "offset" */ |
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if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) { |
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pin = plgpio->o2p(offset); |
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if (pin == -1) |
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continue; |
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} else |
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pin = offset; |
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/* get correct irq line number */ |
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pin = i * MAX_GPIO_PER_REG + pin; |
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generic_handle_domain_irq(gc->irq.domain, pin); |
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} |
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} |
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chained_irq_exit(irqchip, desc); |
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} |
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/* |
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* pin to offset and offset to pin converter functions |
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* |
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* In spear310 there is inconsistency among bit positions in plgpio regiseters, |
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* for different plgpio pins. For example: for pin 27, bit offset is 23, pin |
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* 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1 |
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*/ |
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static int spear310_p2o(int pin) |
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{ |
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int offset = pin; |
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if (pin <= 27) |
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offset += 4; |
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else if (pin <= 33) |
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offset = -1; |
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else if (pin <= 97) |
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offset -= 2; |
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else if (pin <= 101) |
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offset = 101 - pin; |
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else |
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offset = -1; |
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return offset; |
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} |
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static int spear310_o2p(int offset) |
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{ |
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if (offset <= 3) |
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return 101 - offset; |
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else if (offset <= 31) |
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return offset - 4; |
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else |
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return offset + 2; |
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} |
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static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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int ret = -EINVAL; |
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u32 val; |
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if (of_machine_is_compatible("st,spear310")) { |
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plgpio->p2o = spear310_p2o; |
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plgpio->o2p = spear310_o2p; |
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plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG | |
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PTO_RDATA_REG | PTO_MIS_REG; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) { |
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plgpio->chip.ngpio = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid ngpio field\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val)) |
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plgpio->regs.enb = val; |
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else |
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plgpio->regs.enb = -1; |
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if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) { |
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plgpio->regs.wdata = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid wdata reg\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) { |
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plgpio->regs.dir = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid dir reg\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) { |
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plgpio->regs.ie = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid ie reg\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) { |
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plgpio->regs.rdata = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid rdata reg\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) { |
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plgpio->regs.mis = val; |
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} else { |
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dev_err(&pdev->dev, "DT: Invalid mis reg\n"); |
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goto end; |
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} |
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if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val)) |
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plgpio->regs.eit = val; |
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else |
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plgpio->regs.eit = -1; |
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return 0; |
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|
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end: |
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return ret; |
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} |
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static int plgpio_probe(struct platform_device *pdev) |
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{ |
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struct plgpio *plgpio; |
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int ret, irq; |
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plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL); |
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if (!plgpio) |
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return -ENOMEM; |
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plgpio->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(plgpio->base)) |
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return PTR_ERR(plgpio->base); |
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ret = plgpio_probe_dt(pdev, plgpio); |
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if (ret) { |
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dev_err(&pdev->dev, "DT probe failed\n"); |
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return ret; |
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} |
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plgpio->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(plgpio->clk)) |
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dev_warn(&pdev->dev, "clk_get() failed, work without it\n"); |
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|
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#ifdef CONFIG_PM_SLEEP |
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plgpio->csave_regs = devm_kcalloc(&pdev->dev, |
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DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), |
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sizeof(*plgpio->csave_regs), |
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GFP_KERNEL); |
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if (!plgpio->csave_regs) |
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return -ENOMEM; |
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#endif |
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platform_set_drvdata(pdev, plgpio); |
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spin_lock_init(&plgpio->lock); |
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|
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plgpio->chip.base = -1; |
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plgpio->chip.request = plgpio_request; |
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plgpio->chip.free = plgpio_free; |
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plgpio->chip.direction_input = plgpio_direction_input; |
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plgpio->chip.direction_output = plgpio_direction_output; |
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plgpio->chip.get = plgpio_get_value; |
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plgpio->chip.set = plgpio_set_value; |
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plgpio->chip.label = dev_name(&pdev->dev); |
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plgpio->chip.parent = &pdev->dev; |
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plgpio->chip.owner = THIS_MODULE; |
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plgpio->chip.of_node = pdev->dev.of_node; |
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|
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if (!IS_ERR(plgpio->clk)) { |
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ret = clk_prepare(plgpio->clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "clk prepare failed\n"); |
|
return ret; |
|
} |
|
} |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq > 0) { |
|
struct gpio_irq_chip *girq; |
|
|
|
girq = &plgpio->chip.irq; |
|
girq->chip = &plgpio_irqchip; |
|
girq->parent_handler = plgpio_irq_handler; |
|
girq->num_parents = 1; |
|
girq->parents = devm_kcalloc(&pdev->dev, 1, |
|
sizeof(*girq->parents), |
|
GFP_KERNEL); |
|
if (!girq->parents) |
|
return -ENOMEM; |
|
girq->parents[0] = irq; |
|
girq->default_type = IRQ_TYPE_NONE; |
|
girq->handler = handle_simple_irq; |
|
dev_info(&pdev->dev, "PLGPIO registering with IRQs\n"); |
|
} else { |
|
dev_info(&pdev->dev, "PLGPIO registering without IRQs\n"); |
|
} |
|
|
|
ret = gpiochip_add_data(&plgpio->chip, plgpio); |
|
if (ret) { |
|
dev_err(&pdev->dev, "unable to add gpio chip\n"); |
|
goto unprepare_clk; |
|
} |
|
|
|
return 0; |
|
|
|
unprepare_clk: |
|
if (!IS_ERR(plgpio->clk)) |
|
clk_unprepare(plgpio->clk); |
|
|
|
return ret; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int plgpio_suspend(struct device *dev) |
|
{ |
|
struct plgpio *plgpio = dev_get_drvdata(dev); |
|
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); |
|
void __iomem *off; |
|
|
|
for (i = 0; i < reg_count; i++) { |
|
off = plgpio->base + i * sizeof(int *); |
|
|
|
if (plgpio->regs.enb != -1) |
|
plgpio->csave_regs[i].enb = |
|
readl_relaxed(plgpio->regs.enb + off); |
|
if (plgpio->regs.eit != -1) |
|
plgpio->csave_regs[i].eit = |
|
readl_relaxed(plgpio->regs.eit + off); |
|
plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata + |
|
off); |
|
plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir + |
|
off); |
|
plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* This is used to correct the values in end registers. End registers contain |
|
* extra bits that might be used for other purpose in platform. So, we shouldn't |
|
* overwrite these bits. This macro, reads given register again, preserves other |
|
* bit values (non-plgpio bits), and retain captured value (plgpio bits). |
|
*/ |
|
#define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \ |
|
{ \ |
|
_tmp = readl_relaxed(plgpio->regs.__reg + _off); \ |
|
_tmp &= ~_mask; \ |
|
plgpio->csave_regs[i].__reg = \ |
|
_tmp | (plgpio->csave_regs[i].__reg & _mask); \ |
|
} |
|
|
|
static int plgpio_resume(struct device *dev) |
|
{ |
|
struct plgpio *plgpio = dev_get_drvdata(dev); |
|
int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG); |
|
void __iomem *off; |
|
u32 mask, tmp; |
|
|
|
for (i = 0; i < reg_count; i++) { |
|
off = plgpio->base + i * sizeof(int *); |
|
|
|
if (i == reg_count - 1) { |
|
mask = (1 << (plgpio->chip.ngpio - i * |
|
MAX_GPIO_PER_REG)) - 1; |
|
|
|
if (plgpio->regs.enb != -1) |
|
plgpio_prepare_reg(enb, off, mask, tmp); |
|
|
|
if (plgpio->regs.eit != -1) |
|
plgpio_prepare_reg(eit, off, mask, tmp); |
|
|
|
plgpio_prepare_reg(wdata, off, mask, tmp); |
|
plgpio_prepare_reg(dir, off, mask, tmp); |
|
plgpio_prepare_reg(ie, off, mask, tmp); |
|
} |
|
|
|
writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata + |
|
off); |
|
writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir + |
|
off); |
|
|
|
if (plgpio->regs.eit != -1) |
|
writel_relaxed(plgpio->csave_regs[i].eit, |
|
plgpio->regs.eit + off); |
|
|
|
writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off); |
|
|
|
if (plgpio->regs.enb != -1) |
|
writel_relaxed(plgpio->csave_regs[i].enb, |
|
plgpio->regs.enb + off); |
|
} |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume); |
|
|
|
static const struct of_device_id plgpio_of_match[] = { |
|
{ .compatible = "st,spear-plgpio" }, |
|
{} |
|
}; |
|
|
|
static struct platform_driver plgpio_driver = { |
|
.probe = plgpio_probe, |
|
.driver = { |
|
.name = "spear-plgpio", |
|
.pm = &plgpio_dev_pm_ops, |
|
.of_match_table = plgpio_of_match, |
|
}, |
|
}; |
|
|
|
static int __init plgpio_init(void) |
|
{ |
|
return platform_driver_register(&plgpio_driver); |
|
} |
|
subsys_initcall(plgpio_init);
|
|
|