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695 lines
19 KiB
695 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. |
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* Copyright (c) 2020 Linaro Ltd. |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/of.h> |
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#include <linux/pinctrl/pinconf-generic.h> |
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#include <linux/pinctrl/pinconf.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include "../core.h" |
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#include "../pinctrl-utils.h" |
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#define LPI_SLEW_RATE_CTL_REG 0xa000 |
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#define LPI_TLMM_REG_OFFSET 0x1000 |
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#define LPI_SLEW_RATE_MAX 0x03 |
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#define LPI_SLEW_BITS_SIZE 0x02 |
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#define LPI_SLEW_RATE_MASK GENMASK(1, 0) |
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#define LPI_GPIO_CFG_REG 0x00 |
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#define LPI_GPIO_PULL_MASK GENMASK(1, 0) |
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#define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2) |
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#define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6) |
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#define LPI_GPIO_OE_MASK BIT(9) |
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#define LPI_GPIO_VALUE_REG 0x04 |
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#define LPI_GPIO_VALUE_IN_MASK BIT(0) |
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#define LPI_GPIO_VALUE_OUT_MASK BIT(1) |
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#define LPI_GPIO_BIAS_DISABLE 0x0 |
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#define LPI_GPIO_PULL_DOWN 0x1 |
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#define LPI_GPIO_KEEPER 0x2 |
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#define LPI_GPIO_PULL_UP 0x3 |
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#define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1) |
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#define NO_SLEW -1 |
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#define LPI_FUNCTION(fname) \ |
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[LPI_MUX_##fname] = { \ |
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.name = #fname, \ |
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.groups = fname##_groups, \ |
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.ngroups = ARRAY_SIZE(fname##_groups), \ |
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} |
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#define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \ |
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{ \ |
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.name = "gpio" #id, \ |
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.pins = gpio##id##_pins, \ |
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.pin = id, \ |
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.slew_offset = soff, \ |
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.npins = ARRAY_SIZE(gpio##id##_pins), \ |
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.funcs = (int[]){ \ |
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LPI_MUX_gpio, \ |
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LPI_MUX_##f1, \ |
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LPI_MUX_##f2, \ |
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LPI_MUX_##f3, \ |
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LPI_MUX_##f4, \ |
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}, \ |
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.nfuncs = 5, \ |
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} |
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struct lpi_pingroup { |
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const char *name; |
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const unsigned int *pins; |
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unsigned int npins; |
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unsigned int pin; |
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/* Bit offset in slew register for SoundWire pins only */ |
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int slew_offset; |
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unsigned int *funcs; |
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unsigned int nfuncs; |
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}; |
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struct lpi_function { |
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const char *name; |
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const char * const *groups; |
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unsigned int ngroups; |
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}; |
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struct lpi_pinctrl_variant_data { |
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const struct pinctrl_pin_desc *pins; |
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int npins; |
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const struct lpi_pingroup *groups; |
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int ngroups; |
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const struct lpi_function *functions; |
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int nfunctions; |
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}; |
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#define MAX_LPI_NUM_CLKS 2 |
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struct lpi_pinctrl { |
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struct device *dev; |
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struct pinctrl_dev *ctrl; |
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struct gpio_chip chip; |
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struct pinctrl_desc desc; |
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char __iomem *tlmm_base; |
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char __iomem *slew_base; |
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struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; |
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struct mutex slew_access_lock; |
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const struct lpi_pinctrl_variant_data *data; |
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}; |
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/* sm8250 variant specific data */ |
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static const struct pinctrl_pin_desc sm8250_lpi_pins[] = { |
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PINCTRL_PIN(0, "gpio0"), |
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PINCTRL_PIN(1, "gpio1"), |
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PINCTRL_PIN(2, "gpio2"), |
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PINCTRL_PIN(3, "gpio3"), |
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PINCTRL_PIN(4, "gpio4"), |
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PINCTRL_PIN(5, "gpio5"), |
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PINCTRL_PIN(6, "gpio6"), |
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PINCTRL_PIN(7, "gpio7"), |
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PINCTRL_PIN(8, "gpio8"), |
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PINCTRL_PIN(9, "gpio9"), |
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PINCTRL_PIN(10, "gpio10"), |
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PINCTRL_PIN(11, "gpio11"), |
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PINCTRL_PIN(12, "gpio12"), |
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PINCTRL_PIN(13, "gpio13"), |
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}; |
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enum sm8250_lpi_functions { |
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LPI_MUX_dmic1_clk, |
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LPI_MUX_dmic1_data, |
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LPI_MUX_dmic2_clk, |
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LPI_MUX_dmic2_data, |
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LPI_MUX_dmic3_clk, |
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LPI_MUX_dmic3_data, |
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LPI_MUX_i2s1_clk, |
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LPI_MUX_i2s1_data, |
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LPI_MUX_i2s1_ws, |
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LPI_MUX_i2s2_clk, |
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LPI_MUX_i2s2_data, |
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LPI_MUX_i2s2_ws, |
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LPI_MUX_qua_mi2s_data, |
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LPI_MUX_qua_mi2s_sclk, |
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LPI_MUX_qua_mi2s_ws, |
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LPI_MUX_swr_rx_clk, |
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LPI_MUX_swr_rx_data, |
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LPI_MUX_swr_tx_clk, |
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LPI_MUX_swr_tx_data, |
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LPI_MUX_wsa_swr_clk, |
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LPI_MUX_wsa_swr_data, |
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LPI_MUX_gpio, |
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LPI_MUX__, |
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}; |
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static const unsigned int gpio0_pins[] = { 0 }; |
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static const unsigned int gpio1_pins[] = { 1 }; |
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static const unsigned int gpio2_pins[] = { 2 }; |
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static const unsigned int gpio3_pins[] = { 3 }; |
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static const unsigned int gpio4_pins[] = { 4 }; |
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static const unsigned int gpio5_pins[] = { 5 }; |
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static const unsigned int gpio6_pins[] = { 6 }; |
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static const unsigned int gpio7_pins[] = { 7 }; |
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static const unsigned int gpio8_pins[] = { 8 }; |
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static const unsigned int gpio9_pins[] = { 9 }; |
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static const unsigned int gpio10_pins[] = { 10 }; |
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static const unsigned int gpio11_pins[] = { 11 }; |
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static const unsigned int gpio12_pins[] = { 12 }; |
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static const unsigned int gpio13_pins[] = { 13 }; |
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static const char * const swr_tx_clk_groups[] = { "gpio0" }; |
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static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" }; |
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static const char * const swr_rx_clk_groups[] = { "gpio3" }; |
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static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" }; |
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static const char * const dmic1_clk_groups[] = { "gpio6" }; |
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static const char * const dmic1_data_groups[] = { "gpio7" }; |
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static const char * const dmic2_clk_groups[] = { "gpio8" }; |
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static const char * const dmic2_data_groups[] = { "gpio9" }; |
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static const char * const i2s2_clk_groups[] = { "gpio10" }; |
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static const char * const i2s2_ws_groups[] = { "gpio11" }; |
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static const char * const dmic3_clk_groups[] = { "gpio12" }; |
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static const char * const dmic3_data_groups[] = { "gpio13" }; |
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static const char * const qua_mi2s_sclk_groups[] = { "gpio0" }; |
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static const char * const qua_mi2s_ws_groups[] = { "gpio1" }; |
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static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" }; |
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static const char * const i2s1_clk_groups[] = { "gpio6" }; |
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static const char * const i2s1_ws_groups[] = { "gpio7" }; |
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static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" }; |
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static const char * const wsa_swr_clk_groups[] = { "gpio10" }; |
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static const char * const wsa_swr_data_groups[] = { "gpio11" }; |
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static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" }; |
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static const struct lpi_pingroup sm8250_groups[] = { |
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LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _), |
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LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _), |
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LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _), |
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LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _), |
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LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _), |
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LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _), |
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LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _), |
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LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _), |
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LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _), |
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LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _), |
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LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _), |
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LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _), |
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LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _), |
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LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _), |
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}; |
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static const struct lpi_function sm8250_functions[] = { |
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LPI_FUNCTION(dmic1_clk), |
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LPI_FUNCTION(dmic1_data), |
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LPI_FUNCTION(dmic2_clk), |
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LPI_FUNCTION(dmic2_data), |
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LPI_FUNCTION(dmic3_clk), |
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LPI_FUNCTION(dmic3_data), |
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LPI_FUNCTION(i2s1_clk), |
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LPI_FUNCTION(i2s1_data), |
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LPI_FUNCTION(i2s1_ws), |
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LPI_FUNCTION(i2s2_clk), |
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LPI_FUNCTION(i2s2_data), |
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LPI_FUNCTION(i2s2_ws), |
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LPI_FUNCTION(qua_mi2s_data), |
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LPI_FUNCTION(qua_mi2s_sclk), |
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LPI_FUNCTION(qua_mi2s_ws), |
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LPI_FUNCTION(swr_rx_clk), |
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LPI_FUNCTION(swr_rx_data), |
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LPI_FUNCTION(swr_tx_clk), |
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LPI_FUNCTION(swr_tx_data), |
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LPI_FUNCTION(wsa_swr_clk), |
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LPI_FUNCTION(wsa_swr_data), |
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}; |
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static struct lpi_pinctrl_variant_data sm8250_lpi_data = { |
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.pins = sm8250_lpi_pins, |
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.npins = ARRAY_SIZE(sm8250_lpi_pins), |
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.groups = sm8250_groups, |
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.ngroups = ARRAY_SIZE(sm8250_groups), |
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.functions = sm8250_functions, |
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.nfunctions = ARRAY_SIZE(sm8250_functions), |
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}; |
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static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, |
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unsigned int addr) |
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{ |
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return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); |
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} |
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static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, |
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unsigned int addr, unsigned int val) |
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{ |
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iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); |
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return 0; |
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} |
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static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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return pctrl->data->ngroups; |
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} |
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static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev, |
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unsigned int group) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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return pctrl->data->groups[group].name; |
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} |
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static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev, |
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unsigned int group, |
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const unsigned int **pins, |
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unsigned int *num_pins) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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*pins = pctrl->data->groups[group].pins; |
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*num_pins = pctrl->data->groups[group].npins; |
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return 0; |
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} |
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static const struct pinctrl_ops lpi_gpio_pinctrl_ops = { |
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.get_groups_count = lpi_gpio_get_groups_count, |
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.get_group_name = lpi_gpio_get_group_name, |
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.get_group_pins = lpi_gpio_get_group_pins, |
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group, |
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.dt_free_map = pinctrl_utils_free_map, |
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}; |
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static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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return pctrl->data->nfunctions; |
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} |
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static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev, |
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unsigned int function) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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return pctrl->data->functions[function].name; |
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} |
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static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev, |
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unsigned int function, |
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const char *const **groups, |
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unsigned *const num_qgroups) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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*groups = pctrl->data->functions[function].groups; |
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*num_qgroups = pctrl->data->functions[function].ngroups; |
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return 0; |
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} |
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static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, |
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unsigned int group_num) |
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{ |
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struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); |
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const struct lpi_pingroup *g = &pctrl->data->groups[group_num]; |
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u32 val; |
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int i, pin = g->pin; |
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for (i = 0; i < g->nfuncs; i++) { |
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if (g->funcs[i] == function) |
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break; |
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} |
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if (WARN_ON(i == g->nfuncs)) |
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return -EINVAL; |
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val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG); |
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u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK); |
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lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val); |
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return 0; |
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} |
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static const struct pinmux_ops lpi_gpio_pinmux_ops = { |
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.get_functions_count = lpi_gpio_get_functions_count, |
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.get_function_name = lpi_gpio_get_function_name, |
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.get_function_groups = lpi_gpio_get_function_groups, |
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.set_mux = lpi_gpio_set_mux, |
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}; |
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static int lpi_config_get(struct pinctrl_dev *pctldev, |
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unsigned int pin, unsigned long *config) |
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{ |
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unsigned int param = pinconf_to_config_param(*config); |
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struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev); |
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unsigned int arg = 0; |
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int is_out; |
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int pull; |
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u32 ctl_reg; |
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ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG); |
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is_out = ctl_reg & LPI_GPIO_OE_MASK; |
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pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); |
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switch (param) { |
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case PIN_CONFIG_BIAS_DISABLE: |
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if (pull == LPI_GPIO_BIAS_DISABLE) |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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if (pull == LPI_GPIO_PULL_DOWN) |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_BUS_HOLD: |
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if (pull == LPI_GPIO_KEEPER) |
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arg = 1; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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if (pull == LPI_GPIO_PULL_UP) |
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arg = 1; |
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break; |
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case PIN_CONFIG_INPUT_ENABLE: |
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case PIN_CONFIG_OUTPUT: |
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if (is_out) |
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arg = 1; |
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break; |
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default: |
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return -EINVAL; |
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} |
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*config = pinconf_to_config_packed(param, arg); |
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return 0; |
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} |
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static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, |
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unsigned long *configs, unsigned int nconfs) |
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{ |
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struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev); |
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unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; |
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bool value, output_enabled = false; |
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const struct lpi_pingroup *g; |
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unsigned long sval; |
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int i, slew_offset; |
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u32 val; |
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g = &pctrl->data->groups[group]; |
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for (i = 0; i < nconfs; i++) { |
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param = pinconf_to_config_param(configs[i]); |
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arg = pinconf_to_config_argument(configs[i]); |
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switch (param) { |
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case PIN_CONFIG_BIAS_DISABLE: |
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pullup = LPI_GPIO_BIAS_DISABLE; |
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break; |
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case PIN_CONFIG_BIAS_PULL_DOWN: |
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pullup = LPI_GPIO_PULL_DOWN; |
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break; |
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case PIN_CONFIG_BIAS_BUS_HOLD: |
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pullup = LPI_GPIO_KEEPER; |
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break; |
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case PIN_CONFIG_BIAS_PULL_UP: |
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pullup = LPI_GPIO_PULL_UP; |
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break; |
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case PIN_CONFIG_INPUT_ENABLE: |
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output_enabled = false; |
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break; |
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case PIN_CONFIG_OUTPUT: |
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output_enabled = true; |
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value = arg; |
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break; |
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case PIN_CONFIG_DRIVE_STRENGTH: |
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strength = arg; |
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break; |
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case PIN_CONFIG_SLEW_RATE: |
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if (arg > LPI_SLEW_RATE_MAX) { |
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dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", |
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arg, group); |
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return -EINVAL; |
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} |
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slew_offset = g->slew_offset; |
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if (slew_offset == NO_SLEW) |
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break; |
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mutex_lock(&pctrl->slew_access_lock); |
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sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); |
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sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); |
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sval |= arg << slew_offset; |
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iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); |
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mutex_unlock(&pctrl->slew_access_lock); |
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break; |
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default: |
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return -EINVAL; |
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} |
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} |
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val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG); |
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u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK); |
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u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength), |
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LPI_GPIO_OUT_STRENGTH_MASK); |
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u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK); |
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lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val); |
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if (output_enabled) { |
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val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK); |
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lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val); |
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} |
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return 0; |
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} |
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static const struct pinconf_ops lpi_gpio_pinconf_ops = { |
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.is_generic = true, |
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.pin_config_group_get = lpi_config_get, |
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.pin_config_group_set = lpi_config_set, |
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}; |
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static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) |
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{ |
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struct lpi_pinctrl *state = gpiochip_get_data(chip); |
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unsigned long config; |
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config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); |
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return lpi_config_set(state->ctrl, pin, &config, 1); |
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} |
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static int lpi_gpio_direction_output(struct gpio_chip *chip, |
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unsigned int pin, int val) |
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{ |
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struct lpi_pinctrl *state = gpiochip_get_data(chip); |
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unsigned long config; |
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|
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config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); |
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|
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return lpi_config_set(state->ctrl, pin, &config, 1); |
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} |
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|
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static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin) |
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{ |
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struct lpi_pinctrl *state = gpiochip_get_data(chip); |
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|
|
return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) & |
|
LPI_GPIO_VALUE_IN_MASK; |
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} |
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|
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static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) |
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{ |
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struct lpi_pinctrl *state = gpiochip_get_data(chip); |
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unsigned long config; |
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|
|
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); |
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|
|
lpi_config_set(state->ctrl, pin, &config, 1); |
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} |
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|
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#ifdef CONFIG_DEBUG_FS |
|
#include <linux/seq_file.h> |
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|
|
static unsigned int lpi_regval_to_drive(u32 val) |
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{ |
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return (val + 1) * 2; |
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} |
|
|
|
static void lpi_gpio_dbg_show_one(struct seq_file *s, |
|
struct pinctrl_dev *pctldev, |
|
struct gpio_chip *chip, |
|
unsigned int offset, |
|
unsigned int gpio) |
|
{ |
|
struct lpi_pinctrl *state = gpiochip_get_data(chip); |
|
struct pinctrl_pin_desc pindesc; |
|
unsigned int func; |
|
int is_out; |
|
int drive; |
|
int pull; |
|
u32 ctl_reg; |
|
|
|
static const char * const pulls[] = { |
|
"no pull", |
|
"pull down", |
|
"keeper", |
|
"pull up" |
|
}; |
|
|
|
pctldev = pctldev ? : state->ctrl; |
|
pindesc = pctldev->desc->pins[offset]; |
|
ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG); |
|
is_out = ctl_reg & LPI_GPIO_OE_MASK; |
|
|
|
func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg); |
|
drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg); |
|
pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg); |
|
|
|
seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func); |
|
seq_printf(s, " %dmA", lpi_regval_to_drive(drive)); |
|
seq_printf(s, " %s", pulls[pull]); |
|
} |
|
|
|
static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
|
{ |
|
unsigned int gpio = chip->base; |
|
unsigned int i; |
|
|
|
for (i = 0; i < chip->ngpio; i++, gpio++) { |
|
lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio); |
|
seq_puts(s, "\n"); |
|
} |
|
} |
|
|
|
#else |
|
#define lpi_gpio_dbg_show NULL |
|
#endif |
|
|
|
static const struct gpio_chip lpi_gpio_template = { |
|
.direction_input = lpi_gpio_direction_input, |
|
.direction_output = lpi_gpio_direction_output, |
|
.get = lpi_gpio_get, |
|
.set = lpi_gpio_set, |
|
.request = gpiochip_generic_request, |
|
.free = gpiochip_generic_free, |
|
.dbg_show = lpi_gpio_dbg_show, |
|
}; |
|
|
|
static int lpi_pinctrl_probe(struct platform_device *pdev) |
|
{ |
|
const struct lpi_pinctrl_variant_data *data; |
|
struct device *dev = &pdev->dev; |
|
struct lpi_pinctrl *pctrl; |
|
int ret; |
|
|
|
pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); |
|
if (!pctrl) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, pctrl); |
|
|
|
data = of_device_get_match_data(dev); |
|
if (!data) |
|
return -EINVAL; |
|
|
|
pctrl->data = data; |
|
pctrl->dev = &pdev->dev; |
|
|
|
pctrl->clks[0].id = "core"; |
|
pctrl->clks[1].id = "audio"; |
|
|
|
pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(pctrl->tlmm_base)) |
|
return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), |
|
"TLMM resource not provided\n"); |
|
|
|
pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); |
|
if (IS_ERR(pctrl->slew_base)) |
|
return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), |
|
"Slew resource not provided\n"); |
|
|
|
ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks); |
|
if (ret) |
|
return dev_err_probe(dev, ret, "Can't get clocks\n"); |
|
|
|
ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); |
|
if (ret) |
|
return dev_err_probe(dev, ret, "Can't enable clocks\n"); |
|
|
|
pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops; |
|
pctrl->desc.pmxops = &lpi_gpio_pinmux_ops; |
|
pctrl->desc.confops = &lpi_gpio_pinconf_ops; |
|
pctrl->desc.owner = THIS_MODULE; |
|
pctrl->desc.name = dev_name(dev); |
|
pctrl->desc.pins = data->pins; |
|
pctrl->desc.npins = data->npins; |
|
pctrl->chip = lpi_gpio_template; |
|
pctrl->chip.parent = dev; |
|
pctrl->chip.base = -1; |
|
pctrl->chip.ngpio = data->npins; |
|
pctrl->chip.label = dev_name(dev); |
|
pctrl->chip.of_gpio_n_cells = 2; |
|
pctrl->chip.can_sleep = false; |
|
|
|
mutex_init(&pctrl->slew_access_lock); |
|
|
|
pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl); |
|
if (IS_ERR(pctrl->ctrl)) { |
|
ret = PTR_ERR(pctrl->ctrl); |
|
dev_err(dev, "failed to add pin controller\n"); |
|
goto err_pinctrl; |
|
} |
|
|
|
ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); |
|
if (ret) { |
|
dev_err(pctrl->dev, "can't add gpio chip\n"); |
|
goto err_pinctrl; |
|
} |
|
|
|
return 0; |
|
|
|
err_pinctrl: |
|
mutex_destroy(&pctrl->slew_access_lock); |
|
clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); |
|
|
|
return ret; |
|
} |
|
|
|
static int lpi_pinctrl_remove(struct platform_device *pdev) |
|
{ |
|
struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev); |
|
|
|
mutex_destroy(&pctrl->slew_access_lock); |
|
clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id lpi_pinctrl_of_match[] = { |
|
{ |
|
.compatible = "qcom,sm8250-lpass-lpi-pinctrl", |
|
.data = &sm8250_lpi_data, |
|
}, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); |
|
|
|
static struct platform_driver lpi_pinctrl_driver = { |
|
.driver = { |
|
.name = "qcom-lpass-lpi-pinctrl", |
|
.of_match_table = lpi_pinctrl_of_match, |
|
}, |
|
.probe = lpi_pinctrl_probe, |
|
.remove = lpi_pinctrl_remove, |
|
}; |
|
|
|
module_platform_driver(lpi_pinctrl_driver); |
|
MODULE_DESCRIPTION("QTI LPI GPIO pin control driver"); |
|
MODULE_LICENSE("GPL");
|
|
|