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301 lines
7.5 KiB
301 lines
7.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Intel Keem Bay USB PHY driver |
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* Copyright (C) 2020 Intel Corporation |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/bits.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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/* USS (USB Subsystem) clock control registers */ |
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#define USS_CPR_CLK_EN 0x00 |
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#define USS_CPR_CLK_SET 0x04 |
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#define USS_CPR_CLK_CLR 0x08 |
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#define USS_CPR_RST_EN 0x10 |
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#define USS_CPR_RST_SET 0x14 |
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#define USS_CPR_RST_CLR 0x18 |
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/* USS clock/reset bit fields */ |
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#define USS_CPR_PHY_TST BIT(6) |
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#define USS_CPR_LOW_JIT BIT(5) |
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#define USS_CPR_CORE BIT(4) |
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#define USS_CPR_SUSPEND BIT(3) |
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#define USS_CPR_ALT_REF BIT(2) |
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#define USS_CPR_REF BIT(1) |
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#define USS_CPR_SYS BIT(0) |
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#define USS_CPR_MASK GENMASK(6, 0) |
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/* USS APB slave registers */ |
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#define USS_USB_CTRL_CFG0 0x10 |
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#define VCC_RESET_N_MASK BIT(31) |
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#define USS_USB_PHY_CFG0 0x30 |
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#define POR_MASK BIT(15) |
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#define PHY_RESET_MASK BIT(14) |
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#define PHY_REF_USE_PAD_MASK BIT(5) |
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#define USS_USB_PHY_CFG6 0x64 |
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#define PHY0_SRAM_EXT_LD_DONE_MASK BIT(23) |
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#define USS_USB_PARALLEL_IF_CTRL 0xa0 |
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#define USB_PHY_CR_PARA_SEL_MASK BIT(2) |
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#define USS_USB_TSET_SIGNALS_AND_GLOB 0xac |
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#define USB_PHY_CR_PARA_CLK_EN_MASK BIT(7) |
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#define USS_USB_STATUS_REG 0xb8 |
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#define PHY0_SRAM_INIT_DONE_MASK BIT(3) |
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#define USS_USB_TIEOFFS_CONSTANTS_REG1 0xc0 |
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#define IDDQ_ENABLE_MASK BIT(10) |
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struct keembay_usb_phy { |
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struct device *dev; |
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struct regmap *regmap_cpr; |
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struct regmap *regmap_slv; |
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}; |
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static const struct regmap_config keembay_regmap_config = { |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = USS_USB_TIEOFFS_CONSTANTS_REG1, |
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}; |
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static int keembay_usb_clocks_on(struct keembay_usb_phy *priv) |
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{ |
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int ret; |
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ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_CLK_SET, |
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USS_CPR_MASK, USS_CPR_MASK); |
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if (ret) { |
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dev_err(priv->dev, "error clock set: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_update_bits(priv->regmap_cpr, USS_CPR_RST_SET, |
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USS_CPR_MASK, USS_CPR_MASK); |
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if (ret) { |
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dev_err(priv->dev, "error reset set: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_update_bits(priv->regmap_slv, |
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USS_USB_TIEOFFS_CONSTANTS_REG1, |
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IDDQ_ENABLE_MASK, |
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FIELD_PREP(IDDQ_ENABLE_MASK, 0)); |
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if (ret) { |
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dev_err(priv->dev, "error iddq disable: %d\n", ret); |
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return ret; |
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} |
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/* Wait 30us to ensure all analog blocks are powered up. */ |
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usleep_range(30, 60); |
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ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, |
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PHY_REF_USE_PAD_MASK, |
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FIELD_PREP(PHY_REF_USE_PAD_MASK, 1)); |
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if (ret) |
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dev_err(priv->dev, "error ref clock select: %d\n", ret); |
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return ret; |
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} |
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static int keembay_usb_core_off(struct keembay_usb_phy *priv) |
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{ |
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int ret; |
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ret = regmap_update_bits(priv->regmap_slv, USS_USB_CTRL_CFG0, |
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VCC_RESET_N_MASK, |
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FIELD_PREP(VCC_RESET_N_MASK, 0)); |
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if (ret) |
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dev_err(priv->dev, "error core reset: %d\n", ret); |
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return ret; |
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} |
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static int keembay_usb_core_on(struct keembay_usb_phy *priv) |
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{ |
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int ret; |
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ret = regmap_update_bits(priv->regmap_slv, USS_USB_CTRL_CFG0, |
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VCC_RESET_N_MASK, |
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FIELD_PREP(VCC_RESET_N_MASK, 1)); |
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if (ret) |
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dev_err(priv->dev, "error core on: %d\n", ret); |
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return ret; |
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} |
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static int keembay_usb_phys_on(struct keembay_usb_phy *priv) |
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{ |
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int ret; |
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ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG0, |
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POR_MASK | PHY_RESET_MASK, |
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FIELD_PREP(POR_MASK | PHY_RESET_MASK, 0)); |
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if (ret) |
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dev_err(priv->dev, "error phys on: %d\n", ret); |
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return ret; |
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} |
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static int keembay_usb_phy_init(struct phy *phy) |
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{ |
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struct keembay_usb_phy *priv = phy_get_drvdata(phy); |
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u32 val; |
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int ret; |
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ret = keembay_usb_core_off(priv); |
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if (ret) |
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return ret; |
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/* |
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* According to Keem Bay datasheet, wait minimum 20us after clock |
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* enable before bringing PHYs out of reset. |
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*/ |
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usleep_range(20, 40); |
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ret = keembay_usb_phys_on(priv); |
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if (ret) |
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return ret; |
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ret = regmap_update_bits(priv->regmap_slv, |
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USS_USB_TSET_SIGNALS_AND_GLOB, |
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USB_PHY_CR_PARA_CLK_EN_MASK, |
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FIELD_PREP(USB_PHY_CR_PARA_CLK_EN_MASK, 0)); |
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if (ret) { |
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dev_err(priv->dev, "error cr clock disable: %d\n", ret); |
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return ret; |
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} |
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/* |
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* According to Keem Bay datasheet, wait 2us after disabling the |
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* clock into the USB 3.x parallel interface. |
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*/ |
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udelay(2); |
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ret = regmap_update_bits(priv->regmap_slv, |
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USS_USB_PARALLEL_IF_CTRL, |
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USB_PHY_CR_PARA_SEL_MASK, |
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FIELD_PREP(USB_PHY_CR_PARA_SEL_MASK, 1)); |
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if (ret) { |
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dev_err(priv->dev, "error cr select: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_update_bits(priv->regmap_slv, |
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USS_USB_TSET_SIGNALS_AND_GLOB, |
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USB_PHY_CR_PARA_CLK_EN_MASK, |
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FIELD_PREP(USB_PHY_CR_PARA_CLK_EN_MASK, 1)); |
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if (ret) { |
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dev_err(priv->dev, "error cr clock enable: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_read_poll_timeout(priv->regmap_slv, USS_USB_STATUS_REG, |
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val, val & PHY0_SRAM_INIT_DONE_MASK, |
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USEC_PER_MSEC, 10 * USEC_PER_MSEC); |
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if (ret) { |
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dev_err(priv->dev, "SRAM init not done: %d\n", ret); |
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return ret; |
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} |
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ret = regmap_update_bits(priv->regmap_slv, USS_USB_PHY_CFG6, |
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PHY0_SRAM_EXT_LD_DONE_MASK, |
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FIELD_PREP(PHY0_SRAM_EXT_LD_DONE_MASK, 1)); |
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if (ret) { |
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dev_err(priv->dev, "error SRAM init done set: %d\n", ret); |
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return ret; |
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} |
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/* |
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* According to Keem Bay datasheet, wait 20us after setting the |
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* SRAM load done bit, before releasing the controller reset. |
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*/ |
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usleep_range(20, 40); |
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return keembay_usb_core_on(priv); |
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} |
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static const struct phy_ops ops = { |
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.init = keembay_usb_phy_init, |
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.owner = THIS_MODULE, |
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}; |
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static int keembay_usb_phy_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct keembay_usb_phy *priv; |
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struct phy *generic_phy; |
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struct phy_provider *phy_provider; |
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void __iomem *base; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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base = devm_platform_ioremap_resource_byname(pdev, "cpr-apb-base"); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->regmap_cpr = devm_regmap_init_mmio(dev, base, |
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&keembay_regmap_config); |
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if (IS_ERR(priv->regmap_cpr)) |
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return PTR_ERR(priv->regmap_cpr); |
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base = devm_platform_ioremap_resource_byname(pdev, "slv-apb-base"); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->regmap_slv = devm_regmap_init_mmio(dev, base, |
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&keembay_regmap_config); |
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if (IS_ERR(priv->regmap_slv)) |
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return PTR_ERR(priv->regmap_slv); |
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generic_phy = devm_phy_create(dev, dev->of_node, &ops); |
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if (IS_ERR(generic_phy)) |
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return dev_err_probe(dev, PTR_ERR(generic_phy), |
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"failed to create PHY\n"); |
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phy_set_drvdata(generic_phy, priv); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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if (IS_ERR(phy_provider)) |
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return dev_err_probe(dev, PTR_ERR(phy_provider), |
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"failed to register phy provider\n"); |
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/* Setup USB subsystem clocks */ |
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ret = keembay_usb_clocks_on(priv); |
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if (ret) |
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return ret; |
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/* and turn on the DWC3 core, prior to DWC3 driver init. */ |
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return keembay_usb_core_on(priv); |
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} |
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static const struct of_device_id keembay_usb_phy_dt_ids[] = { |
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{ .compatible = "intel,keembay-usb-phy" }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, keembay_usb_phy_dt_ids); |
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static struct platform_driver keembay_usb_phy_driver = { |
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.probe = keembay_usb_phy_probe, |
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.driver = { |
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.name = "keembay-usb-phy", |
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.of_match_table = keembay_usb_phy_dt_ids, |
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}, |
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}; |
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module_platform_driver(keembay_usb_phy_driver); |
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MODULE_AUTHOR("Wan Ahmad Zainie <[email protected]>"); |
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MODULE_DESCRIPTION("Intel Keem Bay USB PHY driver"); |
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MODULE_LICENSE("GPL v2");
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