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323 lines
9.9 KiB
323 lines
9.9 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Salvo PHY is a 28nm PHY, it is a legacy PHY, and only |
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* for USB3 and USB2. |
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* |
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* Copyright (c) 2019-2020 NXP |
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*/ |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/phy/phy.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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/* PHY register definition */ |
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#define PHY_PMA_CMN_CTRL1 0xC800 |
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#define TB_ADDR_CMN_DIAG_HSCLK_SEL 0x01e0 |
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#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR 0x0084 |
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#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR 0x0085 |
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#define TB_ADDR_CMN_PLL0_INTDIV 0x0094 |
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#define TB_ADDR_CMN_PLL0_FRACDIV 0x0095 |
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#define TB_ADDR_CMN_PLL0_HIGH_THR 0x0096 |
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#define TB_ADDR_CMN_PLL0_SS_CTRL1 0x0098 |
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#define TB_ADDR_CMN_PLL0_SS_CTRL2 0x0099 |
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#define TB_ADDR_CMN_PLL0_DSM_DIAG 0x0097 |
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#define TB_ADDR_CMN_DIAG_PLL0_OVRD 0x01c2 |
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#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD 0x01c0 |
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#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD 0x01c1 |
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#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE 0x01C5 |
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#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE 0x01C6 |
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#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG 0x01C7 |
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#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE 0x01c4 |
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#define TB_ADDR_CMN_PSM_CLK_CTRL 0x0061 |
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#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR 0x40ea |
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#define TB_ADDR_XCVR_PSM_RCTRL 0x4001 |
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#define TB_ADDR_TX_PSC_A0 0x4100 |
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#define TB_ADDR_TX_PSC_A1 0x4101 |
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#define TB_ADDR_TX_PSC_A2 0x4102 |
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#define TB_ADDR_TX_PSC_A3 0x4103 |
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#define TB_ADDR_TX_DIAG_ECTRL_OVRD 0x41f5 |
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#define TB_ADDR_TX_PSC_CAL 0x4106 |
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#define TB_ADDR_TX_PSC_RDY 0x4107 |
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#define TB_ADDR_RX_PSC_A0 0x8000 |
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#define TB_ADDR_RX_PSC_A1 0x8001 |
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#define TB_ADDR_RX_PSC_A2 0x8002 |
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#define TB_ADDR_RX_PSC_A3 0x8003 |
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#define TB_ADDR_RX_PSC_CAL 0x8006 |
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#define TB_ADDR_RX_PSC_RDY 0x8007 |
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#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 0x4058 |
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#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY 0x41e7 |
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#define TB_ADDR_RX_SLC_CU_ITER_TMR 0x80e3 |
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#define TB_ADDR_RX_SIGDET_HL_FILT_TMR 0x8090 |
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#define TB_ADDR_RX_SAMP_DAC_CTRL 0x8058 |
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#define TB_ADDR_RX_DIAG_SIGDET_TUNE 0x81dc |
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#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 0x81df |
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#define TB_ADDR_RX_DIAG_BS_TM 0x81f5 |
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#define TB_ADDR_RX_DIAG_DFE_CTRL1 0x81d3 |
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#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 0x81c7 |
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#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 0x81c2 |
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#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 0x81c1 |
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#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 0x81c9 |
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#define TB_ADDR_RX_DIAG_RXFE_TM3 0x81f8 |
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#define TB_ADDR_RX_DIAG_RXFE_TM4 0x81f9 |
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#define TB_ADDR_RX_DIAG_LFPSDET_TUNE 0x81dd |
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#define TB_ADDR_RX_DIAG_DFE_CTRL3 0x81d5 |
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#define TB_ADDR_RX_DIAG_SC2C_DELAY 0x81e1 |
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#define TB_ADDR_RX_REE_VGA_GAIN_NODFE 0x81bf |
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#define TB_ADDR_XCVR_PSM_CAL_TMR 0x4002 |
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#define TB_ADDR_XCVR_PSM_A0BYP_TMR 0x4004 |
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#define TB_ADDR_XCVR_PSM_A0IN_TMR 0x4003 |
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#define TB_ADDR_XCVR_PSM_A1IN_TMR 0x4005 |
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#define TB_ADDR_XCVR_PSM_A2IN_TMR 0x4006 |
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#define TB_ADDR_XCVR_PSM_A3IN_TMR 0x4007 |
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#define TB_ADDR_XCVR_PSM_A4IN_TMR 0x4008 |
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#define TB_ADDR_XCVR_PSM_A5IN_TMR 0x4009 |
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#define TB_ADDR_XCVR_PSM_A0OUT_TMR 0x400a |
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#define TB_ADDR_XCVR_PSM_A1OUT_TMR 0x400b |
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#define TB_ADDR_XCVR_PSM_A2OUT_TMR 0x400c |
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#define TB_ADDR_XCVR_PSM_A3OUT_TMR 0x400d |
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#define TB_ADDR_XCVR_PSM_A4OUT_TMR 0x400e |
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#define TB_ADDR_XCVR_PSM_A5OUT_TMR 0x400f |
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#define TB_ADDR_TX_RCVDET_EN_TMR 0x4122 |
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#define TB_ADDR_TX_RCVDET_ST_TMR 0x4123 |
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#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2 |
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#define TB_ADDR_TX_RCVDETSC_CTRL 0x4124 |
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/* TB_ADDR_TX_RCVDETSC_CTRL */ |
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#define RXDET_IN_P3_32KHZ BIT(0) |
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struct cdns_reg_pairs { |
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u16 val; |
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u32 off; |
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}; |
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struct cdns_salvo_data { |
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u8 reg_offset_shift; |
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const struct cdns_reg_pairs *init_sequence_val; |
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u8 init_sequence_length; |
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}; |
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struct cdns_salvo_phy { |
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struct phy *phy; |
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struct clk *clk; |
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void __iomem *base; |
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struct cdns_salvo_data *data; |
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}; |
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static const struct of_device_id cdns_salvo_phy_of_match[]; |
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static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg) |
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{ |
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return (u16)readl(salvo_phy->base + |
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reg * (1 << salvo_phy->data->reg_offset_shift)); |
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} |
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static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, |
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u32 reg, u16 val) |
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{ |
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writel(val, salvo_phy->base + |
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reg * (1 << salvo_phy->data->reg_offset_shift)); |
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} |
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/* |
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* Below bringup sequence pair are from Cadence PHY's User Guide |
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* and NXP platform tuning results. |
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*/ |
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static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = { |
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{0x0830, PHY_PMA_CMN_CTRL1}, |
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{0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL}, |
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{0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR}, |
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{0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR}, |
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{0x00d0, TB_ADDR_CMN_PLL0_INTDIV}, |
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{0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV}, |
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{0x0034, TB_ADDR_CMN_PLL0_HIGH_THR}, |
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{0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1}, |
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{0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2}, |
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{0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG}, |
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{0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD}, |
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{0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD}, |
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{0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD}, |
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{0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE}, |
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{0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE}, |
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{0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG}, |
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{0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE}, |
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{0x000a, TB_ADDR_CMN_PSM_CLK_CTRL}, |
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{0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR}, |
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{0xbefc, TB_ADDR_XCVR_PSM_RCTRL}, |
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{0x7799, TB_ADDR_TX_PSC_A0}, |
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{0x7798, TB_ADDR_TX_PSC_A1}, |
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{0x509b, TB_ADDR_TX_PSC_A2}, |
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{0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD}, |
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{0x509b, TB_ADDR_TX_PSC_A3}, |
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{0x2090, TB_ADDR_TX_PSC_CAL}, |
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{0x2090, TB_ADDR_TX_PSC_RDY}, |
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{0xA6FD, TB_ADDR_RX_PSC_A0}, |
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{0xA6FD, TB_ADDR_RX_PSC_A1}, |
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{0xA410, TB_ADDR_RX_PSC_A2}, |
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{0x2410, TB_ADDR_RX_PSC_A3}, |
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{0x23FF, TB_ADDR_RX_PSC_CAL}, |
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{0x2010, TB_ADDR_RX_PSC_RDY}, |
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{0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000}, |
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{0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY}, |
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{0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR}, |
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{0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR}, |
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{0x0000, TB_ADDR_RX_SAMP_DAC_CTRL}, |
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{0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE}, |
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{0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2}, |
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{0x0480, TB_ADDR_RX_DIAG_BS_TM}, |
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{0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1}, |
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{0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4}, |
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{0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0}, |
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{0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0}, |
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{0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6}, |
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{0x8000, TB_ADDR_RX_DIAG_RXFE_TM3}, |
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{0x0003, TB_ADDR_RX_DIAG_RXFE_TM4}, |
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{0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE}, |
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{0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3}, |
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{0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY}, |
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{0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE}, |
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{0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR}, |
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{0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR}, |
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{0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR}, |
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{0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR}, |
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{0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR}, |
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{0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR}, |
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{0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR}, |
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{0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR}, |
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/* Change rx detect parameter */ |
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{0x0960, TB_ADDR_TX_RCVDET_EN_TMR}, |
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{0x01e0, TB_ADDR_TX_RCVDET_ST_TMR}, |
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{0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR}, |
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}; |
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static int cdns_salvo_phy_init(struct phy *phy) |
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{ |
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struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy); |
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struct cdns_salvo_data *data = salvo_phy->data; |
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int ret, i; |
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u16 value; |
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ret = clk_prepare_enable(salvo_phy->clk); |
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if (ret) |
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return ret; |
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for (i = 0; i < data->init_sequence_length; i++) { |
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const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i; |
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cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val); |
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} |
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/* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */ |
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value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL); |
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value |= RXDET_IN_P3_32KHZ; |
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cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL, |
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RXDET_IN_P3_32KHZ); |
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udelay(10); |
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clk_disable_unprepare(salvo_phy->clk); |
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return ret; |
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} |
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static int cdns_salvo_phy_power_on(struct phy *phy) |
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{ |
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struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy); |
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return clk_prepare_enable(salvo_phy->clk); |
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} |
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static int cdns_salvo_phy_power_off(struct phy *phy) |
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{ |
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struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy); |
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clk_disable_unprepare(salvo_phy->clk); |
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return 0; |
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} |
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static const struct phy_ops cdns_salvo_phy_ops = { |
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.init = cdns_salvo_phy_init, |
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.power_on = cdns_salvo_phy_power_on, |
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.power_off = cdns_salvo_phy_power_off, |
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.owner = THIS_MODULE, |
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}; |
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static int cdns_salvo_phy_probe(struct platform_device *pdev) |
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{ |
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struct phy_provider *phy_provider; |
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struct device *dev = &pdev->dev; |
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struct cdns_salvo_phy *salvo_phy; |
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const struct of_device_id *match; |
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struct cdns_salvo_data *data; |
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match = of_match_device(cdns_salvo_phy_of_match, dev); |
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if (!match) |
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return -EINVAL; |
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data = (struct cdns_salvo_data *)match->data; |
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salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL); |
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if (!salvo_phy) |
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return -ENOMEM; |
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salvo_phy->data = data; |
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salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk"); |
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if (IS_ERR(salvo_phy->clk)) |
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return PTR_ERR(salvo_phy->clk); |
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salvo_phy->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(salvo_phy->base)) |
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return PTR_ERR(salvo_phy->base); |
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salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops); |
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if (IS_ERR(salvo_phy->phy)) |
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return PTR_ERR(salvo_phy->phy); |
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phy_set_drvdata(salvo_phy->phy, salvo_phy); |
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(phy_provider); |
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} |
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static const struct cdns_salvo_data cdns_nxp_salvo_data = { |
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2, |
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cdns_nxp_sequence_pair, |
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ARRAY_SIZE(cdns_nxp_sequence_pair), |
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}; |
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static const struct of_device_id cdns_salvo_phy_of_match[] = { |
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{ |
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.compatible = "nxp,salvo-phy", |
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.data = &cdns_nxp_salvo_data, |
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}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match); |
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static struct platform_driver cdns_salvo_phy_driver = { |
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.probe = cdns_salvo_phy_probe, |
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.driver = { |
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.name = "cdns-salvo-phy", |
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.of_match_table = cdns_salvo_phy_of_match, |
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} |
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}; |
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module_platform_driver(cdns_salvo_phy_driver); |
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MODULE_AUTHOR("Peter Chen <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("Cadence SALVO PHY Driver");
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