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327 lines
9.0 KiB
327 lines
9.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Driver for handling the PCIe controller errors on |
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* HiSilicon HIP SoCs. |
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* |
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* Copyright (c) 2020 HiSilicon Limited. |
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*/ |
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#include <linux/acpi.h> |
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#include <acpi/ghes.h> |
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#include <linux/bitops.h> |
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#include <linux/delay.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/kfifo.h> |
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#include <linux/spinlock.h> |
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/* HISI PCIe controller error definitions */ |
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#define HISI_PCIE_ERR_MISC_REGS 33 |
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#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0) |
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#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1) |
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#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2) |
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#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3) |
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#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4) |
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#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5) |
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#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6) |
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#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7) |
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#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8) |
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#define HISI_PCIE_LOCAL_VALID_ERR_MISC 9 |
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static guid_t hisi_pcie_sec_guid = |
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GUID_INIT(0xB2889FC9, 0xE7D7, 0x4F9D, |
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0xA8, 0x67, 0xAF, 0x42, 0xE9, 0x8B, 0xE7, 0x72); |
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/* |
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* Firmware reports the socket port ID where the error occurred. These |
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* macros convert that to the core ID and core port ID required by the |
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* ACPI reset method. |
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*/ |
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#define HISI_PCIE_PORT_ID(core, v) (((v) >> 1) + ((core) << 3)) |
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#define HISI_PCIE_CORE_ID(v) ((v) >> 3) |
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#define HISI_PCIE_CORE_PORT_ID(v) (((v) & 7) << 1) |
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struct hisi_pcie_error_data { |
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u64 val_bits; |
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u8 version; |
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u8 soc_id; |
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u8 socket_id; |
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u8 nimbus_id; |
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u8 sub_module_id; |
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u8 core_id; |
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u8 port_id; |
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u8 err_severity; |
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u16 err_type; |
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u8 reserv[2]; |
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u32 err_misc[HISI_PCIE_ERR_MISC_REGS]; |
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}; |
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struct hisi_pcie_error_private { |
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struct notifier_block nb; |
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struct device *dev; |
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}; |
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enum hisi_pcie_submodule_id { |
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HISI_PCIE_SUB_MODULE_ID_AP, |
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HISI_PCIE_SUB_MODULE_ID_TL, |
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HISI_PCIE_SUB_MODULE_ID_MAC, |
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HISI_PCIE_SUB_MODULE_ID_DL, |
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HISI_PCIE_SUB_MODULE_ID_SDI, |
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}; |
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static const char * const hisi_pcie_sub_module[] = { |
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[HISI_PCIE_SUB_MODULE_ID_AP] = "AP Layer", |
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[HISI_PCIE_SUB_MODULE_ID_TL] = "TL Layer", |
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[HISI_PCIE_SUB_MODULE_ID_MAC] = "MAC Layer", |
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[HISI_PCIE_SUB_MODULE_ID_DL] = "DL Layer", |
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[HISI_PCIE_SUB_MODULE_ID_SDI] = "SDI Layer", |
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}; |
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enum hisi_pcie_err_severity { |
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HISI_PCIE_ERR_SEV_RECOVERABLE, |
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HISI_PCIE_ERR_SEV_FATAL, |
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HISI_PCIE_ERR_SEV_CORRECTED, |
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HISI_PCIE_ERR_SEV_NONE, |
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}; |
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static const char * const hisi_pcie_error_sev[] = { |
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[HISI_PCIE_ERR_SEV_RECOVERABLE] = "recoverable", |
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[HISI_PCIE_ERR_SEV_FATAL] = "fatal", |
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[HISI_PCIE_ERR_SEV_CORRECTED] = "corrected", |
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[HISI_PCIE_ERR_SEV_NONE] = "none", |
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}; |
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static const char *hisi_pcie_get_string(const char * const *array, |
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size_t n, u32 id) |
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{ |
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u32 index; |
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for (index = 0; index < n; index++) { |
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if (index == id && array[index]) |
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return array[index]; |
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} |
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return "unknown"; |
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} |
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static int hisi_pcie_port_reset(struct platform_device *pdev, |
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u32 chip_id, u32 port_id) |
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{ |
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struct device *dev = &pdev->dev; |
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acpi_handle handle = ACPI_HANDLE(dev); |
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union acpi_object arg[3]; |
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struct acpi_object_list arg_list; |
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acpi_status s; |
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unsigned long long data = 0; |
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arg[0].type = ACPI_TYPE_INTEGER; |
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arg[0].integer.value = chip_id; |
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arg[1].type = ACPI_TYPE_INTEGER; |
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arg[1].integer.value = HISI_PCIE_CORE_ID(port_id); |
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arg[2].type = ACPI_TYPE_INTEGER; |
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arg[2].integer.value = HISI_PCIE_CORE_PORT_ID(port_id); |
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arg_list.count = 3; |
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arg_list.pointer = arg; |
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s = acpi_evaluate_integer(handle, "RST", &arg_list, &data); |
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if (ACPI_FAILURE(s)) { |
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dev_err(dev, "No RST method\n"); |
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return -EIO; |
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} |
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if (data) { |
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dev_err(dev, "Failed to Reset\n"); |
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return -EIO; |
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} |
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return 0; |
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} |
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static int hisi_pcie_port_do_recovery(struct platform_device *dev, |
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u32 chip_id, u32 port_id) |
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{ |
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acpi_status s; |
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struct device *device = &dev->dev; |
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acpi_handle root_handle = ACPI_HANDLE(device); |
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struct acpi_pci_root *pci_root; |
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struct pci_bus *root_bus; |
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struct pci_dev *pdev; |
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u32 domain, busnr, devfn; |
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s = acpi_get_parent(root_handle, &root_handle); |
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if (ACPI_FAILURE(s)) |
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return -ENODEV; |
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pci_root = acpi_pci_find_root(root_handle); |
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if (!pci_root) |
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return -ENODEV; |
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root_bus = pci_root->bus; |
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domain = pci_root->segment; |
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busnr = root_bus->number; |
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devfn = PCI_DEVFN(port_id, 0); |
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pdev = pci_get_domain_bus_and_slot(domain, busnr, devfn); |
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if (!pdev) { |
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dev_info(device, "Fail to get root port %04x:%02x:%02x.%d device\n", |
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domain, busnr, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
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return -ENODEV; |
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} |
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pci_stop_and_remove_bus_device_locked(pdev); |
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pci_dev_put(pdev); |
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if (hisi_pcie_port_reset(dev, chip_id, port_id)) |
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return -EIO; |
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/* |
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* The initialization time of subordinate devices after |
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* hot reset is no more than 1s, which is required by |
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* the PCI spec v5.0 sec 6.6.1. The time will shorten |
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* if Readiness Notifications mechanisms are used. But |
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* wait 1s here to adapt any conditions. |
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*/ |
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ssleep(1UL); |
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/* add root port and downstream devices */ |
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pci_lock_rescan_remove(); |
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pci_rescan_bus(root_bus); |
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pci_unlock_rescan_remove(); |
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return 0; |
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} |
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static void hisi_pcie_handle_error(struct platform_device *pdev, |
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const struct hisi_pcie_error_data *edata) |
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{ |
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struct device *dev = &pdev->dev; |
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int idx, rc; |
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const unsigned long valid_bits[] = {BITMAP_FROM_U64(edata->val_bits)}; |
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if (edata->val_bits == 0) { |
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dev_warn(dev, "%s: no valid error information\n", __func__); |
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return; |
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} |
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dev_info(dev, "\nHISI : HIP : PCIe controller error\n"); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOC_ID) |
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dev_info(dev, "Table version = %d\n", edata->version); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SOCKET_ID) |
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dev_info(dev, "Socket ID = %d\n", edata->socket_id); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_NIMBUS_ID) |
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dev_info(dev, "Nimbus ID = %d\n", edata->nimbus_id); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID) |
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dev_info(dev, "Sub Module = %s\n", |
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hisi_pcie_get_string(hisi_pcie_sub_module, |
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ARRAY_SIZE(hisi_pcie_sub_module), |
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edata->sub_module_id)); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_CORE_ID) |
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dev_info(dev, "Core ID = core%d\n", edata->core_id); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_PORT_ID) |
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dev_info(dev, "Port ID = port%d\n", edata->port_id); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_SEVERITY) |
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dev_info(dev, "Error severity = %s\n", |
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hisi_pcie_get_string(hisi_pcie_error_sev, |
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ARRAY_SIZE(hisi_pcie_error_sev), |
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edata->err_severity)); |
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if (edata->val_bits & HISI_PCIE_LOCAL_VALID_ERR_TYPE) |
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dev_info(dev, "Error type = 0x%x\n", edata->err_type); |
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dev_info(dev, "Reg Dump:\n"); |
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idx = HISI_PCIE_LOCAL_VALID_ERR_MISC; |
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for_each_set_bit_from(idx, valid_bits, |
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HISI_PCIE_LOCAL_VALID_ERR_MISC + HISI_PCIE_ERR_MISC_REGS) |
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dev_info(dev, "ERR_MISC_%d = 0x%x\n", idx - HISI_PCIE_LOCAL_VALID_ERR_MISC, |
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edata->err_misc[idx - HISI_PCIE_LOCAL_VALID_ERR_MISC]); |
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if (edata->err_severity != HISI_PCIE_ERR_SEV_RECOVERABLE) |
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return; |
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/* Recovery for the PCIe controller errors, try reset |
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* PCI port for the error recovery |
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*/ |
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rc = hisi_pcie_port_do_recovery(pdev, edata->socket_id, |
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HISI_PCIE_PORT_ID(edata->core_id, edata->port_id)); |
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if (rc) |
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dev_info(dev, "fail to do hisi pcie port reset\n"); |
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} |
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static int hisi_pcie_notify_error(struct notifier_block *nb, |
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unsigned long event, void *data) |
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{ |
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struct acpi_hest_generic_data *gdata = data; |
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const struct hisi_pcie_error_data *error_data = acpi_hest_get_payload(gdata); |
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struct hisi_pcie_error_private *priv; |
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struct device *dev; |
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struct platform_device *pdev; |
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guid_t err_sec_guid; |
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u8 socket; |
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import_guid(&err_sec_guid, gdata->section_type); |
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if (!guid_equal(&err_sec_guid, &hisi_pcie_sec_guid)) |
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return NOTIFY_DONE; |
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priv = container_of(nb, struct hisi_pcie_error_private, nb); |
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dev = priv->dev; |
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if (device_property_read_u8(dev, "socket", &socket)) |
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return NOTIFY_DONE; |
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if (error_data->socket_id != socket) |
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return NOTIFY_DONE; |
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pdev = container_of(dev, struct platform_device, dev); |
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hisi_pcie_handle_error(pdev, error_data); |
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return NOTIFY_OK; |
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} |
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static int hisi_pcie_error_handler_probe(struct platform_device *pdev) |
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{ |
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struct hisi_pcie_error_private *priv; |
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int ret; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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priv->nb.notifier_call = hisi_pcie_notify_error; |
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priv->dev = &pdev->dev; |
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ret = ghes_register_vendor_record_notifier(&priv->nb); |
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if (ret) { |
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dev_err(&pdev->dev, |
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"Failed to register hisi pcie controller error handler with apei\n"); |
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return ret; |
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} |
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platform_set_drvdata(pdev, priv); |
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return 0; |
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} |
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static int hisi_pcie_error_handler_remove(struct platform_device *pdev) |
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{ |
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struct hisi_pcie_error_private *priv = platform_get_drvdata(pdev); |
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ghes_unregister_vendor_record_notifier(&priv->nb); |
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return 0; |
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} |
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static const struct acpi_device_id hisi_pcie_acpi_match[] = { |
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{ "HISI0361", 0 }, |
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{ } |
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}; |
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static struct platform_driver hisi_pcie_error_handler_driver = { |
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.driver = { |
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.name = "hisi-pcie-error-handler", |
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.acpi_match_table = hisi_pcie_acpi_match, |
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}, |
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.probe = hisi_pcie_error_handler_probe, |
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.remove = hisi_pcie_error_handler_remove, |
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}; |
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module_platform_driver(hisi_pcie_error_handler_driver); |
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MODULE_DESCRIPTION("HiSilicon HIP PCIe controller error handling driver"); |
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MODULE_LICENSE("GPL v2");
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