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671 lines
18 KiB
671 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Support for Intel IXP4xx PCI host controller |
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* |
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* Copyright (C) 2017 Linus Walleij <[email protected]> |
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* |
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* Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver |
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* Copyright (C) 2002 Intel Corporation |
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* Copyright (C) 2003 Greg Ungerer <[email protected]> |
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* Copyright (C) 2003-2004 MontaVista Software, Inc. |
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* Copyright (C) 2005 Deepak Saxena <[email protected]> |
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* Copyright (C) 2005 Alessandro Zummo <[email protected]> |
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* |
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* TODO: |
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* - Test IO-space access |
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* - DMA support |
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*/ |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/of_pci.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/bits.h> |
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/* Register offsets */ |
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#define IXP4XX_PCI_NP_AD 0x00 |
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#define IXP4XX_PCI_NP_CBE 0x04 |
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#define IXP4XX_PCI_NP_WDATA 0x08 |
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#define IXP4XX_PCI_NP_RDATA 0x0c |
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#define IXP4XX_PCI_CRP_AD_CBE 0x10 |
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#define IXP4XX_PCI_CRP_WDATA 0x14 |
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#define IXP4XX_PCI_CRP_RDATA 0x18 |
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#define IXP4XX_PCI_CSR 0x1c |
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#define IXP4XX_PCI_ISR 0x20 |
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#define IXP4XX_PCI_INTEN 0x24 |
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#define IXP4XX_PCI_DMACTRL 0x28 |
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#define IXP4XX_PCI_AHBMEMBASE 0x2c |
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#define IXP4XX_PCI_AHBIOBASE 0x30 |
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#define IXP4XX_PCI_PCIMEMBASE 0x34 |
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#define IXP4XX_PCI_AHBDOORBELL 0x38 |
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#define IXP4XX_PCI_PCIDOORBELL 0x3c |
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#define IXP4XX_PCI_ATPDMA0_AHBADDR 0x40 |
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#define IXP4XX_PCI_ATPDMA0_PCIADDR 0x44 |
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#define IXP4XX_PCI_ATPDMA0_LENADDR 0x48 |
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#define IXP4XX_PCI_ATPDMA1_AHBADDR 0x4c |
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#define IXP4XX_PCI_ATPDMA1_PCIADDR 0x50 |
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#define IXP4XX_PCI_ATPDMA1_LENADDR 0x54 |
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/* CSR bit definitions */ |
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#define IXP4XX_PCI_CSR_HOST BIT(0) |
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#define IXP4XX_PCI_CSR_ARBEN BIT(1) |
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#define IXP4XX_PCI_CSR_ADS BIT(2) |
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#define IXP4XX_PCI_CSR_PDS BIT(3) |
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#define IXP4XX_PCI_CSR_ABE BIT(4) |
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#define IXP4XX_PCI_CSR_DBT BIT(5) |
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#define IXP4XX_PCI_CSR_ASE BIT(8) |
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#define IXP4XX_PCI_CSR_IC BIT(15) |
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#define IXP4XX_PCI_CSR_PRST BIT(16) |
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/* ISR (Interrupt status) Register bit definitions */ |
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#define IXP4XX_PCI_ISR_PSE BIT(0) |
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#define IXP4XX_PCI_ISR_PFE BIT(1) |
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#define IXP4XX_PCI_ISR_PPE BIT(2) |
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#define IXP4XX_PCI_ISR_AHBE BIT(3) |
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#define IXP4XX_PCI_ISR_APDC BIT(4) |
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#define IXP4XX_PCI_ISR_PADC BIT(5) |
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#define IXP4XX_PCI_ISR_ADB BIT(6) |
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#define IXP4XX_PCI_ISR_PDB BIT(7) |
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/* INTEN (Interrupt Enable) Register bit definitions */ |
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#define IXP4XX_PCI_INTEN_PSE BIT(0) |
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#define IXP4XX_PCI_INTEN_PFE BIT(1) |
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#define IXP4XX_PCI_INTEN_PPE BIT(2) |
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#define IXP4XX_PCI_INTEN_AHBE BIT(3) |
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#define IXP4XX_PCI_INTEN_APDC BIT(4) |
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#define IXP4XX_PCI_INTEN_PADC BIT(5) |
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#define IXP4XX_PCI_INTEN_ADB BIT(6) |
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#define IXP4XX_PCI_INTEN_PDB BIT(7) |
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/* Shift value for byte enable on NP cmd/byte enable register */ |
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#define IXP4XX_PCI_NP_CBE_BESL 4 |
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/* PCI commands supported by NP access unit */ |
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#define NP_CMD_IOREAD 0x2 |
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#define NP_CMD_IOWRITE 0x3 |
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#define NP_CMD_CONFIGREAD 0xa |
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#define NP_CMD_CONFIGWRITE 0xb |
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#define NP_CMD_MEMREAD 0x6 |
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#define NP_CMD_MEMWRITE 0x7 |
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/* Constants for CRP access into local config space */ |
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#define CRP_AD_CBE_BESL 20 |
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#define CRP_AD_CBE_WRITE 0x00010000 |
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/* Special PCI configuration space registers for this controller */ |
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#define IXP4XX_PCI_RTOTTO 0x40 |
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struct ixp4xx_pci { |
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struct device *dev; |
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void __iomem *base; |
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bool errata_hammer; |
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bool host_mode; |
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}; |
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/* |
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* The IXP4xx has a peculiar address bus that will change the |
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* byte order on SoC peripherals depending on whether the device |
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* operates in big-endian or little-endian mode. That means that |
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* readl() and writel() that always use little-endian access |
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* will not work for SoC peripherals such as the PCI controller |
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* when used in big-endian mode. The accesses to the individual |
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* PCI devices on the other hand, are always little-endian and |
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* can use readl() and writel(). |
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* |
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* For local AHB bus access we need to use __raw_[readl|writel]() |
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* to make sure that we access the SoC devices in the CPU native |
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* endianness. |
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*/ |
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static inline u32 ixp4xx_readl(struct ixp4xx_pci *p, u32 reg) |
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{ |
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return __raw_readl(p->base + reg); |
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} |
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static inline void ixp4xx_writel(struct ixp4xx_pci *p, u32 reg, u32 val) |
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{ |
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__raw_writel(val, p->base + reg); |
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} |
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static int ixp4xx_pci_check_master_abort(struct ixp4xx_pci *p) |
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{ |
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u32 isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); |
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if (isr & IXP4XX_PCI_ISR_PFE) { |
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/* Make sure the master abort bit is reset */ |
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ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); |
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dev_dbg(p->dev, "master abort detected\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int ixp4xx_pci_read_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 *data) |
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{ |
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ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); |
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if (p->errata_hammer) { |
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int i; |
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/* |
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* PCI workaround - only works if NP PCI space reads have |
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* no side effects. Hammer the register and read twice 8 |
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* times. last one will be good. |
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*/ |
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for (i = 0; i < 8; i++) { |
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ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); |
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*data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); |
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*data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); |
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} |
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} else { |
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ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); |
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*data = ixp4xx_readl(p, IXP4XX_PCI_NP_RDATA); |
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} |
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return ixp4xx_pci_check_master_abort(p); |
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} |
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static int ixp4xx_pci_write_indirect(struct ixp4xx_pci *p, u32 addr, u32 cmd, u32 data) |
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{ |
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ixp4xx_writel(p, IXP4XX_PCI_NP_AD, addr); |
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/* Set up the write */ |
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ixp4xx_writel(p, IXP4XX_PCI_NP_CBE, cmd); |
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/* Execute the write by writing to NP_WDATA */ |
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ixp4xx_writel(p, IXP4XX_PCI_NP_WDATA, data); |
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return ixp4xx_pci_check_master_abort(p); |
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} |
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static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) |
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{ |
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/* Root bus is always 0 in this hardware */ |
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if (bus_num == 0) { |
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/* type 0 */ |
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return BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | |
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(where & ~3); |
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} else { |
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/* type 1 */ |
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return (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | |
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((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; |
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} |
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} |
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/* |
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* CRP functions are "Controller Configuration Port" accesses |
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* initiated from within this driver itself to read/write PCI |
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* control information in the config space. |
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*/ |
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static u32 ixp4xx_crp_byte_lane_enable_bits(u32 n, int size) |
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{ |
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if (size == 1) |
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return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; |
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if (size == 2) |
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return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; |
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if (size == 4) |
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return 0; |
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return 0xffffffff; |
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} |
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static int ixp4xx_crp_read_config(struct ixp4xx_pci *p, int where, int size, |
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u32 *value) |
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{ |
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u32 n, cmd, val; |
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n = where % 4; |
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cmd = where & ~3; |
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dev_dbg(p->dev, "%s from %d size %d cmd %08x\n", |
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__func__, where, size, cmd); |
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ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); |
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val = ixp4xx_readl(p, IXP4XX_PCI_CRP_RDATA); |
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val >>= (8*n); |
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switch (size) { |
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case 1: |
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val &= U8_MAX; |
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dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); |
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break; |
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case 2: |
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val &= U16_MAX; |
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dev_dbg(p->dev, "%s read word %04x\n", __func__, val); |
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break; |
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case 4: |
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val &= U32_MAX; |
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dev_dbg(p->dev, "%s read long %08x\n", __func__, val); |
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break; |
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default: |
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/* Should not happen */ |
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dev_err(p->dev, "%s illegal size\n", __func__); |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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*value = val; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int ixp4xx_crp_write_config(struct ixp4xx_pci *p, int where, int size, |
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u32 value) |
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{ |
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u32 n, cmd, val; |
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n = where % 4; |
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cmd = ixp4xx_crp_byte_lane_enable_bits(n, size); |
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if (cmd == 0xffffffff) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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cmd |= where & ~3; |
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cmd |= CRP_AD_CBE_WRITE; |
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val = value << (8*n); |
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dev_dbg(p->dev, "%s to %d size %d cmd %08x val %08x\n", |
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__func__, where, size, cmd, val); |
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ixp4xx_writel(p, IXP4XX_PCI_CRP_AD_CBE, cmd); |
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ixp4xx_writel(p, IXP4XX_PCI_CRP_WDATA, val); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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/* |
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* Then follows the functions that read and write from the common PCI |
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* configuration space. |
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*/ |
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static u32 ixp4xx_byte_lane_enable_bits(u32 n, int size) |
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{ |
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if (size == 1) |
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return (0xf & ~BIT(n)) << 4; |
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if (size == 2) |
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return (0xf & ~(BIT(n) | BIT(n+1))) << 4; |
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if (size == 4) |
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return 0; |
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return 0xffffffff; |
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} |
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static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct ixp4xx_pci *p = bus->sysdata; |
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u32 n, addr, val, cmd; |
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u8 bus_num = bus->number; |
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int ret; |
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*value = 0xffffffff; |
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n = where % 4; |
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cmd = ixp4xx_byte_lane_enable_bits(n, size); |
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if (cmd == 0xffffffff) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = ixp4xx_config_addr(bus_num, devfn, where); |
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cmd |= NP_CMD_CONFIGREAD; |
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dev_dbg(p->dev, "read_config from %d size %d dev %d:%d:%d address: %08x cmd: %08x\n", |
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where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); |
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ret = ixp4xx_pci_read_indirect(p, addr, cmd, &val); |
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if (ret) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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val >>= (8*n); |
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switch (size) { |
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case 1: |
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val &= U8_MAX; |
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dev_dbg(p->dev, "%s read byte %02x\n", __func__, val); |
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break; |
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case 2: |
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val &= U16_MAX; |
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dev_dbg(p->dev, "%s read word %04x\n", __func__, val); |
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break; |
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case 4: |
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val &= U32_MAX; |
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dev_dbg(p->dev, "%s read long %08x\n", __func__, val); |
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break; |
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default: |
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/* Should not happen */ |
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dev_err(p->dev, "%s illegal size\n", __func__); |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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*value = val; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct ixp4xx_pci *p = bus->sysdata; |
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u32 n, addr, val, cmd; |
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u8 bus_num = bus->number; |
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int ret; |
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n = where % 4; |
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cmd = ixp4xx_byte_lane_enable_bits(n, size); |
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if (cmd == 0xffffffff) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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addr = ixp4xx_config_addr(bus_num, devfn, where); |
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cmd |= NP_CMD_CONFIGWRITE; |
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val = value << (8*n); |
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dev_dbg(p->dev, "write_config_byte %#x to %d size %d dev %d:%d:%d addr: %08x cmd %08x\n", |
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value, where, size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), addr, cmd); |
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ret = ixp4xx_pci_write_indirect(p, addr, cmd, val); |
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if (ret) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static struct pci_ops ixp4xx_pci_ops = { |
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.read = ixp4xx_pci_read_config, |
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.write = ixp4xx_pci_write_config, |
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}; |
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static u32 ixp4xx_pci_addr_to_64mconf(phys_addr_t addr) |
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{ |
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u8 base; |
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base = ((addr & 0xff000000) >> 24); |
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return (base << 24) | ((base + 1) << 16) |
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| ((base + 2) << 8) | (base + 3); |
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} |
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static int ixp4xx_pci_parse_map_ranges(struct ixp4xx_pci *p) |
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{ |
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struct device *dev = p->dev; |
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); |
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struct resource_entry *win; |
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struct resource *res; |
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phys_addr_t addr; |
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win = resource_list_first_type(&bridge->windows, IORESOURCE_MEM); |
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if (win) { |
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u32 pcimembase; |
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res = win->res; |
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addr = res->start - win->offset; |
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if (res->flags & IORESOURCE_PREFETCH) |
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res->name = "IXP4xx PCI PRE-MEM"; |
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else |
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res->name = "IXP4xx PCI NON-PRE-MEM"; |
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dev_dbg(dev, "%s window %pR, bus addr %pa\n", |
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res->name, res, &addr); |
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if (resource_size(res) != SZ_64M) { |
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dev_err(dev, "memory range is not 64MB\n"); |
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return -EINVAL; |
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} |
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pcimembase = ixp4xx_pci_addr_to_64mconf(addr); |
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/* Commit configuration */ |
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ixp4xx_writel(p, IXP4XX_PCI_PCIMEMBASE, pcimembase); |
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} else { |
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dev_err(dev, "no AHB memory mapping defined\n"); |
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} |
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win = resource_list_first_type(&bridge->windows, IORESOURCE_IO); |
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if (win) { |
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res = win->res; |
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addr = pci_pio_to_address(res->start); |
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if (addr & 0xff) { |
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dev_err(dev, "IO mem at uneven address: %pa\n", &addr); |
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return -EINVAL; |
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} |
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res->name = "IXP4xx PCI IO MEM"; |
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/* |
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* Setup I/O space location for PCI->AHB access, the |
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* upper 24 bits of the address goes into the lower |
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* 24 bits of this register. |
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*/ |
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ixp4xx_writel(p, IXP4XX_PCI_AHBIOBASE, (addr >> 8)); |
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} else { |
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dev_info(dev, "no IO space AHB memory mapping defined\n"); |
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} |
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return 0; |
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} |
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static int ixp4xx_pci_parse_map_dma_ranges(struct ixp4xx_pci *p) |
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{ |
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struct device *dev = p->dev; |
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p); |
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struct resource_entry *win; |
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struct resource *res; |
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phys_addr_t addr; |
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u32 ahbmembase; |
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win = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM); |
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if (win) { |
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res = win->res; |
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addr = res->start - win->offset; |
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if (resource_size(res) != SZ_64M) { |
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dev_err(dev, "DMA memory range is not 64MB\n"); |
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return -EINVAL; |
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} |
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dev_dbg(dev, "DMA MEM BASE: %pa\n", &addr); |
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/* |
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* 4 PCI-to-AHB windows of 16 MB each, write the 8 high bits |
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* into each byte of the PCI_AHBMEMBASE register. |
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*/ |
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ahbmembase = ixp4xx_pci_addr_to_64mconf(addr); |
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/* Commit AHB membase */ |
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ixp4xx_writel(p, IXP4XX_PCI_AHBMEMBASE, ahbmembase); |
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} else { |
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dev_err(dev, "no DMA memory range defined\n"); |
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} |
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return 0; |
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} |
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/* Only used to get context for abort handling */ |
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static struct ixp4xx_pci *ixp4xx_pci_abort_singleton; |
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static int ixp4xx_pci_abort_handler(unsigned long addr, unsigned int fsr, |
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struct pt_regs *regs) |
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{ |
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struct ixp4xx_pci *p = ixp4xx_pci_abort_singleton; |
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u32 isr, status; |
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int ret; |
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isr = ixp4xx_readl(p, IXP4XX_PCI_ISR); |
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ret = ixp4xx_crp_read_config(p, PCI_STATUS, 2, &status); |
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if (ret) { |
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dev_err(p->dev, "unable to read abort status\n"); |
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return -EINVAL; |
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} |
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dev_err(p->dev, |
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"PCI: abort_handler addr = %#lx, isr = %#x, status = %#x\n", |
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addr, isr, status); |
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/* Make sure the Master Abort bit is reset */ |
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ixp4xx_writel(p, IXP4XX_PCI_ISR, IXP4XX_PCI_ISR_PFE); |
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status |= PCI_STATUS_REC_MASTER_ABORT; |
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ret = ixp4xx_crp_write_config(p, PCI_STATUS, 2, status); |
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if (ret) |
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dev_err(p->dev, "unable to clear abort status bit\n"); |
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/* |
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* If it was an imprecise abort, then we need to correct the |
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* return address to be _after_ the instruction. |
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*/ |
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if (fsr & (1 << 10)) { |
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dev_err(p->dev, "imprecise abort\n"); |
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regs->ARM_pc += 4; |
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} |
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return 0; |
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} |
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static int __init ixp4xx_pci_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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struct ixp4xx_pci *p; |
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struct pci_host_bridge *host; |
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int ret; |
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u32 val; |
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phys_addr_t addr; |
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u32 basereg[4] = { |
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PCI_BASE_ADDRESS_0, |
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PCI_BASE_ADDRESS_1, |
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PCI_BASE_ADDRESS_2, |
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PCI_BASE_ADDRESS_3, |
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}; |
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int i; |
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host = devm_pci_alloc_host_bridge(dev, sizeof(*p)); |
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if (!host) |
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return -ENOMEM; |
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host->ops = &ixp4xx_pci_ops; |
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p = pci_host_bridge_priv(host); |
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host->sysdata = p; |
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p->dev = dev; |
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dev_set_drvdata(dev, p); |
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/* |
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* Set up quirk for erratic behaviour in the 42x variant |
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* when accessing config space. |
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*/ |
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if (of_device_is_compatible(np, "intel,ixp42x-pci")) { |
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p->errata_hammer = true; |
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dev_info(dev, "activate hammering errata\n"); |
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} |
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p->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(p->base)) |
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return PTR_ERR(p->base); |
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val = ixp4xx_readl(p, IXP4XX_PCI_CSR); |
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p->host_mode = !!(val & IXP4XX_PCI_CSR_HOST); |
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dev_info(dev, "controller is in %s mode\n", |
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p->host_mode ? "host" : "option"); |
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/* Hook in our fault handler for PCI errors */ |
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ixp4xx_pci_abort_singleton = p; |
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hook_fault_code(16+6, ixp4xx_pci_abort_handler, SIGBUS, 0, |
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"imprecise external abort"); |
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ret = ixp4xx_pci_parse_map_ranges(p); |
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if (ret) |
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return ret; |
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ret = ixp4xx_pci_parse_map_dma_ranges(p); |
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if (ret) |
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return ret; |
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/* This is only configured in host mode */ |
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if (p->host_mode) { |
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addr = __pa(PAGE_OFFSET); |
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/* This is a noop (0x00) but explains what is going on */ |
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addr |= PCI_BASE_ADDRESS_SPACE_MEMORY; |
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for (i = 0; i < 4; i++) { |
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/* Write this directly into the config space */ |
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ret = ixp4xx_crp_write_config(p, basereg[i], 4, addr); |
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if (ret) |
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dev_err(dev, "failed to set up PCI_BASE_ADDRESS_%d\n", i); |
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else |
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dev_info(dev, "set PCI_BASE_ADDR_%d to %pa\n", i, &addr); |
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addr += SZ_16M; |
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} |
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/* |
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* Enable CSR window at 64 MiB to allow PCI masters to continue |
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* prefetching past the 64 MiB boundary, if all AHB to PCI |
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* windows are consecutive. |
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*/ |
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ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_4, 4, addr); |
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if (ret) |
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dev_err(dev, "failed to set up PCI_BASE_ADDRESS_4\n"); |
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else |
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dev_info(dev, "set PCI_BASE_ADDR_4 to %pa\n", &addr); |
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/* |
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* Put the IO memory window at the very end of physical memory |
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* at 0xfffffc00. This is when the system is trying to access IO |
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* memory over AHB. |
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*/ |
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addr = 0xfffffc00; |
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addr |= PCI_BASE_ADDRESS_SPACE_IO; |
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ret = ixp4xx_crp_write_config(p, PCI_BASE_ADDRESS_5, 4, addr); |
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if (ret) |
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dev_err(dev, "failed to set up PCI_BASE_ADDRESS_5\n"); |
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else |
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dev_info(dev, "set PCI_BASE_ADDR_5 to %pa\n", &addr); |
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/* |
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* Retry timeout to 0x80 |
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* Transfer ready timeout to 0xff |
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*/ |
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ret = ixp4xx_crp_write_config(p, IXP4XX_PCI_RTOTTO, 4, |
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0x000080ff); |
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if (ret) |
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dev_err(dev, "failed to set up TRDY limit\n"); |
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else |
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dev_info(dev, "set TRDY limit to 0x80ff\n"); |
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} |
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/* Clear interrupts */ |
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val = IXP4XX_PCI_ISR_PSE | IXP4XX_PCI_ISR_PFE | IXP4XX_PCI_ISR_PPE | IXP4XX_PCI_ISR_AHBE; |
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ixp4xx_writel(p, IXP4XX_PCI_ISR, val); |
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/* |
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* Set Initialize Complete in PCI Control Register: allow IXP4XX to |
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* generate PCI configuration cycles. Specify that the AHB bus is |
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* operating in big-endian mode. Set up byte lane swapping between |
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* little-endian PCI and the big-endian AHB bus. |
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*/ |
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val = IXP4XX_PCI_CSR_IC | IXP4XX_PCI_CSR_ABE; |
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) |
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val |= (IXP4XX_PCI_CSR_PDS | IXP4XX_PCI_CSR_ADS); |
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ixp4xx_writel(p, IXP4XX_PCI_CSR, val); |
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ret = ixp4xx_crp_write_config(p, PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
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if (ret) |
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dev_err(dev, "unable to initialize master and command memory\n"); |
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else |
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dev_info(dev, "initialized as master\n"); |
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pci_host_probe(host); |
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return 0; |
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} |
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static const struct of_device_id ixp4xx_pci_of_match[] = { |
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{ |
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.compatible = "intel,ixp42x-pci", |
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}, |
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{ |
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.compatible = "intel,ixp43x-pci", |
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}, |
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{}, |
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}; |
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/* |
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* This driver needs to be a builtin module with suppressed bind |
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* attributes since the probe() is initializing a hard exception |
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* handler and this can only be done from __init-tagged code |
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* sections. This module cannot be removed and inserted at all. |
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*/ |
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static struct platform_driver ixp4xx_pci_driver = { |
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.driver = { |
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.name = "ixp4xx-pci", |
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.suppress_bind_attrs = true, |
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.of_match_table = ixp4xx_pci_of_match, |
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}, |
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}; |
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builtin_platform_driver_probe(ixp4xx_pci_driver, ixp4xx_pci_probe);
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