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149 lines
3.6 KiB
149 lines
3.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* This file is part of wl12xx |
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* |
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* Copyright (C) 2011 Texas Instruments Inc. |
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*/ |
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#ifndef __WL12XX_PRIV_H__ |
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#define __WL12XX_PRIV_H__ |
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#include "conf.h" |
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/* WiLink 6/7 chip IDs */ |
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#define CHIP_ID_127X_PG10 (0x04030101) |
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#define CHIP_ID_127X_PG20 (0x04030111) |
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#define CHIP_ID_128X_PG10 (0x05030101) |
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#define CHIP_ID_128X_PG20 (0x05030111) |
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/* FW chip version for wl127x */ |
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#define WL127X_CHIP_VER 6 |
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/* minimum single-role FW version for wl127x */ |
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#define WL127X_IFTYPE_SR_VER 3 |
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#define WL127X_MAJOR_SR_VER 10 |
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#define WL127X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE |
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#define WL127X_MINOR_SR_VER 133 |
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/* minimum multi-role FW version for wl127x */ |
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#define WL127X_IFTYPE_MR_VER 5 |
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#define WL127X_MAJOR_MR_VER 7 |
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#define WL127X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE |
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#define WL127X_MINOR_MR_VER 42 |
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/* FW chip version for wl128x */ |
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#define WL128X_CHIP_VER 7 |
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/* minimum single-role FW version for wl128x */ |
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#define WL128X_IFTYPE_SR_VER 3 |
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#define WL128X_MAJOR_SR_VER 10 |
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#define WL128X_SUBTYPE_SR_VER WLCORE_FW_VER_IGNORE |
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#define WL128X_MINOR_SR_VER 133 |
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/* minimum multi-role FW version for wl128x */ |
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#define WL128X_IFTYPE_MR_VER 5 |
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#define WL128X_MAJOR_MR_VER 7 |
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#define WL128X_SUBTYPE_MR_VER WLCORE_FW_VER_IGNORE |
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#define WL128X_MINOR_MR_VER 42 |
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#define WL12XX_AGGR_BUFFER_SIZE (4 * PAGE_SIZE) |
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#define WL12XX_NUM_TX_DESCRIPTORS 16 |
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#define WL12XX_NUM_RX_DESCRIPTORS 8 |
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#define WL12XX_NUM_MAC_ADDRESSES 2 |
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#define WL12XX_RX_BA_MAX_SESSIONS 3 |
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#define WL12XX_MAX_AP_STATIONS 8 |
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#define WL12XX_MAX_LINKS 12 |
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struct wl127x_rx_mem_pool_addr { |
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u32 addr; |
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u32 addr_extra; |
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}; |
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struct wl12xx_priv { |
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struct wl12xx_priv_conf conf; |
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int ref_clock; |
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int tcxo_clock; |
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struct wl127x_rx_mem_pool_addr *rx_mem_addr; |
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}; |
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/* Reference clock values */ |
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enum { |
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WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ |
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WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ |
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WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ |
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WL12XX_REFCLOCK_52 = 3, /* 52 MHz */ |
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WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */ |
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WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ |
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}; |
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/* TCXO clock values */ |
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enum { |
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WL12XX_TCXOCLOCK_19_2 = 0, /* 19.2MHz */ |
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WL12XX_TCXOCLOCK_26 = 1, /* 26 MHz */ |
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WL12XX_TCXOCLOCK_38_4 = 2, /* 38.4MHz */ |
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WL12XX_TCXOCLOCK_52 = 3, /* 52 MHz */ |
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WL12XX_TCXOCLOCK_16_368 = 4, /* 16.368 MHz */ |
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WL12XX_TCXOCLOCK_32_736 = 5, /* 32.736 MHz */ |
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WL12XX_TCXOCLOCK_16_8 = 6, /* 16.8 MHz */ |
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WL12XX_TCXOCLOCK_33_6 = 7, /* 33.6 MHz */ |
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}; |
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struct wl12xx_clock { |
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u32 freq; |
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bool xtal; |
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u8 hw_idx; |
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}; |
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struct wl12xx_fw_packet_counters { |
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/* Cumulative counter of released packets per AC */ |
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u8 tx_released_pkts[NUM_TX_QUEUES]; |
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/* Cumulative counter of freed packets per HLID */ |
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u8 tx_lnk_free_pkts[WL12XX_MAX_LINKS]; |
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/* Cumulative counter of released Voice memory blocks */ |
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u8 tx_voice_released_blks; |
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/* Tx rate of the last transmitted packet */ |
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u8 tx_last_rate; |
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u8 padding[2]; |
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} __packed; |
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/* FW status registers */ |
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struct wl12xx_fw_status { |
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__le32 intr; |
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u8 fw_rx_counter; |
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u8 drv_rx_counter; |
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u8 reserved; |
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u8 tx_results_counter; |
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__le32 rx_pkt_descs[WL12XX_NUM_RX_DESCRIPTORS]; |
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__le32 fw_localtime; |
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/* |
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* A bitmap (where each bit represents a single HLID) |
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* to indicate if the station is in PS mode. |
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*/ |
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__le32 link_ps_bitmap; |
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/* |
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* A bitmap (where each bit represents a single HLID) to indicate |
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* if the station is in Fast mode |
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*/ |
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__le32 link_fast_bitmap; |
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/* Cumulative counter of total released mem blocks since FW-reset */ |
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__le32 total_released_blks; |
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/* Size (in Memory Blocks) of TX pool */ |
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__le32 tx_total; |
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struct wl12xx_fw_packet_counters counters; |
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__le32 log_start_addr; |
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} __packed; |
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#endif /* __WL12XX_PRIV_H__ */
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