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522 lines
14 KiB
522 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Driver for Vitesse PHYs |
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* |
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* Author: Kriston Carson |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mii.h> |
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#include <linux/ethtool.h> |
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#include <linux/phy.h> |
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/* Vitesse Extended Page Magic Register(s) */ |
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#define MII_VSC82X4_EXT_PAGE_16E 0x10 |
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#define MII_VSC82X4_EXT_PAGE_17E 0x11 |
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#define MII_VSC82X4_EXT_PAGE_18E 0x12 |
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/* Vitesse Extended Control Register 1 */ |
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#define MII_VSC8244_EXT_CON1 0x17 |
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#define MII_VSC8244_EXTCON1_INIT 0x0000 |
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#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00 |
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#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300 |
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#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800 |
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#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200 |
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/* Vitesse Interrupt Mask Register */ |
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#define MII_VSC8244_IMASK 0x19 |
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#define MII_VSC8244_IMASK_IEN 0x8000 |
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#define MII_VSC8244_IMASK_SPEED 0x4000 |
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#define MII_VSC8244_IMASK_LINK 0x2000 |
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#define MII_VSC8244_IMASK_DUPLEX 0x1000 |
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#define MII_VSC8244_IMASK_MASK 0xf000 |
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#define MII_VSC8221_IMASK_MASK 0xa000 |
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/* Vitesse Interrupt Status Register */ |
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#define MII_VSC8244_ISTAT 0x1a |
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#define MII_VSC8244_ISTAT_STATUS 0x8000 |
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#define MII_VSC8244_ISTAT_SPEED 0x4000 |
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#define MII_VSC8244_ISTAT_LINK 0x2000 |
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#define MII_VSC8244_ISTAT_DUPLEX 0x1000 |
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#define MII_VSC8244_ISTAT_MASK (MII_VSC8244_ISTAT_SPEED | \ |
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MII_VSC8244_ISTAT_LINK | \ |
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MII_VSC8244_ISTAT_DUPLEX) |
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#define MII_VSC8221_ISTAT_MASK MII_VSC8244_ISTAT_LINK |
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/* Vitesse Auxiliary Control/Status Register */ |
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#define MII_VSC8244_AUX_CONSTAT 0x1c |
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#define MII_VSC8244_AUXCONSTAT_INIT 0x0000 |
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#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020 |
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#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018 |
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#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010 |
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#define MII_VSC8244_AUXCONSTAT_100 0x0008 |
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#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */ |
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#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004 |
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/* Vitesse Extended Page Access Register */ |
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#define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f |
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/* Vitesse VSC8601 Extended PHY Control Register 1 */ |
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#define MII_VSC8601_EPHY_CTL 0x17 |
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#define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8) |
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#define PHY_ID_VSC8234 0x000fc620 |
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#define PHY_ID_VSC8244 0x000fc6c0 |
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#define PHY_ID_VSC8572 0x000704d0 |
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#define PHY_ID_VSC8601 0x00070420 |
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#define PHY_ID_VSC7385 0x00070450 |
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#define PHY_ID_VSC7388 0x00070480 |
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#define PHY_ID_VSC7395 0x00070550 |
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#define PHY_ID_VSC7398 0x00070580 |
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#define PHY_ID_VSC8662 0x00070660 |
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#define PHY_ID_VSC8221 0x000fc550 |
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#define PHY_ID_VSC8211 0x000fc4b0 |
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MODULE_DESCRIPTION("Vitesse PHY driver"); |
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MODULE_AUTHOR("Kriston Carson"); |
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MODULE_LICENSE("GPL"); |
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static int vsc824x_add_skew(struct phy_device *phydev) |
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{ |
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int err; |
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int extcon; |
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extcon = phy_read(phydev, MII_VSC8244_EXT_CON1); |
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if (extcon < 0) |
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return extcon; |
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extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK | |
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MII_VSC8244_EXTCON1_RX_SKEW_MASK); |
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extcon |= (MII_VSC8244_EXTCON1_TX_SKEW | |
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MII_VSC8244_EXTCON1_RX_SKEW); |
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err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); |
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return err; |
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} |
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static int vsc824x_config_init(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, |
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MII_VSC8244_AUXCONSTAT_INIT); |
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if (err < 0) |
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return err; |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
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err = vsc824x_add_skew(phydev); |
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return err; |
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} |
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#define VSC73XX_EXT_PAGE_ACCESS 0x1f |
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static int vsc73xx_read_page(struct phy_device *phydev) |
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{ |
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return __phy_read(phydev, VSC73XX_EXT_PAGE_ACCESS); |
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} |
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static int vsc73xx_write_page(struct phy_device *phydev, int page) |
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{ |
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return __phy_write(phydev, VSC73XX_EXT_PAGE_ACCESS, page); |
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} |
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static void vsc73xx_config_init(struct phy_device *phydev) |
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{ |
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/* Receiver init */ |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x0c, 0x0300, 0x0200); |
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phy_write(phydev, 0x1f, 0x0000); |
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/* Config LEDs 0x61 */ |
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phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061); |
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} |
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static int vsc738x_config_init(struct phy_device *phydev) |
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{ |
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u16 rev; |
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/* This magic sequence appear in the application note |
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* "VSC7385/7388 PHY Configuration". |
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* |
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* Maybe one day we will get to know what it all means. |
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*/ |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0200); |
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phy_write(phydev, 0x1f, 0x52b5); |
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phy_write(phydev, 0x10, 0xb68a); |
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phy_modify(phydev, 0x12, 0xff07, 0x0003); |
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phy_modify(phydev, 0x11, 0x00ff, 0x00a2); |
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phy_write(phydev, 0x10, 0x968a); |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0000); |
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phy_write(phydev, 0x1f, 0x0000); |
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/* Read revision */ |
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rev = phy_read(phydev, MII_PHYSID2); |
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rev &= 0x0f; |
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/* Special quirk for revision 0 */ |
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if (rev == 0) { |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0200); |
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phy_write(phydev, 0x1f, 0x52b5); |
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phy_write(phydev, 0x12, 0x0000); |
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phy_write(phydev, 0x11, 0x0689); |
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phy_write(phydev, 0x10, 0x8f92); |
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phy_write(phydev, 0x1f, 0x52b5); |
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phy_write(phydev, 0x12, 0x0000); |
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phy_write(phydev, 0x11, 0x0e35); |
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phy_write(phydev, 0x10, 0x9786); |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0000); |
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phy_write(phydev, 0x17, 0xff80); |
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phy_write(phydev, 0x17, 0x0000); |
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} |
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phy_write(phydev, 0x1f, 0x0000); |
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phy_write(phydev, 0x12, 0x0048); |
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if (rev == 0) { |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_write(phydev, 0x14, 0x6600); |
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phy_write(phydev, 0x1f, 0x0000); |
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phy_write(phydev, 0x18, 0xa24e); |
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} else { |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x16, 0x0fc0, 0x0240); |
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phy_modify(phydev, 0x14, 0x6000, 0x4000); |
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/* bits 14-15 in extended register 0x14 controls DACG amplitude |
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* 6 = -8%, 2 is hardware default |
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*/ |
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phy_write(phydev, 0x1f, 0x0001); |
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phy_modify(phydev, 0x14, 0xe000, 0x6000); |
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phy_write(phydev, 0x1f, 0x0000); |
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} |
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vsc73xx_config_init(phydev); |
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return 0; |
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} |
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static int vsc739x_config_init(struct phy_device *phydev) |
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{ |
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/* This magic sequence appears in the VSC7395 SparX-G5e application |
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* note "VSC7395/VSC7398 PHY Configuration" |
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* |
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* Maybe one day we will get to know what it all means. |
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*/ |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0200); |
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phy_write(phydev, 0x1f, 0x52b5); |
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phy_write(phydev, 0x10, 0xb68a); |
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phy_modify(phydev, 0x12, 0xff07, 0x0003); |
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phy_modify(phydev, 0x11, 0x00ff, 0x00a2); |
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phy_write(phydev, 0x10, 0x968a); |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x08, 0x0200, 0x0000); |
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phy_write(phydev, 0x1f, 0x0000); |
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phy_write(phydev, 0x1f, 0x0000); |
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phy_write(phydev, 0x12, 0x0048); |
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phy_write(phydev, 0x1f, 0x2a30); |
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phy_modify(phydev, 0x16, 0x0fc0, 0x0240); |
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phy_modify(phydev, 0x14, 0x6000, 0x4000); |
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phy_write(phydev, 0x1f, 0x0001); |
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phy_modify(phydev, 0x14, 0xe000, 0x6000); |
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phy_write(phydev, 0x1f, 0x0000); |
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vsc73xx_config_init(phydev); |
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return 0; |
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} |
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static int vsc73xx_config_aneg(struct phy_device *phydev) |
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{ |
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/* The VSC73xx switches does not like to be instructed to |
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* do autonegotiation in any way, it prefers that you just go |
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* with the power-on/reset defaults. Writing some registers will |
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* just make autonegotiation permanently fail. |
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*/ |
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return 0; |
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} |
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/* This adds a skew for both TX and RX clocks, so the skew should only be |
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* applied to "rgmii-id" interfaces. It may not work as expected |
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* on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. |
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*/ |
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static int vsc8601_add_skew(struct phy_device *phydev) |
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{ |
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int ret; |
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ret = phy_read(phydev, MII_VSC8601_EPHY_CTL); |
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if (ret < 0) |
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return ret; |
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ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW; |
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return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret); |
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} |
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static int vsc8601_config_init(struct phy_device *phydev) |
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{ |
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int ret = 0; |
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
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ret = vsc8601_add_skew(phydev); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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static int vsc82xx_config_intr(struct phy_device *phydev) |
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{ |
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int err; |
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
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/* Don't bother to ACK the interrupts since the 824x cannot |
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* clear the interrupts if they are disabled. |
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*/ |
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err = phy_write(phydev, MII_VSC8244_IMASK, |
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(phydev->drv->phy_id == PHY_ID_VSC8234 || |
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phydev->drv->phy_id == PHY_ID_VSC8244 || |
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phydev->drv->phy_id == PHY_ID_VSC8572 || |
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phydev->drv->phy_id == PHY_ID_VSC8601) ? |
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MII_VSC8244_IMASK_MASK : |
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MII_VSC8221_IMASK_MASK); |
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else { |
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/* The Vitesse PHY cannot clear the interrupt |
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* once it has disabled them, so we clear them first |
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*/ |
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err = phy_read(phydev, MII_VSC8244_ISTAT); |
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if (err < 0) |
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return err; |
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err = phy_write(phydev, MII_VSC8244_IMASK, 0); |
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} |
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return err; |
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} |
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static irqreturn_t vsc82xx_handle_interrupt(struct phy_device *phydev) |
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{ |
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int irq_status, irq_mask; |
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if (phydev->drv->phy_id == PHY_ID_VSC8244 || |
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phydev->drv->phy_id == PHY_ID_VSC8572 || |
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phydev->drv->phy_id == PHY_ID_VSC8601) |
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irq_mask = MII_VSC8244_ISTAT_MASK; |
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else |
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irq_mask = MII_VSC8221_ISTAT_MASK; |
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irq_status = phy_read(phydev, MII_VSC8244_ISTAT); |
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if (irq_status < 0) { |
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phy_error(phydev); |
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return IRQ_NONE; |
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} |
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if (!(irq_status & irq_mask)) |
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return IRQ_NONE; |
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phy_trigger_machine(phydev); |
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return IRQ_HANDLED; |
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} |
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static int vsc8221_config_init(struct phy_device *phydev) |
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{ |
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int err; |
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err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, |
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MII_VSC8221_AUXCONSTAT_INIT); |
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return err; |
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/* Perhaps we should set EXT_CON1 based on the interface? |
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* Options are 802.3Z SerDes or SGMII |
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*/ |
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} |
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/* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links |
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* @phydev: target phy_device struct |
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* |
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* Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing |
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* special values in the VSC8234/VSC8244 extended reserved registers |
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*/ |
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static int vsc82x4_config_autocross_enable(struct phy_device *phydev) |
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{ |
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int ret; |
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if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100) |
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return 0; |
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/* map extended registers set 0x10 - 0x1e */ |
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ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5); |
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if (ret >= 0) |
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ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012); |
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if (ret >= 0) |
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ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803); |
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if (ret >= 0) |
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ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa); |
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/* map standard registers set 0x10 - 0x1e */ |
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if (ret >= 0) |
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ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); |
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else |
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phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); |
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return ret; |
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} |
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/* vsc82x4_config_aneg - restart auto-negotiation or write BMCR |
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* @phydev: target phy_device struct |
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* |
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* Description: If auto-negotiation is enabled, we configure the |
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* advertising, and then restart auto-negotiation. If it is not |
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* enabled, then we write the BMCR and also start the auto |
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* MDI/MDI-X feature |
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*/ |
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static int vsc82x4_config_aneg(struct phy_device *phydev) |
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{ |
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int ret; |
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/* Enable auto MDI/MDI-X when in 10/100 forced link speeds by |
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* writing special values in the VSC8234 extended reserved registers |
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*/ |
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if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) { |
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ret = genphy_setup_forced(phydev); |
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if (ret < 0) /* error */ |
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return ret; |
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return vsc82x4_config_autocross_enable(phydev); |
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} |
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return genphy_config_aneg(phydev); |
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} |
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/* Vitesse 82xx */ |
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static struct phy_driver vsc82xx_driver[] = { |
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{ |
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.phy_id = PHY_ID_VSC8234, |
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.name = "Vitesse VSC8234", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc824x_config_init, |
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.config_aneg = &vsc82x4_config_aneg, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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.phy_id = PHY_ID_VSC8244, |
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.name = "Vitesse VSC8244", |
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.phy_id_mask = 0x000fffc0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc824x_config_init, |
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.config_aneg = &vsc82x4_config_aneg, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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.phy_id = PHY_ID_VSC8572, |
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.name = "Vitesse VSC8572", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc824x_config_init, |
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.config_aneg = &vsc82x4_config_aneg, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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.phy_id = PHY_ID_VSC8601, |
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.name = "Vitesse VSC8601", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc8601_config_init, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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.phy_id = PHY_ID_VSC7385, |
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.name = "Vitesse VSC7385", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = vsc738x_config_init, |
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.config_aneg = vsc73xx_config_aneg, |
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.read_page = vsc73xx_read_page, |
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.write_page = vsc73xx_write_page, |
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}, { |
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.phy_id = PHY_ID_VSC7388, |
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.name = "Vitesse VSC7388", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = vsc738x_config_init, |
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.config_aneg = vsc73xx_config_aneg, |
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.read_page = vsc73xx_read_page, |
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.write_page = vsc73xx_write_page, |
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}, { |
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.phy_id = PHY_ID_VSC7395, |
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.name = "Vitesse VSC7395", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = vsc739x_config_init, |
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.config_aneg = vsc73xx_config_aneg, |
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.read_page = vsc73xx_read_page, |
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.write_page = vsc73xx_write_page, |
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}, { |
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.phy_id = PHY_ID_VSC7398, |
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.name = "Vitesse VSC7398", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = vsc739x_config_init, |
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.config_aneg = vsc73xx_config_aneg, |
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.read_page = vsc73xx_read_page, |
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.write_page = vsc73xx_write_page, |
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}, { |
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.phy_id = PHY_ID_VSC8662, |
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.name = "Vitesse VSC8662", |
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.phy_id_mask = 0x000ffff0, |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc824x_config_init, |
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.config_aneg = &vsc82x4_config_aneg, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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/* Vitesse 8221 */ |
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.phy_id = PHY_ID_VSC8221, |
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.phy_id_mask = 0x000ffff0, |
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.name = "Vitesse VSC8221", |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc8221_config_init, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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}, { |
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/* Vitesse 8211 */ |
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.phy_id = PHY_ID_VSC8211, |
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.phy_id_mask = 0x000ffff0, |
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.name = "Vitesse VSC8211", |
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/* PHY_GBIT_FEATURES */ |
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.config_init = &vsc8221_config_init, |
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.config_intr = &vsc82xx_config_intr, |
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.handle_interrupt = &vsc82xx_handle_interrupt, |
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} }; |
|
|
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module_phy_driver(vsc82xx_driver); |
|
|
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static struct mdio_device_id __maybe_unused vitesse_tbl[] = { |
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{ PHY_ID_VSC8234, 0x000ffff0 }, |
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{ PHY_ID_VSC8244, 0x000fffc0 }, |
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{ PHY_ID_VSC8572, 0x000ffff0 }, |
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{ PHY_ID_VSC7385, 0x000ffff0 }, |
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{ PHY_ID_VSC7388, 0x000ffff0 }, |
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{ PHY_ID_VSC7395, 0x000ffff0 }, |
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{ PHY_ID_VSC7398, 0x000ffff0 }, |
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{ PHY_ID_VSC8662, 0x000ffff0 }, |
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{ PHY_ID_VSC8221, 0x000ffff0 }, |
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{ PHY_ID_VSC8211, 0x000ffff0 }, |
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{ } |
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}; |
|
|
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MODULE_DEVICE_TABLE(mdio, vitesse_tbl);
|
|
|