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127 lines
3.3 KiB
127 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* MDIO bus driver for the Xilinx TEMAC device |
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* |
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* Copyright (c) 2009 Secret Lab Technologies, Ltd. |
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*/ |
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#include <linux/io.h> |
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#include <linux/netdevice.h> |
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#include <linux/mutex.h> |
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#include <linux/phy.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/of_address.h> |
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#include <linux/slab.h> |
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#include <linux/of_mdio.h> |
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#include <linux/platform_data/xilinx-ll-temac.h> |
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#include "ll_temac.h" |
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/* --------------------------------------------------------------------- |
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* MDIO Bus functions |
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*/ |
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static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg) |
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{ |
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struct temac_local *lp = bus->priv; |
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u32 rc; |
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unsigned long flags; |
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/* Write the PHY address to the MIIM Access Initiator register. |
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* When the transfer completes, the PHY register value will appear |
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* in the LSW0 register */ |
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spin_lock_irqsave(lp->indirect_lock, flags); |
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temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg); |
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rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET); |
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spin_unlock_irqrestore(lp->indirect_lock, flags); |
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dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n", |
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phy_id, reg, rc); |
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return rc; |
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} |
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static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) |
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{ |
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struct temac_local *lp = bus->priv; |
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unsigned long flags; |
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dev_dbg(lp->dev, "temac_mdio_write(phy_id=%i, reg=%x, val=%x)\n", |
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phy_id, reg, val); |
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/* First write the desired value into the write data register |
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* and then write the address into the access initiator register |
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*/ |
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spin_lock_irqsave(lp->indirect_lock, flags); |
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temac_indirect_out32_locked(lp, XTE_MGTDR_OFFSET, val); |
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temac_indirect_out32_locked(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg); |
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spin_unlock_irqrestore(lp->indirect_lock, flags); |
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return 0; |
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} |
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int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev) |
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{ |
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struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev); |
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struct device_node *np = dev_of_node(&pdev->dev); |
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struct mii_bus *bus; |
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u32 bus_hz; |
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int clk_div; |
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int rc; |
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struct resource res; |
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/* Get MDIO bus frequency (if specified) */ |
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bus_hz = 0; |
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if (np) |
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of_property_read_u32(np, "clock-frequency", &bus_hz); |
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else if (pdata) |
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bus_hz = pdata->mdio_clk_freq; |
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/* Calculate a reasonable divisor for the clock rate */ |
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clk_div = 0x3f; /* worst-case default setting */ |
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if (bus_hz != 0) { |
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clk_div = bus_hz / (2500 * 1000 * 2) - 1; |
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if (clk_div < 1) |
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clk_div = 1; |
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if (clk_div > 0x3f) |
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clk_div = 0x3f; |
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} |
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/* Enable the MDIO bus by asserting the enable bit and writing |
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* in the clock config */ |
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temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); |
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bus = devm_mdiobus_alloc(&pdev->dev); |
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if (!bus) |
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return -ENOMEM; |
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if (np) { |
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of_address_to_resource(np, 0, &res); |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", |
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(unsigned long long)res.start); |
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} else if (pdata) { |
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snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", |
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pdata->mdio_bus_id); |
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} |
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bus->priv = lp; |
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bus->name = "Xilinx TEMAC MDIO"; |
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bus->read = temac_mdio_read; |
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bus->write = temac_mdio_write; |
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bus->parent = lp->dev; |
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lp->mii_bus = bus; |
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rc = of_mdiobus_register(bus, np); |
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if (rc) |
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return rc; |
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dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n", |
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temac_indirect_in32(lp, XTE_MC_OFFSET)); |
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return 0; |
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} |
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void temac_mdio_teardown(struct temac_local *lp) |
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{ |
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mdiobus_unregister(lp->mii_bus); |
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}
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