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405 lines
13 KiB
405 lines
13 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef XILINX_LL_TEMAC_H |
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#define XILINX_LL_TEMAC_H |
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#include <linux/netdevice.h> |
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#include <linux/of.h> |
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#include <linux/spinlock.h> |
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#ifdef CONFIG_PPC_DCR |
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#include <asm/dcr.h> |
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#include <asm/dcr-regs.h> |
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#endif |
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/* packet size info */ |
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#define XTE_HDR_SIZE 14 /* size of Ethernet header */ |
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#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */ |
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#define XTE_JUMBO_MTU 9000 |
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#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE) |
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/* Configuration options */ |
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/* Accept all incoming packets. |
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* This option defaults to disabled (cleared) */ |
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#define XTE_OPTION_PROMISC (1 << 0) |
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/* Jumbo frame support for Tx & Rx. |
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* This option defaults to disabled (cleared) */ |
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#define XTE_OPTION_JUMBO (1 << 1) |
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/* VLAN Rx & Tx frame support. |
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* This option defaults to disabled (cleared) */ |
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#define XTE_OPTION_VLAN (1 << 2) |
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/* Enable recognition of flow control frames on Rx |
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* This option defaults to enabled (set) */ |
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#define XTE_OPTION_FLOW_CONTROL (1 << 4) |
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/* Strip FCS and PAD from incoming frames. |
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* Note: PAD from VLAN frames is not stripped. |
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* This option defaults to disabled (set) */ |
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#define XTE_OPTION_FCS_STRIP (1 << 5) |
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/* Generate FCS field and add PAD automatically for outgoing frames. |
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* This option defaults to enabled (set) */ |
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#define XTE_OPTION_FCS_INSERT (1 << 6) |
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/* Enable Length/Type error checking for incoming frames. When this option is |
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set, the MAC will filter frames that have a mismatched type/length field |
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and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these |
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types of frames are encountered. When this option is cleared, the MAC will |
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allow these types of frames to be received. |
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This option defaults to enabled (set) */ |
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#define XTE_OPTION_LENTYPE_ERR (1 << 7) |
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/* Enable the transmitter. |
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* This option defaults to enabled (set) */ |
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#define XTE_OPTION_TXEN (1 << 11) |
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/* Enable the receiver |
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* This option defaults to enabled (set) */ |
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#define XTE_OPTION_RXEN (1 << 12) |
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/* Default options set when device is initialized or reset */ |
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#define XTE_OPTION_DEFAULTS \ |
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(XTE_OPTION_TXEN | \ |
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XTE_OPTION_FLOW_CONTROL | \ |
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XTE_OPTION_RXEN) |
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/* XPS_LL_TEMAC SDMA registers definition */ |
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#define TX_NXTDESC_PTR 0x00 /* r */ |
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#define TX_CURBUF_ADDR 0x01 /* r */ |
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#define TX_CURBUF_LENGTH 0x02 /* r */ |
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#define TX_CURDESC_PTR 0x03 /* rw */ |
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#define TX_TAILDESC_PTR 0x04 /* rw */ |
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#define TX_CHNL_CTRL 0x05 /* rw */ |
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/* |
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0:7 24:31 IRQTimeout |
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8:15 16:23 IRQCount |
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16:20 11:15 Reserved |
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21 10 0 |
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22 9 UseIntOnEnd |
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23 8 LdIRQCnt |
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24 7 IRQEn |
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25:28 3:6 Reserved |
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29 2 IrqErrEn |
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30 1 IrqDlyEn |
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31 0 IrqCoalEn |
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*/ |
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#define CHNL_CTRL_IRQ_IOE (1 << 9) |
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#define CHNL_CTRL_IRQ_EN (1 << 7) |
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#define CHNL_CTRL_IRQ_ERR_EN (1 << 2) |
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#define CHNL_CTRL_IRQ_DLY_EN (1 << 1) |
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#define CHNL_CTRL_IRQ_COAL_EN (1 << 0) |
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#define TX_IRQ_REG 0x06 /* rw */ |
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/* |
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0:7 24:31 DltTmrValue |
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8:15 16:23 ClscCntrValue |
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16:17 14:15 Reserved |
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18:21 10:13 ClscCnt |
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22:23 8:9 DlyCnt |
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24:28 3::7 Reserved |
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29 2 ErrIrq |
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30 1 DlyIrq |
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31 0 CoalIrq |
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*/ |
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#define TX_CHNL_STS 0x07 /* r */ |
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/* |
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0:9 22:31 Reserved |
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10 21 TailPErr |
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11 20 CmpErr |
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12 19 AddrErr |
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13 18 NxtPErr |
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14 17 CurPErr |
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15 16 BsyWr |
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16:23 8:15 Reserved |
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24 7 Error |
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25 6 IOE |
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26 5 SOE |
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27 4 Cmplt |
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28 3 SOP |
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29 2 EOP |
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30 1 EngBusy |
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31 0 Reserved |
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*/ |
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#define RX_NXTDESC_PTR 0x08 /* r */ |
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#define RX_CURBUF_ADDR 0x09 /* r */ |
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#define RX_CURBUF_LENGTH 0x0a /* r */ |
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#define RX_CURDESC_PTR 0x0b /* rw */ |
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#define RX_TAILDESC_PTR 0x0c /* rw */ |
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#define RX_CHNL_CTRL 0x0d /* rw */ |
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/* |
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0:7 24:31 IRQTimeout |
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8:15 16:23 IRQCount |
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16:20 11:15 Reserved |
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21 10 0 |
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22 9 UseIntOnEnd |
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23 8 LdIRQCnt |
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24 7 IRQEn |
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25:28 3:6 Reserved |
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29 2 IrqErrEn |
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30 1 IrqDlyEn |
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31 0 IrqCoalEn |
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*/ |
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#define RX_IRQ_REG 0x0e /* rw */ |
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#define IRQ_COAL (1 << 0) |
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#define IRQ_DLY (1 << 1) |
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#define IRQ_ERR (1 << 2) |
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#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */ |
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/* |
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0:7 24:31 DltTmrValue |
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8:15 16:23 ClscCntrValue |
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16:17 14:15 Reserved |
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18:21 10:13 ClscCnt |
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22:23 8:9 DlyCnt |
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24:28 3::7 Reserved |
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*/ |
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#define RX_CHNL_STS 0x0f /* r */ |
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#define CHNL_STS_ENGBUSY (1 << 1) |
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#define CHNL_STS_EOP (1 << 2) |
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#define CHNL_STS_SOP (1 << 3) |
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#define CHNL_STS_CMPLT (1 << 4) |
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#define CHNL_STS_SOE (1 << 5) |
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#define CHNL_STS_IOE (1 << 6) |
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#define CHNL_STS_ERR (1 << 7) |
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#define CHNL_STS_BSYWR (1 << 16) |
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#define CHNL_STS_CURPERR (1 << 17) |
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#define CHNL_STS_NXTPERR (1 << 18) |
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#define CHNL_STS_ADDRERR (1 << 19) |
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#define CHNL_STS_CMPERR (1 << 20) |
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#define CHNL_STS_TAILERR (1 << 21) |
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/* |
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0:9 22:31 Reserved |
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10 21 TailPErr |
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11 20 CmpErr |
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12 19 AddrErr |
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13 18 NxtPErr |
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14 17 CurPErr |
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15 16 BsyWr |
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16:23 8:15 Reserved |
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24 7 Error |
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25 6 IOE |
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26 5 SOE |
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27 4 Cmplt |
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28 3 SOP |
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29 2 EOP |
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30 1 EngBusy |
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31 0 Reserved |
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*/ |
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#define DMA_CONTROL_REG 0x10 /* rw */ |
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#define DMA_CONTROL_RST (1 << 0) |
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#define DMA_TAIL_ENABLE (1 << 2) |
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/* XPS_LL_TEMAC direct registers definition */ |
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#define XTE_RAF0_OFFSET 0x00 |
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#define RAF0_RST (1 << 0) |
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#define RAF0_MCSTREJ (1 << 1) |
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#define RAF0_BCSTREJ (1 << 2) |
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#define XTE_TPF0_OFFSET 0x04 |
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#define XTE_IFGP0_OFFSET 0x08 |
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#define XTE_ISR0_OFFSET 0x0c |
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#define ISR0_HARDACSCMPLT (1 << 0) |
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#define ISR0_AUTONEG (1 << 1) |
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#define ISR0_RXCMPLT (1 << 2) |
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#define ISR0_RXREJ (1 << 3) |
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#define ISR0_RXFIFOOVR (1 << 4) |
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#define ISR0_TXCMPLT (1 << 5) |
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#define ISR0_RXDCMLCK (1 << 6) |
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#define XTE_IPR0_OFFSET 0x10 |
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#define XTE_IER0_OFFSET 0x14 |
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#define XTE_MSW0_OFFSET 0x20 |
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#define XTE_LSW0_OFFSET 0x24 |
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#define XTE_CTL0_OFFSET 0x28 |
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#define XTE_RDY0_OFFSET 0x2c |
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#define XTE_RSE_MIIM_RR_MASK 0x0002 |
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#define XTE_RSE_MIIM_WR_MASK 0x0004 |
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#define XTE_RSE_CFG_RR_MASK 0x0020 |
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#define XTE_RSE_CFG_WR_MASK 0x0040 |
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#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000) |
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/* XPS_LL_TEMAC indirect registers offset definition */ |
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#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */ |
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#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */ |
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#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */ |
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#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */ |
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#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */ |
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#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */ |
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#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */ |
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#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */ |
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#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */ |
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#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */ |
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#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */ |
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#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */ |
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#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */ |
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#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */ |
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#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */ |
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#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */ |
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#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */ |
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#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */ |
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#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */ |
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#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */ |
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#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */ |
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#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */ |
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#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */ |
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#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */ |
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#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */ |
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#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */ |
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#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */ |
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#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */ |
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#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */ |
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#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */ |
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#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */ |
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#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */ |
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#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */ |
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/* Interrupt Request status */ |
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#define XTE_TIS_OFFSET 0x000003A0 |
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#define TIS_FRIS (1 << 0) |
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#define TIS_MRIS (1 << 1) |
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#define TIS_MWIS (1 << 2) |
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#define TIS_ARIS (1 << 3) |
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#define TIS_AWIS (1 << 4) |
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#define TIS_CRIS (1 << 5) |
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#define TIS_CWIS (1 << 6) |
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#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */ |
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/** MII Mamagement Control register (MGTCR) */ |
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#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */ |
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#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */ |
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#define CNTLREG_WRITE_ENABLE_MASK 0x8000 |
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#define CNTLREG_EMAC1SEL_MASK 0x0400 |
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#define CNTLREG_ADDRESSCODE_MASK 0x03ff |
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/* CDMAC descriptor status bit definitions */ |
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#define STS_CTRL_APP0_ERR (1 << 31) |
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#define STS_CTRL_APP0_IRQONEND (1 << 30) |
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/* undoccumented */ |
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#define STS_CTRL_APP0_STOPONEND (1 << 29) |
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#define STS_CTRL_APP0_CMPLT (1 << 28) |
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#define STS_CTRL_APP0_SOP (1 << 27) |
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#define STS_CTRL_APP0_EOP (1 << 26) |
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#define STS_CTRL_APP0_ENGBUSY (1 << 25) |
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/* undocumented */ |
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#define STS_CTRL_APP0_ENGRST (1 << 24) |
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#define TX_CONTROL_CALC_CSUM_MASK 1 |
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#define MULTICAST_CAM_TABLE_NUM 4 |
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/* TEMAC Synthesis features */ |
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#define TEMAC_FEATURE_RX_CSUM (1 << 0) |
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#define TEMAC_FEATURE_TX_CSUM (1 << 1) |
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/* TX/RX CURDESC_PTR points to first descriptor */ |
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/* TX/RX TAILDESC_PTR points to last descriptor in linked list */ |
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/** |
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* struct cdmac_bd - LocalLink buffer descriptor format |
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* |
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* app0 bits: |
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* 0 Error |
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* 1 IrqOnEnd generate an interrupt at completion of DMA op |
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* 2 reserved |
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* 3 completed Current descriptor completed |
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* 4 SOP TX - marks first desc/ RX marks first desct |
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* 5 EOP TX marks last desc/RX marks last desc |
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* 6 EngBusy DMA is processing |
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* 7 reserved |
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* 8:31 application specific |
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*/ |
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struct cdmac_bd { |
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u32 next; /* Physical address of next buffer descriptor */ |
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u32 phys; |
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u32 len; |
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u32 app0; |
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u32 app1; /* TX start << 16 | insert */ |
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u32 app2; /* TX csum */ |
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u32 app3; |
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u32 app4; /* skb for TX length for RX */ |
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}; |
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struct temac_local { |
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struct net_device *ndev; |
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struct device *dev; |
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/* Connection to PHY device */ |
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struct device_node *phy_node; |
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/* For non-device-tree devices */ |
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char phy_name[MII_BUS_ID_SIZE + 3]; |
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phy_interface_t phy_interface; |
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/* MDIO bus data */ |
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struct mii_bus *mii_bus; /* MII bus reference */ |
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/* IO registers, dma functions and IRQs */ |
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void __iomem *regs; |
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void __iomem *sdma_regs; |
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#ifdef CONFIG_PPC_DCR |
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dcr_host_t sdma_dcrs; |
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#endif |
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u32 (*temac_ior)(struct temac_local *lp, int offset); |
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void (*temac_iow)(struct temac_local *lp, int offset, u32 value); |
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u32 (*dma_in)(struct temac_local *lp, int reg); |
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void (*dma_out)(struct temac_local *lp, int reg, u32 value); |
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int tx_irq; |
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int rx_irq; |
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int emac_num; |
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struct sk_buff **rx_skb; |
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spinlock_t rx_lock; |
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/* For synchronization of indirect register access. Must be |
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* shared mutex between interfaces in same TEMAC block. |
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*/ |
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spinlock_t *indirect_lock; |
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u32 options; /* Current options word */ |
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int last_link; |
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unsigned int temac_features; |
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/* Buffer descriptors */ |
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struct cdmac_bd *tx_bd_v; |
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dma_addr_t tx_bd_p; |
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u32 tx_bd_num; |
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struct cdmac_bd *rx_bd_v; |
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dma_addr_t rx_bd_p; |
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u32 rx_bd_num; |
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int tx_bd_ci; |
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int tx_bd_tail; |
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int rx_bd_ci; |
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int rx_bd_tail; |
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/* DMA channel control setup */ |
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u8 coalesce_count_tx; |
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u8 coalesce_delay_tx; |
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u8 coalesce_count_rx; |
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u8 coalesce_delay_rx; |
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struct delayed_work restart_work; |
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}; |
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/* Wrappers for temac_ior()/temac_iow() function pointers above */ |
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#define temac_ior(lp, o) ((lp)->temac_ior(lp, o)) |
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#define temac_iow(lp, o, v) ((lp)->temac_iow(lp, o, v)) |
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/* xilinx_temac.c */ |
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int temac_indirect_busywait(struct temac_local *lp); |
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u32 temac_indirect_in32(struct temac_local *lp, int reg); |
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u32 temac_indirect_in32_locked(struct temac_local *lp, int reg); |
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void temac_indirect_out32(struct temac_local *lp, int reg, u32 value); |
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void temac_indirect_out32_locked(struct temac_local *lp, int reg, u32 value); |
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/* xilinx_temac_mdio.c */ |
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int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev); |
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void temac_mdio_teardown(struct temac_local *lp); |
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#endif /* XILINX_LL_TEMAC_H */
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