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750 lines
19 KiB
750 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Texas Instruments Ethernet Switch Driver ethtool intf |
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* |
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* Copyright (C) 2019 Texas Instruments |
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*/ |
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#include <linux/if_ether.h> |
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#include <linux/if_vlan.h> |
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#include <linux/kmemleak.h> |
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#include <linux/module.h> |
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#include <linux/netdevice.h> |
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#include <linux/net_tstamp.h> |
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#include <linux/phy.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/skbuff.h> |
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#include "cpsw.h" |
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#include "cpts.h" |
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#include "cpsw_ale.h" |
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#include "cpsw_priv.h" |
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#include "davinci_cpdma.h" |
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struct cpsw_hw_stats { |
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u32 rxgoodframes; |
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u32 rxbroadcastframes; |
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u32 rxmulticastframes; |
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u32 rxpauseframes; |
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u32 rxcrcerrors; |
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u32 rxaligncodeerrors; |
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u32 rxoversizedframes; |
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u32 rxjabberframes; |
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u32 rxundersizedframes; |
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u32 rxfragments; |
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u32 __pad_0[2]; |
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u32 rxoctets; |
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u32 txgoodframes; |
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u32 txbroadcastframes; |
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u32 txmulticastframes; |
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u32 txpauseframes; |
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u32 txdeferredframes; |
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u32 txcollisionframes; |
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u32 txsinglecollframes; |
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u32 txmultcollframes; |
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u32 txexcessivecollisions; |
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u32 txlatecollisions; |
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u32 txunderrun; |
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u32 txcarriersenseerrors; |
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u32 txoctets; |
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u32 octetframes64; |
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u32 octetframes65t127; |
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u32 octetframes128t255; |
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u32 octetframes256t511; |
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u32 octetframes512t1023; |
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u32 octetframes1024tup; |
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u32 netoctets; |
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u32 rxsofoverruns; |
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u32 rxmofoverruns; |
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u32 rxdmaoverruns; |
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}; |
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struct cpsw_stats { |
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char stat_string[ETH_GSTRING_LEN]; |
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int type; |
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int sizeof_stat; |
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int stat_offset; |
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}; |
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enum { |
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CPSW_STATS, |
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CPDMA_RX_STATS, |
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CPDMA_TX_STATS, |
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}; |
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#define CPSW_STAT(m) CPSW_STATS, \ |
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sizeof_field(struct cpsw_hw_stats, m), \ |
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offsetof(struct cpsw_hw_stats, m) |
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#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ |
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sizeof_field(struct cpdma_chan_stats, m), \ |
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offsetof(struct cpdma_chan_stats, m) |
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#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ |
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sizeof_field(struct cpdma_chan_stats, m), \ |
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offsetof(struct cpdma_chan_stats, m) |
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static const struct cpsw_stats cpsw_gstrings_stats[] = { |
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{ "Good Rx Frames", CPSW_STAT(rxgoodframes) }, |
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{ "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, |
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{ "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, |
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{ "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, |
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{ "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, |
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{ "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, |
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{ "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, |
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{ "Rx Jabbers", CPSW_STAT(rxjabberframes) }, |
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{ "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, |
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{ "Rx Fragments", CPSW_STAT(rxfragments) }, |
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{ "Rx Octets", CPSW_STAT(rxoctets) }, |
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{ "Good Tx Frames", CPSW_STAT(txgoodframes) }, |
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{ "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, |
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{ "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, |
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{ "Pause Tx Frames", CPSW_STAT(txpauseframes) }, |
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{ "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, |
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{ "Collisions", CPSW_STAT(txcollisionframes) }, |
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{ "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, |
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{ "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, |
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{ "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, |
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{ "Late Collisions", CPSW_STAT(txlatecollisions) }, |
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{ "Tx Underrun", CPSW_STAT(txunderrun) }, |
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{ "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, |
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{ "Tx Octets", CPSW_STAT(txoctets) }, |
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{ "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, |
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{ "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, |
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{ "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, |
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{ "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, |
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{ "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, |
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{ "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, |
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{ "Net Octets", CPSW_STAT(netoctets) }, |
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{ "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, |
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{ "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, |
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{ "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, |
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}; |
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static const struct cpsw_stats cpsw_gstrings_ch_stats[] = { |
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{ "head_enqueue", CPDMA_RX_STAT(head_enqueue) }, |
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{ "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, |
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{ "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, |
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{ "misqueued", CPDMA_RX_STAT(misqueued) }, |
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{ "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, |
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{ "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, |
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{ "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, |
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{ "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, |
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{ "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, |
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{ "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, |
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{ "good_dequeue", CPDMA_RX_STAT(good_dequeue) }, |
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{ "requeue", CPDMA_RX_STAT(requeue) }, |
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{ "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, |
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}; |
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#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats) |
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#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats) |
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u32 cpsw_get_msglevel(struct net_device *ndev) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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return priv->msg_enable; |
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} |
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void cpsw_set_msglevel(struct net_device *ndev, u32 value) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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priv->msg_enable = value; |
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} |
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int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, |
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struct kernel_ethtool_coalesce *kernel_coal, |
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struct netlink_ext_ack *extack) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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coal->rx_coalesce_usecs = cpsw->coal_intvl; |
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return 0; |
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} |
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int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal, |
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struct kernel_ethtool_coalesce *kernel_coal, |
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struct netlink_ext_ack *extack) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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u32 int_ctrl; |
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u32 num_interrupts = 0; |
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u32 prescale = 0; |
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u32 addnl_dvdr = 1; |
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u32 coal_intvl = 0; |
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struct cpsw_common *cpsw = priv->cpsw; |
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coal_intvl = coal->rx_coalesce_usecs; |
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int_ctrl = readl(&cpsw->wr_regs->int_control); |
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prescale = cpsw->bus_freq_mhz * 4; |
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if (!coal->rx_coalesce_usecs) { |
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int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN); |
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goto update_return; |
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} |
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if (coal_intvl < CPSW_CMINTMIN_INTVL) |
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coal_intvl = CPSW_CMINTMIN_INTVL; |
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if (coal_intvl > CPSW_CMINTMAX_INTVL) { |
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/* Interrupt pacer works with 4us Pulse, we can |
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* throttle further by dilating the 4us pulse. |
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*/ |
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addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; |
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if (addnl_dvdr > 1) { |
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prescale *= addnl_dvdr; |
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if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) |
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coal_intvl = (CPSW_CMINTMAX_INTVL |
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* addnl_dvdr); |
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} else { |
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addnl_dvdr = 1; |
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coal_intvl = CPSW_CMINTMAX_INTVL; |
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} |
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} |
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num_interrupts = (1000 * addnl_dvdr) / coal_intvl; |
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writel(num_interrupts, &cpsw->wr_regs->rx_imax); |
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writel(num_interrupts, &cpsw->wr_regs->tx_imax); |
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int_ctrl |= CPSW_INTPACEEN; |
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int_ctrl &= (~CPSW_INTPRESCALE_MASK); |
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int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); |
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update_return: |
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writel(int_ctrl, &cpsw->wr_regs->int_control); |
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cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); |
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cpsw->coal_intvl = coal_intvl; |
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return 0; |
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} |
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int cpsw_get_sset_count(struct net_device *ndev, int sset) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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switch (sset) { |
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case ETH_SS_STATS: |
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return (CPSW_STATS_COMMON_LEN + |
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(cpsw->rx_ch_num + cpsw->tx_ch_num) * |
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CPSW_STATS_CH_LEN); |
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default: |
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return -EOPNOTSUPP; |
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} |
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} |
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static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir) |
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{ |
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int ch_stats_len; |
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int line; |
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int i; |
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ch_stats_len = CPSW_STATS_CH_LEN * ch_num; |
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for (i = 0; i < ch_stats_len; i++) { |
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line = i % CPSW_STATS_CH_LEN; |
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snprintf(*p, ETH_GSTRING_LEN, |
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"%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx", |
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(long)(i / CPSW_STATS_CH_LEN), |
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cpsw_gstrings_ch_stats[line].stat_string); |
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*p += ETH_GSTRING_LEN; |
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} |
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} |
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void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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u8 *p = data; |
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int i; |
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switch (stringset) { |
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case ETH_SS_STATS: |
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for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) { |
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memcpy(p, cpsw_gstrings_stats[i].stat_string, |
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ETH_GSTRING_LEN); |
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p += ETH_GSTRING_LEN; |
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} |
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cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1); |
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cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0); |
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break; |
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} |
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} |
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void cpsw_get_ethtool_stats(struct net_device *ndev, |
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struct ethtool_stats *stats, u64 *data) |
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{ |
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u8 *p; |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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struct cpdma_chan_stats ch_stats; |
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int i, l, ch; |
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/* Collect Davinci CPDMA stats for Rx and Tx Channel */ |
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for (l = 0; l < CPSW_STATS_COMMON_LEN; l++) |
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data[l] = readl(cpsw->hw_stats + |
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cpsw_gstrings_stats[l].stat_offset); |
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for (ch = 0; ch < cpsw->rx_ch_num; ch++) { |
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cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats); |
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for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { |
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p = (u8 *)&ch_stats + |
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cpsw_gstrings_ch_stats[i].stat_offset; |
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data[l] = *(u32 *)p; |
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} |
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} |
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for (ch = 0; ch < cpsw->tx_ch_num; ch++) { |
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cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats); |
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for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) { |
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p = (u8 *)&ch_stats + |
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cpsw_gstrings_ch_stats[i].stat_offset; |
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data[l] = *(u32 *)p; |
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} |
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} |
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} |
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void cpsw_get_pauseparam(struct net_device *ndev, |
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struct ethtool_pauseparam *pause) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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pause->autoneg = AUTONEG_DISABLE; |
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pause->rx_pause = priv->rx_pause ? true : false; |
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pause->tx_pause = priv->tx_pause ? true : false; |
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} |
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void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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wol->supported = 0; |
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wol->wolopts = 0; |
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if (cpsw->slaves[slave_no].phy) |
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phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol); |
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} |
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int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (cpsw->slaves[slave_no].phy) |
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return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol); |
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else |
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return -EOPNOTSUPP; |
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} |
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int cpsw_get_regs_len(struct net_device *ndev) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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return cpsw_ale_get_num_entries(cpsw->ale) * |
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ALE_ENTRY_WORDS * sizeof(u32); |
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} |
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void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p) |
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{ |
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u32 *reg = p; |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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/* update CPSW IP version */ |
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regs->version = cpsw->version; |
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cpsw_ale_dump(cpsw->ale, reg); |
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} |
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int cpsw_ethtool_op_begin(struct net_device *ndev) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int ret; |
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ret = pm_runtime_get_sync(cpsw->dev); |
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if (ret < 0) { |
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cpsw_err(priv, drv, "ethtool begin failed %d\n", ret); |
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pm_runtime_put_noidle(cpsw->dev); |
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} |
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return ret; |
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} |
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void cpsw_ethtool_op_complete(struct net_device *ndev) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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int ret; |
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ret = pm_runtime_put(priv->cpsw->dev); |
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if (ret < 0) |
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cpsw_err(priv, drv, "ethtool complete failed %d\n", ret); |
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} |
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void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; |
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ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES; |
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ch->max_combined = 0; |
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ch->max_other = 0; |
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ch->other_count = 0; |
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ch->rx_count = cpsw->rx_ch_num; |
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ch->tx_count = cpsw->tx_ch_num; |
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ch->combined_count = 0; |
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} |
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int cpsw_get_link_ksettings(struct net_device *ndev, |
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struct ethtool_link_ksettings *ecmd) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (!cpsw->slaves[slave_no].phy) |
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return -EOPNOTSUPP; |
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phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd); |
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return 0; |
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} |
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int cpsw_set_link_ksettings(struct net_device *ndev, |
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const struct ethtool_link_ksettings *ecmd) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (!cpsw->slaves[slave_no].phy) |
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return -EOPNOTSUPP; |
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return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, ecmd); |
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} |
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int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (cpsw->slaves[slave_no].phy) |
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return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata); |
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else |
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return -EOPNOTSUPP; |
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} |
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int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (cpsw->slaves[slave_no].phy) |
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return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata); |
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else |
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return -EOPNOTSUPP; |
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} |
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int cpsw_nway_reset(struct net_device *ndev) |
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{ |
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struct cpsw_priv *priv = netdev_priv(ndev); |
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struct cpsw_common *cpsw = priv->cpsw; |
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int slave_no = cpsw_slave_index(cpsw, priv); |
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if (cpsw->slaves[slave_no].phy) |
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return genphy_restart_aneg(cpsw->slaves[slave_no].phy); |
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else |
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return -EOPNOTSUPP; |
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} |
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static void cpsw_suspend_data_pass(struct net_device *ndev) |
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{ |
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struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
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int i; |
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/* Disable NAPI scheduling */ |
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cpsw_intr_disable(cpsw); |
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/* Stop all transmit queues for every network device. |
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*/ |
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for (i = 0; i < cpsw->data.slaves; i++) { |
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ndev = cpsw->slaves[i].ndev; |
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if (!(ndev && netif_running(ndev))) |
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continue; |
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netif_tx_stop_all_queues(ndev); |
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/* Barrier, so that stop_queue visible to other cpus */ |
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smp_mb__after_atomic(); |
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} |
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|
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/* Handle rest of tx packets and stop cpdma channels */ |
|
cpdma_ctlr_stop(cpsw->dma); |
|
} |
|
|
|
static int cpsw_resume_data_pass(struct net_device *ndev) |
|
{ |
|
struct cpsw_priv *priv = netdev_priv(ndev); |
|
struct cpsw_common *cpsw = priv->cpsw; |
|
int i, ret; |
|
|
|
/* After this receive is started */ |
|
if (cpsw->usage_count) { |
|
ret = cpsw_fill_rx_channels(priv); |
|
if (ret) |
|
return ret; |
|
|
|
cpdma_ctlr_start(cpsw->dma); |
|
cpsw_intr_enable(cpsw); |
|
} |
|
|
|
/* Resume transmit for every affected interface */ |
|
for (i = 0; i < cpsw->data.slaves; i++) { |
|
ndev = cpsw->slaves[i].ndev; |
|
if (ndev && netif_running(ndev)) |
|
netif_tx_start_all_queues(ndev); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int cpsw_check_ch_settings(struct cpsw_common *cpsw, |
|
struct ethtool_channels *ch) |
|
{ |
|
if (cpsw->quirk_irq) { |
|
dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed"); |
|
return -EOPNOTSUPP; |
|
} |
|
|
|
if (ch->combined_count) |
|
return -EINVAL; |
|
|
|
/* verify we have at least one channel in each direction */ |
|
if (!ch->rx_count || !ch->tx_count) |
|
return -EINVAL; |
|
|
|
if (ch->rx_count > cpsw->data.channels || |
|
ch->tx_count > cpsw->data.channels) |
|
return -EINVAL; |
|
|
|
return 0; |
|
} |
|
|
|
static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx, |
|
cpdma_handler_fn rx_handler) |
|
{ |
|
struct cpsw_common *cpsw = priv->cpsw; |
|
void (*handler)(void *, int, int); |
|
struct netdev_queue *queue; |
|
struct cpsw_vector *vec; |
|
int ret, *ch, vch; |
|
|
|
if (rx) { |
|
ch = &cpsw->rx_ch_num; |
|
vec = cpsw->rxv; |
|
handler = rx_handler; |
|
} else { |
|
ch = &cpsw->tx_ch_num; |
|
vec = cpsw->txv; |
|
handler = cpsw_tx_handler; |
|
} |
|
|
|
while (*ch < ch_num) { |
|
vch = rx ? *ch : 7 - *ch; |
|
vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx); |
|
queue = netdev_get_tx_queue(priv->ndev, *ch); |
|
queue->tx_maxrate = 0; |
|
|
|
if (IS_ERR(vec[*ch].ch)) |
|
return PTR_ERR(vec[*ch].ch); |
|
|
|
if (!vec[*ch].ch) |
|
return -EINVAL; |
|
|
|
cpsw_info(priv, ifup, "created new %d %s channel\n", *ch, |
|
(rx ? "rx" : "tx")); |
|
(*ch)++; |
|
} |
|
|
|
while (*ch > ch_num) { |
|
(*ch)--; |
|
|
|
ret = cpdma_chan_destroy(vec[*ch].ch); |
|
if (ret) |
|
return ret; |
|
|
|
cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch, |
|
(rx ? "rx" : "tx")); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void cpsw_fail(struct cpsw_common *cpsw) |
|
{ |
|
struct net_device *ndev; |
|
int i; |
|
|
|
for (i = 0; i < cpsw->data.slaves; i++) { |
|
ndev = cpsw->slaves[i].ndev; |
|
if (ndev) |
|
dev_close(ndev); |
|
} |
|
} |
|
|
|
int cpsw_set_channels_common(struct net_device *ndev, |
|
struct ethtool_channels *chs, |
|
cpdma_handler_fn rx_handler) |
|
{ |
|
struct cpsw_priv *priv = netdev_priv(ndev); |
|
struct cpsw_common *cpsw = priv->cpsw; |
|
struct net_device *sl_ndev; |
|
int i, new_pools, ret; |
|
|
|
ret = cpsw_check_ch_settings(cpsw, chs); |
|
if (ret < 0) |
|
return ret; |
|
|
|
cpsw_suspend_data_pass(ndev); |
|
|
|
new_pools = (chs->rx_count != cpsw->rx_ch_num) && cpsw->usage_count; |
|
|
|
ret = cpsw_update_channels_res(priv, chs->rx_count, 1, rx_handler); |
|
if (ret) |
|
goto err; |
|
|
|
ret = cpsw_update_channels_res(priv, chs->tx_count, 0, rx_handler); |
|
if (ret) |
|
goto err; |
|
|
|
for (i = 0; i < cpsw->data.slaves; i++) { |
|
sl_ndev = cpsw->slaves[i].ndev; |
|
if (!(sl_ndev && netif_running(sl_ndev))) |
|
continue; |
|
|
|
/* Inform stack about new count of queues */ |
|
ret = netif_set_real_num_tx_queues(sl_ndev, cpsw->tx_ch_num); |
|
if (ret) { |
|
dev_err(priv->dev, "cannot set real number of tx queues\n"); |
|
goto err; |
|
} |
|
|
|
ret = netif_set_real_num_rx_queues(sl_ndev, cpsw->rx_ch_num); |
|
if (ret) { |
|
dev_err(priv->dev, "cannot set real number of rx queues\n"); |
|
goto err; |
|
} |
|
} |
|
|
|
cpsw_split_res(cpsw); |
|
|
|
if (new_pools) { |
|
cpsw_destroy_xdp_rxqs(cpsw); |
|
ret = cpsw_create_xdp_rxqs(cpsw); |
|
if (ret) |
|
goto err; |
|
} |
|
|
|
ret = cpsw_resume_data_pass(ndev); |
|
if (!ret) |
|
return 0; |
|
err: |
|
dev_err(priv->dev, "cannot update channels number, closing device\n"); |
|
cpsw_fail(cpsw); |
|
return ret; |
|
} |
|
|
|
void cpsw_get_ringparam(struct net_device *ndev, |
|
struct ethtool_ringparam *ering) |
|
{ |
|
struct cpsw_priv *priv = netdev_priv(ndev); |
|
struct cpsw_common *cpsw = priv->cpsw; |
|
|
|
/* not supported */ |
|
ering->tx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES; |
|
ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma); |
|
ering->rx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES; |
|
ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma); |
|
} |
|
|
|
int cpsw_set_ringparam(struct net_device *ndev, |
|
struct ethtool_ringparam *ering) |
|
{ |
|
struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
|
int descs_num, ret; |
|
|
|
/* ignore ering->tx_pending - only rx_pending adjustment is supported */ |
|
|
|
if (ering->rx_mini_pending || ering->rx_jumbo_pending || |
|
ering->rx_pending < CPSW_MAX_QUEUES || |
|
ering->rx_pending > (cpsw->descs_pool_size - CPSW_MAX_QUEUES)) |
|
return -EINVAL; |
|
|
|
descs_num = cpdma_get_num_rx_descs(cpsw->dma); |
|
if (ering->rx_pending == descs_num) |
|
return 0; |
|
|
|
cpsw_suspend_data_pass(ndev); |
|
|
|
ret = cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending); |
|
if (ret) { |
|
if (cpsw_resume_data_pass(ndev)) |
|
goto err; |
|
|
|
return ret; |
|
} |
|
|
|
if (cpsw->usage_count) { |
|
cpsw_destroy_xdp_rxqs(cpsw); |
|
ret = cpsw_create_xdp_rxqs(cpsw); |
|
if (ret) |
|
goto err; |
|
} |
|
|
|
ret = cpsw_resume_data_pass(ndev); |
|
if (!ret) |
|
return 0; |
|
err: |
|
cpdma_set_num_rx_descs(cpsw->dma, descs_num); |
|
dev_err(cpsw->dev, "cannot set ring params, closing device\n"); |
|
cpsw_fail(cpsw); |
|
return ret; |
|
} |
|
|
|
#if IS_ENABLED(CONFIG_TI_CPTS) |
|
int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) |
|
{ |
|
struct cpsw_common *cpsw = ndev_to_cpsw(ndev); |
|
|
|
info->so_timestamping = |
|
SOF_TIMESTAMPING_TX_HARDWARE | |
|
SOF_TIMESTAMPING_TX_SOFTWARE | |
|
SOF_TIMESTAMPING_RX_HARDWARE | |
|
SOF_TIMESTAMPING_RX_SOFTWARE | |
|
SOF_TIMESTAMPING_SOFTWARE | |
|
SOF_TIMESTAMPING_RAW_HARDWARE; |
|
info->phc_index = cpsw->cpts->phc_index; |
|
info->tx_types = |
|
(1 << HWTSTAMP_TX_OFF) | |
|
(1 << HWTSTAMP_TX_ON); |
|
info->rx_filters = |
|
(1 << HWTSTAMP_FILTER_NONE) | |
|
(1 << HWTSTAMP_FILTER_PTP_V2_EVENT); |
|
return 0; |
|
} |
|
#else |
|
int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info) |
|
{ |
|
info->so_timestamping = |
|
SOF_TIMESTAMPING_TX_SOFTWARE | |
|
SOF_TIMESTAMPING_RX_SOFTWARE | |
|
SOF_TIMESTAMPING_SOFTWARE; |
|
info->phc_index = -1; |
|
info->tx_types = 0; |
|
info->rx_filters = 0; |
|
return 0; |
|
} |
|
#endif
|
|
|