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599 lines
11 KiB
599 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Huawei HiNIC PCI Express Linux driver |
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* Copyright(c) 2017 Huawei Technologies Co., Ltd |
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*/ |
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#ifndef HINIC_HW_DEV_H |
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#define HINIC_HW_DEV_H |
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#include <linux/pci.h> |
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#include <linux/types.h> |
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#include <linux/bitops.h> |
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#include <net/devlink.h> |
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#include "hinic_hw_if.h" |
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#include "hinic_hw_eqs.h" |
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#include "hinic_hw_mgmt.h" |
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#include "hinic_hw_qp.h" |
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#include "hinic_hw_io.h" |
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#include "hinic_hw_mbox.h" |
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#define HINIC_MAX_QPS 32 |
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#define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ |
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HINIC_MGMT_MSG_CMD_BASE) |
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#define HINIC_PF_SET_VF_ALREADY 0x4 |
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#define HINIC_MGMT_STATUS_EXIST 0x6 |
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#define HINIC_MGMT_CMD_UNSUPPORTED 0xFF |
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#define HINIC_CMD_VER_FUNC_ID 2 |
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struct hinic_cap { |
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u16 max_qps; |
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u16 num_qps; |
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u8 max_vf; |
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u16 max_vf_qps; |
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}; |
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enum hw_ioctxt_set_cmdq_depth { |
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HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, |
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HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, |
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}; |
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enum hinic_port_cmd { |
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HINIC_PORT_CMD_VF_REGISTER = 0x0, |
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HINIC_PORT_CMD_VF_UNREGISTER = 0x1, |
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HINIC_PORT_CMD_CHANGE_MTU = 2, |
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HINIC_PORT_CMD_ADD_VLAN = 3, |
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HINIC_PORT_CMD_DEL_VLAN = 4, |
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HINIC_PORT_CMD_SET_PFC = 5, |
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HINIC_PORT_CMD_SET_MAC = 9, |
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HINIC_PORT_CMD_GET_MAC = 10, |
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HINIC_PORT_CMD_DEL_MAC = 11, |
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HINIC_PORT_CMD_SET_RX_MODE = 12, |
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HINIC_PORT_CMD_GET_PAUSE_INFO = 20, |
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HINIC_PORT_CMD_SET_PAUSE_INFO = 21, |
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HINIC_PORT_CMD_GET_LINK_STATE = 24, |
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HINIC_PORT_CMD_SET_LRO = 25, |
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HINIC_PORT_CMD_SET_RX_CSUM = 26, |
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HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, |
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HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, |
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HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, |
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HINIC_PORT_CMD_GET_VPORT_STAT = 30, |
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HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, |
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HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, |
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HINIC_PORT_CMD_SET_PORT_STATE = 41, |
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HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, |
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HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, |
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HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, |
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HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, |
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HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, |
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HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, |
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HINIC_PORT_CMD_RSS_TEMP_MGR = 49, |
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HINIC_PORT_CMD_RD_LINE_TBL = 57, |
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HINIC_PORT_CMD_RSS_CFG = 66, |
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HINIC_PORT_CMD_FWCTXT_INIT = 69, |
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HINIC_PORT_CMD_GET_LOOPBACK_MODE = 72, |
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HINIC_PORT_CMD_SET_LOOPBACK_MODE, |
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HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, |
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HINIC_PORT_CMD_GET_MGMT_VERSION = 88, |
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HINIC_PORT_CMD_SET_FUNC_STATE = 93, |
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HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, |
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HINIC_PORT_CMD_SET_VF_RATE = 105, |
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HINIC_PORT_CMD_SET_VF_VLAN = 106, |
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HINIC_PORT_CMD_CLR_VF_VLAN, |
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HINIC_PORT_CMD_SET_TSO = 112, |
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HINIC_PORT_CMD_UPDATE_FW = 114, |
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HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, |
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HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, |
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HINIC_PORT_CMD_UPDATE_MAC = 164, |
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HINIC_PORT_CMD_GET_CAP = 170, |
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HINIC_PORT_CMD_GET_LINK_MODE = 217, |
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HINIC_PORT_CMD_SET_SPEED = 218, |
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HINIC_PORT_CMD_SET_AUTONEG = 219, |
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HINIC_PORT_CMD_GET_STD_SFP_INFO = 240, |
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HINIC_PORT_CMD_SET_LRO_TIMER = 244, |
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HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, |
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HINIC_PORT_CMD_GET_SFP_ABS = 251, |
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}; |
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/* cmd of mgmt CPU message for HILINK module */ |
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enum hinic_hilink_cmd { |
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HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, |
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HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, |
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}; |
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enum hinic_ucode_cmd { |
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HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, |
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HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, |
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HINIC_UCODE_CMD_ARM_SQ, |
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HINIC_UCODE_CMD_ARM_RQ, |
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HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, |
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HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, |
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HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, |
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HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, |
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HINIC_UCODE_CMD_SET_IQ_ENABLE, |
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HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 |
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}; |
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#define NIC_RSS_CMD_TEMP_ALLOC 0x01 |
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#define NIC_RSS_CMD_TEMP_FREE 0x02 |
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enum hinic_mgmt_msg_cmd { |
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HINIC_MGMT_MSG_CMD_BASE = 0xA0, |
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HINIC_MGMT_MSG_CMD_LINK_STATUS = 0xA0, |
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HINIC_MGMT_MSG_CMD_CABLE_PLUG_EVENT = 0xE5, |
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HINIC_MGMT_MSG_CMD_LINK_ERR_EVENT = 0xE6, |
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HINIC_MGMT_MSG_CMD_MAX, |
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}; |
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enum hinic_cb_state { |
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HINIC_CB_ENABLED = BIT(0), |
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HINIC_CB_RUNNING = BIT(1), |
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}; |
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enum hinic_res_state { |
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HINIC_RES_CLEAN = 0, |
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HINIC_RES_ACTIVE = 1, |
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}; |
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struct hinic_cmd_fw_ctxt { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u16 rx_buf_sz; |
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u32 rsvd1; |
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}; |
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struct hinic_cmd_hw_ioctxt { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u16 rsvd1; |
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u8 set_cmdq_depth; |
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u8 cmdq_depth; |
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u8 lro_en; |
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u8 rsvd3; |
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u8 ppf_idx; |
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u8 rsvd4; |
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u16 rq_depth; |
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u16 rx_buf_sz_idx; |
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u16 sq_depth; |
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}; |
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struct hinic_cmd_io_status { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u8 rsvd1; |
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u8 rsvd2; |
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u32 io_status; |
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}; |
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struct hinic_cmd_clear_io_res { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u8 rsvd1; |
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u8 rsvd2; |
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}; |
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struct hinic_cmd_set_res_state { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u8 state; |
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u8 rsvd1; |
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u32 rsvd2; |
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}; |
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struct hinic_ceq_ctrl_reg { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_id; |
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u16 q_id; |
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u32 ctrl0; |
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u32 ctrl1; |
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}; |
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struct hinic_cmd_base_qpn { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u16 qpn; |
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}; |
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struct hinic_cmd_hw_ci { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_idx; |
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u8 dma_attr_off; |
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u8 pending_limit; |
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u8 coalesc_timer; |
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u8 msix_en; |
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u16 msix_entry_idx; |
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u32 sq_id; |
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u32 rsvd1; |
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u64 ci_addr; |
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}; |
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struct hinic_cmd_l2nic_reset { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_id; |
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u16 reset_flag; |
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}; |
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struct hinic_msix_config { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u16 func_id; |
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u16 msix_index; |
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u8 pending_cnt; |
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u8 coalesce_timer_cnt; |
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u8 lli_timer_cnt; |
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u8 lli_credit_cnt; |
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u8 resend_timer_cnt; |
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u8 rsvd1[3]; |
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}; |
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struct hinic_set_random_id { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u8 vf_in_pf; |
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u8 rsvd1; |
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u16 func_idx; |
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u32 random_id; |
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}; |
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struct hinic_board_info { |
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u32 board_type; |
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u32 port_num; |
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u32 port_speed; |
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u32 pcie_width; |
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u32 host_num; |
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u32 pf_num; |
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u32 vf_total_num; |
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u32 tile_num; |
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u32 qcm_num; |
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u32 core_num; |
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u32 work_mode; |
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u32 service_mode; |
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u32 pcie_mode; |
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u32 cfg_addr; |
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u32 boot_sel; |
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u32 board_id; |
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}; |
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struct hinic_comm_board_info { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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struct hinic_board_info info; |
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u32 rsvd1[4]; |
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}; |
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struct hinic_hwdev { |
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struct hinic_hwif *hwif; |
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struct msix_entry *msix_entries; |
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struct hinic_aeqs aeqs; |
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struct hinic_func_to_io func_to_io; |
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struct hinic_mbox_func_to_func *func_to_func; |
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struct hinic_cap nic_cap; |
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u8 port_id; |
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struct hinic_devlink_priv *devlink_dev; |
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}; |
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struct hinic_nic_cb { |
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void (*handler)(void *handle, void *buf_in, |
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u16 in_size, void *buf_out, |
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u16 *out_size); |
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void *handle; |
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unsigned long cb_state; |
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}; |
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#define HINIC_COMM_SELF_CMD_MAX 4 |
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typedef void (*comm_mgmt_self_msg_proc)(void *handle, void *buf_in, u16 in_size, |
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void *buf_out, u16 *out_size); |
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struct comm_mgmt_self_msg_sub_info { |
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u8 cmd; |
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comm_mgmt_self_msg_proc proc; |
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}; |
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struct comm_mgmt_self_msg_info { |
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u8 cmd_num; |
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struct comm_mgmt_self_msg_sub_info info[HINIC_COMM_SELF_CMD_MAX]; |
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}; |
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struct hinic_pfhwdev { |
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struct hinic_hwdev hwdev; |
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struct hinic_pf_to_mgmt pf_to_mgmt; |
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struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; |
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struct comm_mgmt_self_msg_info proc; |
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}; |
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struct hinic_dev_cap { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u8 rsvd1[5]; |
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u8 intr_type; |
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u8 max_cos_id; |
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u8 er_id; |
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u8 port_id; |
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u8 max_vf; |
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u8 rsvd2[62]; |
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u16 max_sqs; |
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u16 max_rqs; |
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u16 max_vf_sqs; |
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u16 max_vf_rqs; |
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u8 rsvd3[204]; |
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}; |
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union hinic_fault_hw_mgmt { |
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u32 val[4]; |
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/* valid only type == FAULT_TYPE_CHIP */ |
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struct { |
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u8 node_id; |
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u8 err_level; |
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u16 err_type; |
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u32 err_csr_addr; |
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u32 err_csr_value; |
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/* func_id valid only if err_level == FAULT_LEVEL_SERIOUS_FLR */ |
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u16 func_id; |
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u16 rsvd2; |
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} chip; |
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/* valid only if type == FAULT_TYPE_UCODE */ |
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struct { |
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u8 cause_id; |
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u8 core_id; |
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u8 c_id; |
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u8 rsvd3; |
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u32 epc; |
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u32 rsvd4; |
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u32 rsvd5; |
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} ucode; |
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/* valid only if type == FAULT_TYPE_MEM_RD_TIMEOUT || |
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* FAULT_TYPE_MEM_WR_TIMEOUT |
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*/ |
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struct { |
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u32 err_csr_ctrl; |
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u32 err_csr_data; |
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u32 ctrl_tab; |
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u32 mem_index; |
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} mem_timeout; |
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/* valid only if type == FAULT_TYPE_REG_RD_TIMEOUT || |
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* FAULT_TYPE_REG_WR_TIMEOUT |
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*/ |
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struct { |
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u32 err_csr; |
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u32 rsvd6; |
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u32 rsvd7; |
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u32 rsvd8; |
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} reg_timeout; |
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struct { |
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/* 0: read; 1: write */ |
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u8 op_type; |
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u8 port_id; |
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u8 dev_ad; |
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u8 rsvd9; |
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u32 csr_addr; |
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u32 op_data; |
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u32 rsvd10; |
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} phy_fault; |
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}; |
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struct hinic_fault_event { |
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u8 type; |
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u8 fault_level; |
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u8 rsvd0[2]; |
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union hinic_fault_hw_mgmt event; |
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}; |
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struct hinic_cmd_fault_event { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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struct hinic_fault_event event; |
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}; |
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enum hinic_fault_type { |
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FAULT_TYPE_CHIP, |
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FAULT_TYPE_UCODE, |
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FAULT_TYPE_MEM_RD_TIMEOUT, |
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FAULT_TYPE_MEM_WR_TIMEOUT, |
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FAULT_TYPE_REG_RD_TIMEOUT, |
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FAULT_TYPE_REG_WR_TIMEOUT, |
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FAULT_TYPE_PHY_FAULT, |
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FAULT_TYPE_MAX, |
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}; |
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enum hinic_fault_err_level { |
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FAULT_LEVEL_FATAL, |
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FAULT_LEVEL_SERIOUS_RESET, |
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FAULT_LEVEL_SERIOUS_FLR, |
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FAULT_LEVEL_GENERAL, |
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FAULT_LEVEL_SUGGESTION, |
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FAULT_LEVEL_MAX |
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}; |
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struct hinic_mgmt_watchdog_info { |
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u8 status; |
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u8 version; |
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u8 rsvd0[6]; |
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u32 curr_time_h; |
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u32 curr_time_l; |
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u32 task_id; |
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u32 rsv; |
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u32 reg[13]; |
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u32 pc; |
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u32 lr; |
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u32 cpsr; |
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u32 stack_top; |
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u32 stack_bottom; |
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u32 sp; |
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u32 curr_used; |
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u32 peak_used; |
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u32 is_overflow; |
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u32 stack_actlen; |
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u8 data[1024]; |
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}; |
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void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, |
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enum hinic_mgmt_msg_cmd cmd, void *handle, |
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void (*handler)(void *handle, void *buf_in, |
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u16 in_size, void *buf_out, |
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u16 *out_size)); |
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void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, |
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enum hinic_mgmt_msg_cmd cmd); |
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int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, |
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void *buf_in, u16 in_size, void *buf_out, |
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u16 *out_size); |
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int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, |
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void *buf_in, u16 in_size, void *buf_out, |
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u16 *out_size); |
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int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); |
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void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); |
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struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev, struct devlink *devlink); |
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void hinic_free_hwdev(struct hinic_hwdev *hwdev); |
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int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); |
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int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); |
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struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); |
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struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); |
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int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); |
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int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, |
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u8 pending_limit, u8 coalesc_timer, |
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u8 lli_timer_cfg, u8 lli_credit_limit, |
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u8 resend_timer); |
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int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, |
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u8 pending_limit, u8 coalesc_timer); |
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void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, |
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enum hinic_msix_state flag); |
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int hinic_get_interrupt_cfg(struct hinic_hwdev *hwdev, |
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struct hinic_msix_config *interrupt_info); |
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int hinic_set_interrupt_cfg(struct hinic_hwdev *hwdev, |
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struct hinic_msix_config *interrupt_info); |
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int hinic_get_board_info(struct hinic_hwdev *hwdev, |
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struct hinic_comm_board_info *board_info); |
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#endif
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