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193 lines
6.0 KiB
193 lines
6.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright(c) 2015 EZchip Technologies. |
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*/ |
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#ifndef _NPS_ENET_H |
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#define _NPS_ENET_H |
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/* default values */ |
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#define NPS_ENET_NAPI_POLL_WEIGHT 0x2 |
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#define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF |
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#define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7 |
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#define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5 |
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#define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC |
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#define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7 |
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#define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3 |
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#define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14 |
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#define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC |
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#define NPS_ENET_ENABLE 1 |
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#define NPS_ENET_DISABLE 0 |
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/* register definitions */ |
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#define NPS_ENET_REG_TX_CTL 0x800 |
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#define NPS_ENET_REG_TX_BUF 0x808 |
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#define NPS_ENET_REG_RX_CTL 0x810 |
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#define NPS_ENET_REG_RX_BUF 0x818 |
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#define NPS_ENET_REG_BUF_INT_ENABLE 0x8C0 |
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#define NPS_ENET_REG_GE_MAC_CFG_0 0x1000 |
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#define NPS_ENET_REG_GE_MAC_CFG_1 0x1004 |
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#define NPS_ENET_REG_GE_MAC_CFG_2 0x1008 |
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#define NPS_ENET_REG_GE_MAC_CFG_3 0x100C |
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#define NPS_ENET_REG_GE_RST 0x1400 |
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#define NPS_ENET_REG_PHASE_FIFO_CTL 0x1404 |
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/* Tx control register masks and shifts */ |
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#define TX_CTL_NT_MASK 0x7FF |
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#define TX_CTL_NT_SHIFT 0 |
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#define TX_CTL_ET_MASK 0x4000 |
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#define TX_CTL_ET_SHIFT 14 |
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#define TX_CTL_CT_MASK 0x8000 |
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#define TX_CTL_CT_SHIFT 15 |
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/* Rx control register masks and shifts */ |
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#define RX_CTL_NR_MASK 0x7FF |
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#define RX_CTL_NR_SHIFT 0 |
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#define RX_CTL_CRC_MASK 0x2000 |
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#define RX_CTL_CRC_SHIFT 13 |
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#define RX_CTL_ER_MASK 0x4000 |
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#define RX_CTL_ER_SHIFT 14 |
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#define RX_CTL_CR_MASK 0x8000 |
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#define RX_CTL_CR_SHIFT 15 |
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/* Interrupt enable for data buffer events register masks and shifts */ |
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#define RX_RDY_MASK 0x1 |
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#define RX_RDY_SHIFT 0 |
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#define TX_DONE_MASK 0x2 |
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#define TX_DONE_SHIFT 1 |
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/* Gbps Eth MAC Configuration 0 register masks and shifts */ |
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#define CFG_0_RX_EN_MASK 0x1 |
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#define CFG_0_RX_EN_SHIFT 0 |
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#define CFG_0_TX_EN_MASK 0x2 |
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#define CFG_0_TX_EN_SHIFT 1 |
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#define CFG_0_TX_FC_EN_MASK 0x4 |
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#define CFG_0_TX_FC_EN_SHIFT 2 |
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#define CFG_0_TX_PAD_EN_MASK 0x8 |
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#define CFG_0_TX_PAD_EN_SHIFT 3 |
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#define CFG_0_TX_CRC_EN_MASK 0x10 |
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#define CFG_0_TX_CRC_EN_SHIFT 4 |
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#define CFG_0_RX_FC_EN_MASK 0x20 |
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#define CFG_0_RX_FC_EN_SHIFT 5 |
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#define CFG_0_RX_CRC_STRIP_MASK 0x40 |
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#define CFG_0_RX_CRC_STRIP_SHIFT 6 |
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#define CFG_0_RX_CRC_IGNORE_MASK 0x80 |
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#define CFG_0_RX_CRC_IGNORE_SHIFT 7 |
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#define CFG_0_RX_LENGTH_CHECK_EN_MASK 0x100 |
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#define CFG_0_RX_LENGTH_CHECK_EN_SHIFT 8 |
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#define CFG_0_TX_FC_RETR_MASK 0xE00 |
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#define CFG_0_TX_FC_RETR_SHIFT 9 |
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#define CFG_0_RX_IFG_MASK 0xF000 |
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#define CFG_0_RX_IFG_SHIFT 12 |
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#define CFG_0_TX_IFG_MASK 0x3F0000 |
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#define CFG_0_TX_IFG_SHIFT 16 |
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#define CFG_0_RX_PR_CHECK_EN_MASK 0x400000 |
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#define CFG_0_RX_PR_CHECK_EN_SHIFT 22 |
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#define CFG_0_NIB_MODE_MASK 0x800000 |
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#define CFG_0_NIB_MODE_SHIFT 23 |
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#define CFG_0_TX_IFG_NIB_MASK 0xF000000 |
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#define CFG_0_TX_IFG_NIB_SHIFT 24 |
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#define CFG_0_TX_PR_LEN_MASK 0xF0000000 |
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#define CFG_0_TX_PR_LEN_SHIFT 28 |
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/* Gbps Eth MAC Configuration 1 register masks and shifts */ |
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#define CFG_1_OCTET_0_MASK 0x000000FF |
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#define CFG_1_OCTET_0_SHIFT 0 |
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#define CFG_1_OCTET_1_MASK 0x0000FF00 |
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#define CFG_1_OCTET_1_SHIFT 8 |
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#define CFG_1_OCTET_2_MASK 0x00FF0000 |
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#define CFG_1_OCTET_2_SHIFT 16 |
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#define CFG_1_OCTET_3_MASK 0xFF000000 |
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#define CFG_1_OCTET_3_SHIFT 24 |
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/* Gbps Eth MAC Configuration 2 register masks and shifts */ |
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#define CFG_2_OCTET_4_MASK 0x000000FF |
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#define CFG_2_OCTET_4_SHIFT 0 |
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#define CFG_2_OCTET_5_MASK 0x0000FF00 |
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#define CFG_2_OCTET_5_SHIFT 8 |
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#define CFG_2_DISK_MC_MASK 0x00100000 |
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#define CFG_2_DISK_MC_SHIFT 20 |
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#define CFG_2_DISK_BC_MASK 0x00200000 |
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#define CFG_2_DISK_BC_SHIFT 21 |
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#define CFG_2_DISK_DA_MASK 0x00400000 |
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#define CFG_2_DISK_DA_SHIFT 22 |
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#define CFG_2_STAT_EN_MASK 0x3000000 |
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#define CFG_2_STAT_EN_SHIFT 24 |
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#define CFG_2_TRANSMIT_FLUSH_EN_MASK 0x80000000 |
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#define CFG_2_TRANSMIT_FLUSH_EN_SHIFT 31 |
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/* Gbps Eth MAC Configuration 3 register masks and shifts */ |
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#define CFG_3_TM_HD_MODE_MASK 0x1 |
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#define CFG_3_TM_HD_MODE_SHIFT 0 |
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#define CFG_3_RX_CBFC_EN_MASK 0x2 |
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#define CFG_3_RX_CBFC_EN_SHIFT 1 |
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#define CFG_3_RX_CBFC_REDIR_EN_MASK 0x4 |
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#define CFG_3_RX_CBFC_REDIR_EN_SHIFT 2 |
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#define CFG_3_REDIRECT_CBFC_SEL_MASK 0x18 |
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#define CFG_3_REDIRECT_CBFC_SEL_SHIFT 3 |
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#define CFG_3_CF_DROP_MASK 0x20 |
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#define CFG_3_CF_DROP_SHIFT 5 |
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#define CFG_3_CF_TIMEOUT_MASK 0x3C0 |
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#define CFG_3_CF_TIMEOUT_SHIFT 6 |
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#define CFG_3_RX_IFG_TH_MASK 0x7C00 |
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#define CFG_3_RX_IFG_TH_SHIFT 10 |
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#define CFG_3_TX_CBFC_EN_MASK 0x8000 |
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#define CFG_3_TX_CBFC_EN_SHIFT 15 |
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#define CFG_3_MAX_LEN_MASK 0x3FFF0000 |
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#define CFG_3_MAX_LEN_SHIFT 16 |
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#define CFG_3_EXT_OOB_CBFC_SEL_MASK 0xC0000000 |
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#define CFG_3_EXT_OOB_CBFC_SEL_SHIFT 30 |
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/* GE MAC, PCS reset control register masks and shifts */ |
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#define RST_SPCS_MASK 0x1 |
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#define RST_SPCS_SHIFT 0 |
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#define RST_GMAC_0_MASK 0x100 |
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#define RST_GMAC_0_SHIFT 8 |
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/* Tx phase sync FIFO control register masks and shifts */ |
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#define PHASE_FIFO_CTL_RST_MASK 0x1 |
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#define PHASE_FIFO_CTL_RST_SHIFT 0 |
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#define PHASE_FIFO_CTL_INIT_MASK 0x2 |
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#define PHASE_FIFO_CTL_INIT_SHIFT 1 |
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/** |
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* struct nps_enet_priv - Storage of ENET's private information. |
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* @regs_base: Base address of ENET memory-mapped control registers. |
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* @irq: For RX/TX IRQ number. |
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* @tx_skb: socket buffer of sent frame. |
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* @napi: Structure for NAPI. |
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*/ |
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struct nps_enet_priv { |
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void __iomem *regs_base; |
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s32 irq; |
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struct sk_buff *tx_skb; |
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struct napi_struct napi; |
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u32 ge_mac_cfg_2_value; |
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u32 ge_mac_cfg_3_value; |
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}; |
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/** |
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* nps_enet_reg_set - Sets ENET register with provided value. |
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* @priv: Pointer to EZchip ENET private data structure. |
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* @reg: Register offset from base address. |
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* @value: Value to set in register. |
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*/ |
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static inline void nps_enet_reg_set(struct nps_enet_priv *priv, |
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s32 reg, s32 value) |
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{ |
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iowrite32be(value, priv->regs_base + reg); |
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} |
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/** |
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* nps_enet_reg_get - Gets value of specified ENET register. |
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* @priv: Pointer to EZchip ENET private data structure. |
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* @reg: Register offset from base address. |
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* |
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* returns: Value of requested register. |
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*/ |
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static inline u32 nps_enet_reg_get(struct nps_enet_priv *priv, s32 reg) |
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{ |
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return ioread32be(priv->regs_base + reg); |
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} |
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#endif /* _NPS_ENET_H */
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