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936 lines
24 KiB
936 lines
24 KiB
/********************************************************************** |
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* Author: Cavium, Inc. |
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* |
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* Contact: [email protected] |
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* Please include "LiquidIO" in the subject. |
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* |
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* Copyright (c) 2003-2016 Cavium, Inc. |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more |
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* details. |
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**********************************************************************/ |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/vmalloc.h> |
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#include "liquidio_common.h" |
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#include "octeon_droq.h" |
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#include "octeon_iq.h" |
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#include "response_manager.h" |
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#include "octeon_device.h" |
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#include "octeon_main.h" |
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#include "octeon_network.h" |
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#include "cn66xx_device.h" |
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#include "cn23xx_pf_device.h" |
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#include "cn23xx_vf_device.h" |
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|
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struct iq_post_status { |
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int status; |
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int index; |
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}; |
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|
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static void check_db_timeout(struct work_struct *work); |
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static void __check_db_timeout(struct octeon_device *oct, u64 iq_no); |
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|
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static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *); |
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|
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static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no) |
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{ |
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struct octeon_instr_queue *iq = |
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(struct octeon_instr_queue *)oct->instr_queue[iq_no]; |
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return iq->iqcmd_64B; |
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} |
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|
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#define IQ_INSTR_MODE_32B(oct, iq_no) (!IQ_INSTR_MODE_64B(oct, iq_no)) |
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|
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/* Define this to return the request status comaptible to old code */ |
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/*#define OCTEON_USE_OLD_REQ_STATUS*/ |
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|
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/* Return 0 on success, 1 on failure */ |
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int octeon_init_instr_queue(struct octeon_device *oct, |
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union oct_txpciq txpciq, |
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u32 num_descs) |
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{ |
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struct octeon_instr_queue *iq; |
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struct octeon_iq_config *conf = NULL; |
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u32 iq_no = (u32)txpciq.s.q_no; |
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u32 q_size; |
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struct cavium_wq *db_wq; |
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int numa_node = dev_to_node(&oct->pci_dev->dev); |
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|
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if (OCTEON_CN6XXX(oct)) |
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx))); |
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else if (OCTEON_CN23XX_PF(oct)) |
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf))); |
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else if (OCTEON_CN23XX_VF(oct)) |
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conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf))); |
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|
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if (!conf) { |
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dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n", |
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oct->chip_id); |
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return 1; |
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} |
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q_size = (u32)conf->instr_type * num_descs; |
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|
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iq = oct->instr_queue[iq_no]; |
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|
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iq->oct_dev = oct; |
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|
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iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma); |
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if (!iq->base_addr) { |
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dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n", |
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iq_no); |
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return 1; |
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} |
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|
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iq->max_count = num_descs; |
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|
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/* Initialize a list to holds requests that have been posted to Octeon |
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* but has yet to be fetched by octeon |
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*/ |
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iq->request_list = vzalloc_node(array_size(num_descs, sizeof(*iq->request_list)), |
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numa_node); |
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if (!iq->request_list) |
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iq->request_list = vzalloc(array_size(num_descs, sizeof(*iq->request_list))); |
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if (!iq->request_list) { |
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lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); |
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dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n", |
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iq_no); |
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return 1; |
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} |
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|
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dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %pad count: %d\n", |
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iq_no, iq->base_addr, &iq->base_addr_dma, iq->max_count); |
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|
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iq->txpciq.u64 = txpciq.u64; |
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iq->fill_threshold = (u32)conf->db_min; |
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iq->fill_cnt = 0; |
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iq->host_write_index = 0; |
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iq->octeon_read_index = 0; |
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iq->flush_index = 0; |
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iq->last_db_time = 0; |
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iq->do_auto_flush = 1; |
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iq->db_timeout = (u32)conf->db_timeout; |
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atomic_set(&iq->instr_pending, 0); |
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iq->pkts_processed = 0; |
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|
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/* Initialize the spinlock for this instruction queue */ |
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spin_lock_init(&iq->lock); |
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if (iq_no == 0) { |
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iq->allow_soft_cmds = true; |
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spin_lock_init(&iq->post_lock); |
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} else { |
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iq->allow_soft_cmds = false; |
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} |
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spin_lock_init(&iq->iq_flush_running_lock); |
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|
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oct->io_qmask.iq |= BIT_ULL(iq_no); |
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|
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/* Set the 32B/64B mode for each input queue */ |
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oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no); |
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iq->iqcmd_64B = (conf->instr_type == 64); |
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|
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oct->fn_list.setup_iq_regs(oct, iq_no); |
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|
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oct->check_db_wq[iq_no].wq = alloc_workqueue("check_iq_db", |
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WQ_MEM_RECLAIM, |
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0); |
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if (!oct->check_db_wq[iq_no].wq) { |
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vfree(iq->request_list); |
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iq->request_list = NULL; |
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lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma); |
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dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n", |
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iq_no); |
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return 1; |
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} |
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db_wq = &oct->check_db_wq[iq_no]; |
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|
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INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout); |
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db_wq->wk.ctxptr = oct; |
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db_wq->wk.ctxul = iq_no; |
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queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1)); |
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|
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return 0; |
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} |
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int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no) |
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{ |
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u64 desc_size = 0, q_size; |
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struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; |
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|
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cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work); |
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destroy_workqueue(oct->check_db_wq[iq_no].wq); |
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if (OCTEON_CN6XXX(oct)) |
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desc_size = |
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx)); |
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else if (OCTEON_CN23XX_PF(oct)) |
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desc_size = |
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf)); |
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else if (OCTEON_CN23XX_VF(oct)) |
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desc_size = |
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CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf)); |
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|
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vfree(iq->request_list); |
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|
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if (iq->base_addr) { |
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q_size = iq->max_count * desc_size; |
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lio_dma_free(oct, (u32)q_size, iq->base_addr, |
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iq->base_addr_dma); |
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oct->io_qmask.iq &= ~(1ULL << iq_no); |
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vfree(oct->instr_queue[iq_no]); |
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oct->instr_queue[iq_no] = NULL; |
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oct->num_iqs--; |
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return 0; |
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} |
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return 1; |
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} |
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|
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/* Return 0 on success, 1 on failure */ |
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int octeon_setup_iq(struct octeon_device *oct, |
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int ifidx, |
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int q_index, |
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union oct_txpciq txpciq, |
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u32 num_descs, |
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void *app_ctx) |
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{ |
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u32 iq_no = (u32)txpciq.s.q_no; |
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int numa_node = dev_to_node(&oct->pci_dev->dev); |
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|
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if (oct->instr_queue[iq_no]) { |
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dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n", |
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iq_no); |
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oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64; |
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oct->instr_queue[iq_no]->app_ctx = app_ctx; |
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return 0; |
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} |
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oct->instr_queue[iq_no] = |
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vzalloc_node(sizeof(struct octeon_instr_queue), numa_node); |
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if (!oct->instr_queue[iq_no]) |
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oct->instr_queue[iq_no] = |
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vzalloc(sizeof(struct octeon_instr_queue)); |
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if (!oct->instr_queue[iq_no]) |
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return 1; |
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oct->instr_queue[iq_no]->q_index = q_index; |
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oct->instr_queue[iq_no]->app_ctx = app_ctx; |
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oct->instr_queue[iq_no]->ifidx = ifidx; |
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if (octeon_init_instr_queue(oct, txpciq, num_descs)) { |
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vfree(oct->instr_queue[iq_no]); |
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oct->instr_queue[iq_no] = NULL; |
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return 1; |
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} |
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oct->num_iqs++; |
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if (oct->fn_list.enable_io_queues(oct)) { |
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octeon_delete_instr_queue(oct, iq_no); |
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return 1; |
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} |
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return 0; |
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} |
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int lio_wait_for_instr_fetch(struct octeon_device *oct) |
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{ |
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int i, retry = 1000, pending, instr_cnt = 0; |
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do { |
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instr_cnt = 0; |
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|
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for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { |
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if (!(oct->io_qmask.iq & BIT_ULL(i))) |
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continue; |
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pending = |
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atomic_read(&oct->instr_queue[i]->instr_pending); |
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if (pending) |
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__check_db_timeout(oct, i); |
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instr_cnt += pending; |
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} |
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if (instr_cnt == 0) |
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break; |
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schedule_timeout_uninterruptible(1); |
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} while (retry-- && instr_cnt); |
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return instr_cnt; |
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} |
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|
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static inline void |
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ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq) |
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{ |
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if (atomic_read(&oct->status) == OCT_DEV_RUNNING) { |
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writel(iq->fill_cnt, iq->doorbell_reg); |
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/* make sure doorbell write goes through */ |
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iq->fill_cnt = 0; |
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iq->last_db_time = jiffies; |
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return; |
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} |
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} |
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|
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void |
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octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no) |
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{ |
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struct octeon_instr_queue *iq; |
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|
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iq = oct->instr_queue[iq_no]; |
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spin_lock(&iq->post_lock); |
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if (iq->fill_cnt) |
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ring_doorbell(oct, iq); |
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spin_unlock(&iq->post_lock); |
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} |
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static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq, |
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u8 *cmd) |
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{ |
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u8 *iqptr, cmdsize; |
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|
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cmdsize = ((iq->iqcmd_64B) ? 64 : 32); |
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iqptr = iq->base_addr + (cmdsize * iq->host_write_index); |
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memcpy(iqptr, cmd, cmdsize); |
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} |
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|
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static inline struct iq_post_status |
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__post_command2(struct octeon_instr_queue *iq, u8 *cmd) |
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{ |
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struct iq_post_status st; |
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st.status = IQ_SEND_OK; |
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|
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/* This ensures that the read index does not wrap around to the same |
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* position if queue gets full before Octeon could fetch any instr. |
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*/ |
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if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) { |
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st.status = IQ_SEND_FAILED; |
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st.index = -1; |
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return st; |
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} |
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if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2)) |
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st.status = IQ_SEND_STOP; |
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|
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__copy_cmd_into_iq(iq, cmd); |
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/* "index" is returned, host_write_index is modified. */ |
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st.index = iq->host_write_index; |
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iq->host_write_index = incr_index(iq->host_write_index, 1, |
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iq->max_count); |
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iq->fill_cnt++; |
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|
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/* Flush the command into memory. We need to be sure the data is in |
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* memory before indicating that the instruction is pending. |
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*/ |
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wmb(); |
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|
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atomic_inc(&iq->instr_pending); |
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return st; |
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} |
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|
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int |
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octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype, |
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void (*fn)(void *)) |
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{ |
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if (reqtype > REQTYPE_LAST) { |
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dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n", |
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__func__, reqtype); |
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return -EINVAL; |
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} |
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reqtype_free_fn[oct->octeon_id][reqtype] = fn; |
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|
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return 0; |
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} |
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|
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static inline void |
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__add_to_request_list(struct octeon_instr_queue *iq, |
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int idx, void *buf, int reqtype) |
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{ |
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iq->request_list[idx].buf = buf; |
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iq->request_list[idx].reqtype = reqtype; |
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} |
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|
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/* Can only run in process context */ |
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int |
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lio_process_iq_request_list(struct octeon_device *oct, |
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struct octeon_instr_queue *iq, u32 napi_budget) |
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{ |
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struct cavium_wq *cwq = &oct->dma_comp_wq; |
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int reqtype; |
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void *buf; |
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u32 old = iq->flush_index; |
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u32 inst_count = 0; |
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unsigned int pkts_compl = 0, bytes_compl = 0; |
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struct octeon_soft_command *sc; |
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unsigned long flags; |
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|
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while (old != iq->octeon_read_index) { |
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reqtype = iq->request_list[old].reqtype; |
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buf = iq->request_list[old].buf; |
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|
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if (reqtype == REQTYPE_NONE) |
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goto skip_this; |
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octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl, |
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&bytes_compl); |
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|
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switch (reqtype) { |
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case REQTYPE_NORESP_NET: |
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case REQTYPE_NORESP_NET_SG: |
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case REQTYPE_RESP_NET_SG: |
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reqtype_free_fn[oct->octeon_id][reqtype](buf); |
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break; |
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case REQTYPE_RESP_NET: |
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case REQTYPE_SOFT_COMMAND: |
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sc = buf; |
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/* We're expecting a response from Octeon. |
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* It's up to lio_process_ordered_list() to |
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* process sc. Add sc to the ordered soft |
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* command response list because we expect |
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* a response from Octeon. |
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*/ |
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spin_lock_irqsave(&oct->response_list |
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[OCTEON_ORDERED_SC_LIST].lock, flags); |
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atomic_inc(&oct->response_list |
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[OCTEON_ORDERED_SC_LIST].pending_req_count); |
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list_add_tail(&sc->node, &oct->response_list |
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[OCTEON_ORDERED_SC_LIST].head); |
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spin_unlock_irqrestore(&oct->response_list |
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[OCTEON_ORDERED_SC_LIST].lock, |
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flags); |
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break; |
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default: |
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dev_err(&oct->pci_dev->dev, |
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"%s Unknown reqtype: %d buf: %p at idx %d\n", |
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__func__, reqtype, buf, old); |
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} |
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|
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iq->request_list[old].buf = NULL; |
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iq->request_list[old].reqtype = 0; |
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|
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skip_this: |
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inst_count++; |
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old = incr_index(old, 1, iq->max_count); |
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|
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if ((napi_budget) && (inst_count >= napi_budget)) |
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break; |
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} |
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if (bytes_compl) |
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octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl, |
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bytes_compl); |
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iq->flush_index = old; |
|
|
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if (atomic_read(&oct->response_list |
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[OCTEON_ORDERED_SC_LIST].pending_req_count)) |
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queue_work(cwq->wq, &cwq->wk.work.work); |
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|
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return inst_count; |
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} |
|
|
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/* Can only be called from process context */ |
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int |
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octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq, |
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u32 napi_budget) |
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{ |
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u32 inst_processed = 0; |
|
u32 tot_inst_processed = 0; |
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int tx_done = 1; |
|
|
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if (!spin_trylock(&iq->iq_flush_running_lock)) |
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return tx_done; |
|
|
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spin_lock_bh(&iq->lock); |
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|
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iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq); |
|
|
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do { |
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/* Process any outstanding IQ packets. */ |
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if (iq->flush_index == iq->octeon_read_index) |
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break; |
|
|
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if (napi_budget) |
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inst_processed = |
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lio_process_iq_request_list(oct, iq, |
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napi_budget - |
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tot_inst_processed); |
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else |
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inst_processed = |
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lio_process_iq_request_list(oct, iq, 0); |
|
|
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if (inst_processed) { |
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iq->pkts_processed += inst_processed; |
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atomic_sub(inst_processed, &iq->instr_pending); |
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iq->stats.instr_processed += inst_processed; |
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} |
|
|
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tot_inst_processed += inst_processed; |
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} while (tot_inst_processed < napi_budget); |
|
|
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if (napi_budget && (tot_inst_processed >= napi_budget)) |
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tx_done = 0; |
|
|
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iq->last_db_time = jiffies; |
|
|
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spin_unlock_bh(&iq->lock); |
|
|
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spin_unlock(&iq->iq_flush_running_lock); |
|
|
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return tx_done; |
|
} |
|
|
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/* Process instruction queue after timeout. |
|
* This routine gets called from a workqueue or when removing the module. |
|
*/ |
|
static void __check_db_timeout(struct octeon_device *oct, u64 iq_no) |
|
{ |
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struct octeon_instr_queue *iq; |
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u64 next_time; |
|
|
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if (!oct) |
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return; |
|
|
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iq = oct->instr_queue[iq_no]; |
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if (!iq) |
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return; |
|
|
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/* return immediately, if no work pending */ |
|
if (!atomic_read(&iq->instr_pending)) |
|
return; |
|
/* If jiffies - last_db_time < db_timeout do nothing */ |
|
next_time = iq->last_db_time + iq->db_timeout; |
|
if (!time_after(jiffies, (unsigned long)next_time)) |
|
return; |
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iq->last_db_time = jiffies; |
|
|
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/* Flush the instruction queue */ |
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octeon_flush_iq(oct, iq, 0); |
|
|
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lio_enable_irq(NULL, iq); |
|
} |
|
|
|
/* Called by the Poll thread at regular intervals to check the instruction |
|
* queue for commands to be posted and for commands that were fetched by Octeon. |
|
*/ |
|
static void check_db_timeout(struct work_struct *work) |
|
{ |
|
struct cavium_wk *wk = (struct cavium_wk *)work; |
|
struct octeon_device *oct = (struct octeon_device *)wk->ctxptr; |
|
u64 iq_no = wk->ctxul; |
|
struct cavium_wq *db_wq = &oct->check_db_wq[iq_no]; |
|
u32 delay = 10; |
|
|
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__check_db_timeout(oct, iq_no); |
|
queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(delay)); |
|
} |
|
|
|
int |
|
octeon_send_command(struct octeon_device *oct, u32 iq_no, |
|
u32 force_db, void *cmd, void *buf, |
|
u32 datasize, u32 reqtype) |
|
{ |
|
int xmit_stopped; |
|
struct iq_post_status st; |
|
struct octeon_instr_queue *iq = oct->instr_queue[iq_no]; |
|
|
|
/* Get the lock and prevent other tasks and tx interrupt handler from |
|
* running. |
|
*/ |
|
if (iq->allow_soft_cmds) |
|
spin_lock_bh(&iq->post_lock); |
|
|
|
st = __post_command2(iq, cmd); |
|
|
|
if (st.status != IQ_SEND_FAILED) { |
|
xmit_stopped = octeon_report_sent_bytes_to_bql(buf, reqtype); |
|
__add_to_request_list(iq, st.index, buf, reqtype); |
|
INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize); |
|
INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1); |
|
|
|
if (iq->fill_cnt >= MAX_OCTEON_FILL_COUNT || force_db || |
|
xmit_stopped || st.status == IQ_SEND_STOP) |
|
ring_doorbell(oct, iq); |
|
} else { |
|
INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1); |
|
} |
|
|
|
if (iq->allow_soft_cmds) |
|
spin_unlock_bh(&iq->post_lock); |
|
|
|
/* This is only done here to expedite packets being flushed |
|
* for cases where there are no IQ completion interrupts. |
|
*/ |
|
|
|
return st.status; |
|
} |
|
|
|
void |
|
octeon_prepare_soft_command(struct octeon_device *oct, |
|
struct octeon_soft_command *sc, |
|
u8 opcode, |
|
u8 subcode, |
|
u32 irh_ossp, |
|
u64 ossp0, |
|
u64 ossp1) |
|
{ |
|
struct octeon_config *oct_cfg; |
|
struct octeon_instr_ih2 *ih2; |
|
struct octeon_instr_ih3 *ih3; |
|
struct octeon_instr_pki_ih3 *pki_ih3; |
|
struct octeon_instr_irh *irh; |
|
struct octeon_instr_rdp *rdp; |
|
|
|
WARN_ON(opcode > 15); |
|
WARN_ON(subcode > 127); |
|
|
|
oct_cfg = octeon_get_conf(oct); |
|
|
|
if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { |
|
ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; |
|
|
|
ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind; |
|
|
|
pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3; |
|
|
|
pki_ih3->w = 1; |
|
pki_ih3->raw = 1; |
|
pki_ih3->utag = 1; |
|
pki_ih3->uqpg = |
|
oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg; |
|
pki_ih3->utt = 1; |
|
pki_ih3->tag = LIO_CONTROL; |
|
pki_ih3->tagtype = ATOMIC_TAG; |
|
pki_ih3->qpg = |
|
oct->instr_queue[sc->iq_no]->txpciq.s.ctrl_qpg; |
|
|
|
pki_ih3->pm = 0x7; |
|
pki_ih3->sl = 8; |
|
|
|
if (sc->datasize) |
|
ih3->dlengsz = sc->datasize; |
|
|
|
irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; |
|
irh->opcode = opcode; |
|
irh->subcode = subcode; |
|
|
|
/* opcode/subcode specific parameters (ossp) */ |
|
irh->ossp = irh_ossp; |
|
sc->cmd.cmd3.ossp[0] = ossp0; |
|
sc->cmd.cmd3.ossp[1] = ossp1; |
|
|
|
if (sc->rdatasize) { |
|
rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp; |
|
rdp->pcie_port = oct->pcie_port; |
|
rdp->rlen = sc->rdatasize; |
|
|
|
irh->rflag = 1; |
|
/*PKI IH3*/ |
|
/* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */ |
|
ih3->fsz = LIO_SOFTCMDRESP_IH3; |
|
} else { |
|
irh->rflag = 0; |
|
/*PKI IH3*/ |
|
/* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */ |
|
ih3->fsz = LIO_PCICMD_O3; |
|
} |
|
|
|
} else { |
|
ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; |
|
ih2->tagtype = ATOMIC_TAG; |
|
ih2->tag = LIO_CONTROL; |
|
ih2->raw = 1; |
|
ih2->grp = CFG_GET_CTRL_Q_GRP(oct_cfg); |
|
|
|
if (sc->datasize) { |
|
ih2->dlengsz = sc->datasize; |
|
ih2->rs = 1; |
|
} |
|
|
|
irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh; |
|
irh->opcode = opcode; |
|
irh->subcode = subcode; |
|
|
|
/* opcode/subcode specific parameters (ossp) */ |
|
irh->ossp = irh_ossp; |
|
sc->cmd.cmd2.ossp[0] = ossp0; |
|
sc->cmd.cmd2.ossp[1] = ossp1; |
|
|
|
if (sc->rdatasize) { |
|
rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd2.rdp; |
|
rdp->pcie_port = oct->pcie_port; |
|
rdp->rlen = sc->rdatasize; |
|
|
|
irh->rflag = 1; |
|
/* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */ |
|
ih2->fsz = LIO_SOFTCMDRESP_IH2; |
|
} else { |
|
irh->rflag = 0; |
|
/* irh + ossp[0] + ossp[1] = 24 bytes */ |
|
ih2->fsz = LIO_PCICMD_O2; |
|
} |
|
} |
|
} |
|
|
|
int octeon_send_soft_command(struct octeon_device *oct, |
|
struct octeon_soft_command *sc) |
|
{ |
|
struct octeon_instr_queue *iq; |
|
struct octeon_instr_ih2 *ih2; |
|
struct octeon_instr_ih3 *ih3; |
|
struct octeon_instr_irh *irh; |
|
u32 len; |
|
|
|
iq = oct->instr_queue[sc->iq_no]; |
|
if (!iq->allow_soft_cmds) { |
|
dev_err(&oct->pci_dev->dev, "Soft commands are not allowed on Queue %d\n", |
|
sc->iq_no); |
|
INCR_INSTRQUEUE_PKT_COUNT(oct, sc->iq_no, instr_dropped, 1); |
|
return IQ_SEND_FAILED; |
|
} |
|
|
|
if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { |
|
ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3; |
|
if (ih3->dlengsz) { |
|
WARN_ON(!sc->dmadptr); |
|
sc->cmd.cmd3.dptr = sc->dmadptr; |
|
} |
|
irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh; |
|
if (irh->rflag) { |
|
WARN_ON(!sc->dmarptr); |
|
WARN_ON(!sc->status_word); |
|
*sc->status_word = COMPLETION_WORD_INIT; |
|
sc->cmd.cmd3.rptr = sc->dmarptr; |
|
} |
|
len = (u32)ih3->dlengsz; |
|
} else { |
|
ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2; |
|
if (ih2->dlengsz) { |
|
WARN_ON(!sc->dmadptr); |
|
sc->cmd.cmd2.dptr = sc->dmadptr; |
|
} |
|
irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh; |
|
if (irh->rflag) { |
|
WARN_ON(!sc->dmarptr); |
|
WARN_ON(!sc->status_word); |
|
*sc->status_word = COMPLETION_WORD_INIT; |
|
sc->cmd.cmd2.rptr = sc->dmarptr; |
|
} |
|
len = (u32)ih2->dlengsz; |
|
} |
|
|
|
sc->expiry_time = jiffies + msecs_to_jiffies(LIO_SC_MAX_TMO_MS); |
|
|
|
return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc, |
|
len, REQTYPE_SOFT_COMMAND)); |
|
} |
|
|
|
int octeon_setup_sc_buffer_pool(struct octeon_device *oct) |
|
{ |
|
int i; |
|
u64 dma_addr; |
|
struct octeon_soft_command *sc; |
|
|
|
INIT_LIST_HEAD(&oct->sc_buf_pool.head); |
|
spin_lock_init(&oct->sc_buf_pool.lock); |
|
atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0); |
|
|
|
for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) { |
|
sc = (struct octeon_soft_command *) |
|
lio_dma_alloc(oct, |
|
SOFT_COMMAND_BUFFER_SIZE, |
|
(dma_addr_t *)&dma_addr); |
|
if (!sc) { |
|
octeon_free_sc_buffer_pool(oct); |
|
return 1; |
|
} |
|
|
|
sc->dma_addr = dma_addr; |
|
sc->size = SOFT_COMMAND_BUFFER_SIZE; |
|
|
|
list_add_tail(&sc->node, &oct->sc_buf_pool.head); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
int octeon_free_sc_done_list(struct octeon_device *oct) |
|
{ |
|
struct octeon_response_list *done_sc_list, *zombie_sc_list; |
|
struct octeon_soft_command *sc; |
|
struct list_head *tmp, *tmp2; |
|
spinlock_t *sc_lists_lock; /* lock for response_list */ |
|
|
|
done_sc_list = &oct->response_list[OCTEON_DONE_SC_LIST]; |
|
zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST]; |
|
|
|
if (!atomic_read(&done_sc_list->pending_req_count)) |
|
return 0; |
|
|
|
sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock; |
|
|
|
spin_lock_bh(sc_lists_lock); |
|
|
|
list_for_each_safe(tmp, tmp2, &done_sc_list->head) { |
|
sc = list_entry(tmp, struct octeon_soft_command, node); |
|
|
|
if (READ_ONCE(sc->caller_is_done)) { |
|
list_del(&sc->node); |
|
atomic_dec(&done_sc_list->pending_req_count); |
|
|
|
if (*sc->status_word == COMPLETION_WORD_INIT) { |
|
/* timeout; move sc to zombie list */ |
|
list_add_tail(&sc->node, &zombie_sc_list->head); |
|
atomic_inc(&zombie_sc_list->pending_req_count); |
|
} else { |
|
octeon_free_soft_command(oct, sc); |
|
} |
|
} |
|
} |
|
|
|
spin_unlock_bh(sc_lists_lock); |
|
|
|
return 0; |
|
} |
|
|
|
int octeon_free_sc_zombie_list(struct octeon_device *oct) |
|
{ |
|
struct octeon_response_list *zombie_sc_list; |
|
struct octeon_soft_command *sc; |
|
struct list_head *tmp, *tmp2; |
|
spinlock_t *sc_lists_lock; /* lock for response_list */ |
|
|
|
zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST]; |
|
sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock; |
|
|
|
spin_lock_bh(sc_lists_lock); |
|
|
|
list_for_each_safe(tmp, tmp2, &zombie_sc_list->head) { |
|
list_del(tmp); |
|
atomic_dec(&zombie_sc_list->pending_req_count); |
|
sc = list_entry(tmp, struct octeon_soft_command, node); |
|
octeon_free_soft_command(oct, sc); |
|
} |
|
|
|
spin_unlock_bh(sc_lists_lock); |
|
|
|
return 0; |
|
} |
|
|
|
int octeon_free_sc_buffer_pool(struct octeon_device *oct) |
|
{ |
|
struct list_head *tmp, *tmp2; |
|
struct octeon_soft_command *sc; |
|
|
|
octeon_free_sc_zombie_list(oct); |
|
|
|
spin_lock_bh(&oct->sc_buf_pool.lock); |
|
|
|
list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) { |
|
list_del(tmp); |
|
|
|
sc = (struct octeon_soft_command *)tmp; |
|
|
|
lio_dma_free(oct, sc->size, sc, sc->dma_addr); |
|
} |
|
|
|
INIT_LIST_HEAD(&oct->sc_buf_pool.head); |
|
|
|
spin_unlock_bh(&oct->sc_buf_pool.lock); |
|
|
|
return 0; |
|
} |
|
|
|
struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct, |
|
u32 datasize, |
|
u32 rdatasize, |
|
u32 ctxsize) |
|
{ |
|
u64 dma_addr; |
|
u32 size; |
|
u32 offset = sizeof(struct octeon_soft_command); |
|
struct octeon_soft_command *sc = NULL; |
|
struct list_head *tmp; |
|
|
|
if (!rdatasize) |
|
rdatasize = 16; |
|
|
|
WARN_ON((offset + datasize + rdatasize + ctxsize) > |
|
SOFT_COMMAND_BUFFER_SIZE); |
|
|
|
spin_lock_bh(&oct->sc_buf_pool.lock); |
|
|
|
if (list_empty(&oct->sc_buf_pool.head)) { |
|
spin_unlock_bh(&oct->sc_buf_pool.lock); |
|
return NULL; |
|
} |
|
|
|
list_for_each(tmp, &oct->sc_buf_pool.head) |
|
break; |
|
|
|
list_del(tmp); |
|
|
|
atomic_inc(&oct->sc_buf_pool.alloc_buf_count); |
|
|
|
spin_unlock_bh(&oct->sc_buf_pool.lock); |
|
|
|
sc = (struct octeon_soft_command *)tmp; |
|
|
|
dma_addr = sc->dma_addr; |
|
size = sc->size; |
|
|
|
memset(sc, 0, sc->size); |
|
|
|
sc->dma_addr = dma_addr; |
|
sc->size = size; |
|
|
|
if (ctxsize) { |
|
sc->ctxptr = (u8 *)sc + offset; |
|
sc->ctxsize = ctxsize; |
|
} |
|
|
|
/* Start data at 128 byte boundary */ |
|
offset = (offset + ctxsize + 127) & 0xffffff80; |
|
|
|
if (datasize) { |
|
sc->virtdptr = (u8 *)sc + offset; |
|
sc->dmadptr = dma_addr + offset; |
|
sc->datasize = datasize; |
|
} |
|
|
|
/* Start rdata at 128 byte boundary */ |
|
offset = (offset + datasize + 127) & 0xffffff80; |
|
|
|
if (rdatasize) { |
|
WARN_ON(rdatasize < 16); |
|
sc->virtrptr = (u8 *)sc + offset; |
|
sc->dmarptr = dma_addr + offset; |
|
sc->rdatasize = rdatasize; |
|
sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8); |
|
} |
|
|
|
return sc; |
|
} |
|
|
|
void octeon_free_soft_command(struct octeon_device *oct, |
|
struct octeon_soft_command *sc) |
|
{ |
|
spin_lock_bh(&oct->sc_buf_pool.lock); |
|
|
|
list_add_tail(&sc->node, &oct->sc_buf_pool.head); |
|
|
|
atomic_dec(&oct->sc_buf_pool.alloc_buf_count); |
|
|
|
spin_unlock_bh(&oct->sc_buf_pool.lock); |
|
}
|
|
|