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920 lines
25 KiB
920 lines
25 KiB
/********************************************************************** |
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* Author: Cavium, Inc. |
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* |
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* Contact: [email protected] |
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* Please include "LiquidIO" in the subject. |
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* |
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* Copyright (c) 2003-2016 Cavium, Inc. |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more details. |
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***********************************************************************/ |
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/* |
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* @file octeon_console.c |
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*/ |
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#include <linux/moduleparam.h> |
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#include <linux/pci.h> |
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#include <linux/netdevice.h> |
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#include <linux/crc32.h> |
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#include "liquidio_common.h" |
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#include "octeon_droq.h" |
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#include "octeon_iq.h" |
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#include "response_manager.h" |
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#include "octeon_device.h" |
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#include "liquidio_image.h" |
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#include "octeon_mem_ops.h" |
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|
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static void octeon_remote_lock(void); |
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static void octeon_remote_unlock(void); |
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static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, |
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const char *name, |
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u32 flags); |
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static int octeon_console_read(struct octeon_device *oct, u32 console_num, |
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char *buffer, u32 buf_size); |
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|
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#define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR 0x0006c008 |
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#define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR 0x0006c004 |
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#define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR 0x0006c000 |
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#define BOOTLOADER_PCI_READ_DESC_ADDR 0x0006c100 |
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#define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN 248 |
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|
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#define OCTEON_PCI_IO_BUF_OWNER_OCTEON 0x00000001 |
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#define OCTEON_PCI_IO_BUF_OWNER_HOST 0x00000002 |
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|
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/** Can change without breaking ABI */ |
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#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64 |
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|
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/** minimum alignment of bootmem alloced blocks */ |
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#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull) |
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|
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/** CVMX bootmem descriptor major version */ |
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#define CVMX_BOOTMEM_DESC_MAJ_VER 3 |
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/* CVMX bootmem descriptor minor version */ |
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#define CVMX_BOOTMEM_DESC_MIN_VER 0 |
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|
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/* Current versions */ |
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#define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1 |
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#define OCTEON_PCI_CONSOLE_MINOR_VERSION 0 |
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#define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console" |
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#define OCTEON_CONSOLE_POLL_INTERVAL_MS 100 /* 10 times per second */ |
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|
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/* First three members of cvmx_bootmem_desc are left in original |
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* positions for backwards compatibility. |
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* Assumes big endian target |
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*/ |
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struct cvmx_bootmem_desc { |
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/** spinlock to control access to list */ |
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u32 lock; |
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|
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/** flags for indicating various conditions */ |
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u32 flags; |
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u64 head_addr; |
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/** incremented changed when incompatible changes made */ |
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u32 major_version; |
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/** incremented changed when compatible changes made, |
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* reset to zero when major incremented |
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*/ |
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u32 minor_version; |
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u64 app_data_addr; |
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u64 app_data_size; |
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/** number of elements in named blocks array */ |
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u32 nb_num_blocks; |
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|
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/** length of name array in bootmem blocks */ |
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u32 named_block_name_len; |
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|
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/** address of named memory block descriptors */ |
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u64 named_block_array_addr; |
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}; |
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|
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/* Structure that defines a single console. |
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* |
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* Note: when read_index == write_index, the buffer is empty. |
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* The actual usable size of each console is console_buf_size -1; |
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*/ |
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struct octeon_pci_console { |
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u64 input_base_addr; |
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u32 input_read_index; |
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u32 input_write_index; |
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u64 output_base_addr; |
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u32 output_read_index; |
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u32 output_write_index; |
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u32 lock; |
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u32 buf_size; |
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}; |
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|
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/* This is the main container structure that contains all the information |
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* about all PCI consoles. The address of this structure is passed to various |
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* routines that operation on PCI consoles. |
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*/ |
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struct octeon_pci_console_desc { |
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u32 major_version; |
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u32 minor_version; |
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u32 lock; |
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u32 flags; |
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u32 num_consoles; |
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u32 pad; |
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/* must be 64 bit aligned here... */ |
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/* Array of addresses of octeon_pci_console structures */ |
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u64 console_addr_array[]; |
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/* Implicit storage for console_addr_array */ |
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}; |
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/* |
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* This function is the implementation of the get macros defined |
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* for individual structure members. The argument are generated |
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* by the macros inorder to read only the needed memory. |
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* |
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* @param oct Pointer to current octeon device |
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* @param base 64bit physical address of the complete structure |
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* @param offset Offset from the beginning of the structure to the member being |
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* accessed. |
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* @param size Size of the structure member. |
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* |
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* @return Value of the structure member promoted into a u64. |
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*/ |
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static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct, |
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u64 base, |
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u32 offset, |
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u32 size) |
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{ |
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base = (1ull << 63) | (base + offset); |
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switch (size) { |
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case 4: |
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return octeon_read_device_mem32(oct, base); |
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case 8: |
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return octeon_read_device_mem64(oct, base); |
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default: |
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return 0; |
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} |
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} |
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/* |
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* This function retrieves the string name of a named block. It is |
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* more complicated than a simple memcpy() since the named block |
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* descriptor may not be directly accessible. |
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* |
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* @param addr Physical address of the named block descriptor |
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* @param str String to receive the named block string name |
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* @param len Length of the string buffer, which must match the length |
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* stored in the bootmem descriptor. |
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*/ |
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static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct, |
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u64 addr, |
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char *str, |
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u32 len) |
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{ |
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addr += offsetof(struct cvmx_bootmem_named_block_desc, name); |
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octeon_pci_read_core_mem(oct, addr, (u8 *)str, len); |
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str[len] = 0; |
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} |
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/* See header file for descriptions of functions */ |
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/* |
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* Check the version information on the bootmem descriptor |
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* |
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* @param exact_match |
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* Exact major version to check against. A zero means |
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* check that the version supports named blocks. |
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* |
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* @return Zero if the version is correct. Negative if the version is |
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* incorrect. Failures also cause a message to be displayed. |
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*/ |
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static int __cvmx_bootmem_check_version(struct octeon_device *oct, |
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u32 exact_match) |
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{ |
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u32 major_version; |
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u32 minor_version; |
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|
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if (!oct->bootmem_desc_addr) |
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oct->bootmem_desc_addr = |
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octeon_read_device_mem64(oct, |
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BOOTLOADER_PCI_READ_DESC_ADDR); |
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major_version = (u32)__cvmx_bootmem_desc_get( |
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oct, oct->bootmem_desc_addr, |
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offsetof(struct cvmx_bootmem_desc, major_version), |
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sizeof_field(struct cvmx_bootmem_desc, major_version)); |
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minor_version = (u32)__cvmx_bootmem_desc_get( |
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oct, oct->bootmem_desc_addr, |
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offsetof(struct cvmx_bootmem_desc, minor_version), |
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sizeof_field(struct cvmx_bootmem_desc, minor_version)); |
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dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__, |
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major_version); |
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if ((major_version > 3) || |
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(exact_match && major_version != exact_match)) { |
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dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n", |
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major_version, minor_version, |
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(long long)oct->bootmem_desc_addr); |
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return -1; |
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} else { |
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return 0; |
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} |
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} |
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static const struct cvmx_bootmem_named_block_desc |
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*__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct, |
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const char *name, u32 flags) |
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{ |
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struct cvmx_bootmem_named_block_desc *desc = |
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&oct->bootmem_named_block_desc; |
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u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags); |
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if (named_addr) { |
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desc->base_addr = __cvmx_bootmem_desc_get( |
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oct, named_addr, |
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offsetof(struct cvmx_bootmem_named_block_desc, |
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base_addr), |
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sizeof_field( |
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struct cvmx_bootmem_named_block_desc, |
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base_addr)); |
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desc->size = __cvmx_bootmem_desc_get(oct, named_addr, |
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offsetof(struct cvmx_bootmem_named_block_desc, |
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size), |
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sizeof_field( |
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struct cvmx_bootmem_named_block_desc, |
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size)); |
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strncpy(desc->name, name, sizeof(desc->name)); |
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desc->name[sizeof(desc->name) - 1] = 0; |
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return &oct->bootmem_named_block_desc; |
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} else { |
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return NULL; |
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} |
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} |
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static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct, |
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const char *name, |
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u32 flags) |
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{ |
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u64 result = 0; |
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if (!__cvmx_bootmem_check_version(oct, 3)) { |
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u32 i; |
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u64 named_block_array_addr = __cvmx_bootmem_desc_get( |
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oct, oct->bootmem_desc_addr, |
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offsetof(struct cvmx_bootmem_desc, |
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named_block_array_addr), |
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sizeof_field(struct cvmx_bootmem_desc, |
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named_block_array_addr)); |
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u32 num_blocks = (u32)__cvmx_bootmem_desc_get( |
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oct, oct->bootmem_desc_addr, |
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offsetof(struct cvmx_bootmem_desc, |
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nb_num_blocks), |
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sizeof_field(struct cvmx_bootmem_desc, |
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nb_num_blocks)); |
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u32 name_length = (u32)__cvmx_bootmem_desc_get( |
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oct, oct->bootmem_desc_addr, |
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offsetof(struct cvmx_bootmem_desc, |
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named_block_name_len), |
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sizeof_field(struct cvmx_bootmem_desc, |
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named_block_name_len)); |
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u64 named_addr = named_block_array_addr; |
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for (i = 0; i < num_blocks; i++) { |
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u64 named_size = __cvmx_bootmem_desc_get( |
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oct, named_addr, |
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offsetof( |
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struct cvmx_bootmem_named_block_desc, |
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size), |
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sizeof_field( |
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struct cvmx_bootmem_named_block_desc, |
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size)); |
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if (name && named_size) { |
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char *name_tmp = |
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kmalloc(name_length + 1, GFP_KERNEL); |
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if (!name_tmp) |
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break; |
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CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr, |
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name_tmp, |
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name_length); |
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if (!strncmp(name, name_tmp, name_length)) { |
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result = named_addr; |
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kfree(name_tmp); |
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break; |
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} |
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kfree(name_tmp); |
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} else if (!name && !named_size) { |
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result = named_addr; |
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break; |
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} |
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named_addr += |
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sizeof(struct cvmx_bootmem_named_block_desc); |
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} |
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} |
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return result; |
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} |
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/* |
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* Find a named block on the remote Octeon |
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* |
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* @param name Name of block to find |
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* @param base_addr Address the block is at (OUTPUT) |
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* @param size The size of the block (OUTPUT) |
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* |
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* @return Zero on success, One on failure. |
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*/ |
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static int octeon_named_block_find(struct octeon_device *oct, const char *name, |
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u64 *base_addr, u64 *size) |
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{ |
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const struct cvmx_bootmem_named_block_desc *named_block; |
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octeon_remote_lock(); |
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named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0); |
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octeon_remote_unlock(); |
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if (named_block) { |
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*base_addr = named_block->base_addr; |
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*size = named_block->size; |
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return 0; |
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} |
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return 1; |
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} |
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static void octeon_remote_lock(void) |
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{ |
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/* fill this in if any sharing is needed */ |
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} |
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|
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static void octeon_remote_unlock(void) |
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{ |
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/* fill this in if any sharing is needed */ |
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} |
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int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str, |
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u32 wait_hundredths) |
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{ |
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u32 len = (u32)strlen(cmd_str); |
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|
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dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str); |
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|
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if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) { |
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dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n", |
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BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1); |
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return -1; |
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} |
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|
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if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) { |
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dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n"); |
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return -1; |
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} |
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|
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/* Write command to bootloader */ |
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octeon_remote_lock(); |
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octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR, |
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(u8 *)cmd_str, len); |
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octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR, |
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len); |
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octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR, |
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OCTEON_PCI_IO_BUF_OWNER_OCTEON); |
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|
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/* Bootloader should accept command very quickly |
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* if it really was ready |
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*/ |
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if (octeon_wait_for_bootloader(oct, 200) != 0) { |
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octeon_remote_unlock(); |
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dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n"); |
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return -1; |
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} |
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octeon_remote_unlock(); |
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return 0; |
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} |
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int octeon_wait_for_bootloader(struct octeon_device *oct, |
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u32 wait_time_hundredths) |
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{ |
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dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n", |
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wait_time_hundredths); |
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|
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if (octeon_mem_access_ok(oct)) |
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return -1; |
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|
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while (wait_time_hundredths > 0 && |
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octeon_read_device_mem32(oct, |
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BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR) |
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!= OCTEON_PCI_IO_BUF_OWNER_HOST) { |
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if (--wait_time_hundredths <= 0) |
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return -1; |
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schedule_timeout_uninterruptible(HZ / 100); |
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} |
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return 0; |
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} |
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static void octeon_console_handle_result(struct octeon_device *oct, |
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size_t console_num) |
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{ |
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struct octeon_console *console; |
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|
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console = &oct->console[console_num]; |
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|
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console->waiting = 0; |
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} |
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|
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static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES]; |
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|
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static void output_console_line(struct octeon_device *oct, |
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struct octeon_console *console, |
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size_t console_num, |
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char *console_buffer, |
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s32 bytes_read) |
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{ |
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char *line; |
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s32 i; |
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size_t len; |
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line = console_buffer; |
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for (i = 0; i < bytes_read; i++) { |
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/* Output a line at a time, prefixed */ |
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if (console_buffer[i] == '\n') { |
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console_buffer[i] = '\0'; |
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/* We need to output 'line', prefaced by 'leftover'. |
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* However, it is possible we're being called to |
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* output 'leftover' by itself (in the case of nothing |
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* having been read from the console). |
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* |
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* To avoid duplication, check for this condition. |
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*/ |
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if (console->leftover[0] && |
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(line != console->leftover)) { |
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if (console->print) |
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(*console->print)(oct, (u32)console_num, |
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console->leftover, |
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line); |
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console->leftover[0] = '\0'; |
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} else { |
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if (console->print) |
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(*console->print)(oct, (u32)console_num, |
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line, NULL); |
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} |
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line = &console_buffer[i + 1]; |
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} |
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} |
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|
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/* Save off any leftovers */ |
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if (line != &console_buffer[bytes_read]) { |
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console_buffer[bytes_read] = '\0'; |
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len = strlen(console->leftover); |
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strncpy(&console->leftover[len], line, |
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sizeof(console->leftover) - len); |
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} |
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} |
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|
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static void check_console(struct work_struct *work) |
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{ |
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s32 bytes_read, tries, total_read; |
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size_t len; |
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struct octeon_console *console; |
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struct cavium_wk *wk = (struct cavium_wk *)work; |
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struct octeon_device *oct = (struct octeon_device *)wk->ctxptr; |
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u32 console_num = (u32)wk->ctxul; |
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u32 delay; |
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|
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console = &oct->console[console_num]; |
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tries = 0; |
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total_read = 0; |
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|
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do { |
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/* Take console output regardless of whether it will |
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* be logged |
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*/ |
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bytes_read = |
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octeon_console_read(oct, console_num, console_buffer, |
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sizeof(console_buffer) - 1); |
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if (bytes_read > 0) { |
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total_read += bytes_read; |
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if (console->waiting) |
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octeon_console_handle_result(oct, console_num); |
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if (console->print) { |
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output_console_line(oct, console, console_num, |
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console_buffer, bytes_read); |
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} |
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} else if (bytes_read < 0) { |
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dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n", |
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console_num, bytes_read); |
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} |
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|
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tries++; |
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} while ((bytes_read > 0) && (tries < 16)); |
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|
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/* If nothing is read after polling the console, |
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* output any leftovers if any |
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*/ |
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if (console->print && (total_read == 0) && |
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(console->leftover[0])) { |
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/* append '\n' as terminator for 'output_console_line' */ |
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len = strlen(console->leftover); |
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console->leftover[len] = '\n'; |
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output_console_line(oct, console, console_num, |
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console->leftover, (s32)(len + 1)); |
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console->leftover[0] = '\0'; |
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} |
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|
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delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; |
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|
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schedule_delayed_work(&wk->work, msecs_to_jiffies(delay)); |
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} |
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|
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int octeon_init_consoles(struct octeon_device *oct) |
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{ |
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int ret = 0; |
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u64 addr, size; |
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|
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ret = octeon_mem_access_ok(oct); |
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if (ret) { |
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dev_err(&oct->pci_dev->dev, "Memory access not okay'\n"); |
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return ret; |
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} |
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|
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ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr, |
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&size); |
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if (ret) { |
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dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n", |
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OCTEON_PCI_CONSOLE_BLOCK_NAME); |
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return ret; |
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} |
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|
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/* Dedicate one of Octeon's BAR1 index registers to create a static |
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* mapping to a region of Octeon DRAM that contains the PCI console |
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* named block. |
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*/ |
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oct->console_nb_info.bar1_index = BAR1_INDEX_STATIC_MAP; |
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oct->fn_list.bar1_idx_setup(oct, addr, oct->console_nb_info.bar1_index, |
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true); |
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oct->console_nb_info.dram_region_base = addr |
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& ~(OCTEON_BAR1_ENTRY_SIZE - 1ULL); |
|
|
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/* num_consoles > 0, is an indication that the consoles |
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* are accessible |
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*/ |
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oct->num_consoles = octeon_read_device_mem32(oct, |
|
addr + offsetof(struct octeon_pci_console_desc, |
|
num_consoles)); |
|
oct->console_desc_addr = addr; |
|
|
|
dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n", |
|
oct->num_consoles); |
|
|
|
return ret; |
|
} |
|
|
|
static void octeon_get_uboot_version(struct octeon_device *oct) |
|
{ |
|
s32 bytes_read, tries, total_read; |
|
struct octeon_console *console; |
|
u32 console_num = 0; |
|
char *uboot_ver; |
|
char *buf; |
|
char *p; |
|
|
|
#define OCTEON_UBOOT_VER_BUF_SIZE 512 |
|
buf = kmalloc(OCTEON_UBOOT_VER_BUF_SIZE, GFP_KERNEL); |
|
if (!buf) |
|
return; |
|
|
|
if (octeon_console_send_cmd(oct, "setenv stdout pci\n", 50)) { |
|
kfree(buf); |
|
return; |
|
} |
|
|
|
if (octeon_console_send_cmd(oct, "version\n", 1)) { |
|
kfree(buf); |
|
return; |
|
} |
|
|
|
console = &oct->console[console_num]; |
|
tries = 0; |
|
total_read = 0; |
|
|
|
do { |
|
/* Take console output regardless of whether it will |
|
* be logged |
|
*/ |
|
bytes_read = |
|
octeon_console_read(oct, |
|
console_num, buf + total_read, |
|
OCTEON_UBOOT_VER_BUF_SIZE - 1 - |
|
total_read); |
|
if (bytes_read > 0) { |
|
buf[bytes_read] = '\0'; |
|
|
|
total_read += bytes_read; |
|
if (console->waiting) |
|
octeon_console_handle_result(oct, console_num); |
|
} else if (bytes_read < 0) { |
|
dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n", |
|
console_num, bytes_read); |
|
} |
|
|
|
tries++; |
|
} while ((bytes_read > 0) && (tries < 16)); |
|
|
|
/* If nothing is read after polling the console, |
|
* output any leftovers if any |
|
*/ |
|
if ((total_read == 0) && (console->leftover[0])) { |
|
dev_dbg(&oct->pci_dev->dev, "%u: %s\n", |
|
console_num, console->leftover); |
|
console->leftover[0] = '\0'; |
|
} |
|
|
|
buf[OCTEON_UBOOT_VER_BUF_SIZE - 1] = '\0'; |
|
|
|
uboot_ver = strstr(buf, "U-Boot"); |
|
if (uboot_ver) { |
|
p = strstr(uboot_ver, "mips"); |
|
if (p) { |
|
p--; |
|
*p = '\0'; |
|
dev_info(&oct->pci_dev->dev, "%s\n", uboot_ver); |
|
} |
|
} |
|
|
|
kfree(buf); |
|
octeon_console_send_cmd(oct, "setenv stdout serial\n", 50); |
|
} |
|
|
|
int octeon_add_console(struct octeon_device *oct, u32 console_num, |
|
char *dbg_enb) |
|
{ |
|
int ret = 0; |
|
u32 delay; |
|
u64 coreaddr; |
|
struct delayed_work *work; |
|
struct octeon_console *console; |
|
|
|
if (console_num >= oct->num_consoles) { |
|
dev_err(&oct->pci_dev->dev, |
|
"trying to read from console number %d when only 0 to %d exist\n", |
|
console_num, oct->num_consoles); |
|
} else { |
|
console = &oct->console[console_num]; |
|
|
|
console->waiting = 0; |
|
|
|
coreaddr = oct->console_desc_addr + console_num * 8 + |
|
offsetof(struct octeon_pci_console_desc, |
|
console_addr_array); |
|
console->addr = octeon_read_device_mem64(oct, coreaddr); |
|
coreaddr = console->addr + offsetof(struct octeon_pci_console, |
|
buf_size); |
|
console->buffer_size = octeon_read_device_mem32(oct, coreaddr); |
|
coreaddr = console->addr + offsetof(struct octeon_pci_console, |
|
input_base_addr); |
|
console->input_base_addr = |
|
octeon_read_device_mem64(oct, coreaddr); |
|
coreaddr = console->addr + offsetof(struct octeon_pci_console, |
|
output_base_addr); |
|
console->output_base_addr = |
|
octeon_read_device_mem64(oct, coreaddr); |
|
console->leftover[0] = '\0'; |
|
|
|
work = &oct->console_poll_work[console_num].work; |
|
|
|
octeon_get_uboot_version(oct); |
|
|
|
INIT_DELAYED_WORK(work, check_console); |
|
oct->console_poll_work[console_num].ctxptr = (void *)oct; |
|
oct->console_poll_work[console_num].ctxul = console_num; |
|
delay = OCTEON_CONSOLE_POLL_INTERVAL_MS; |
|
schedule_delayed_work(work, msecs_to_jiffies(delay)); |
|
|
|
/* an empty string means use default debug console enablement */ |
|
if (dbg_enb && !dbg_enb[0]) |
|
dbg_enb = "setenv pci_console_active 1"; |
|
if (dbg_enb) |
|
ret = octeon_console_send_cmd(oct, dbg_enb, 2000); |
|
|
|
console->active = 1; |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
/* |
|
* Removes all consoles |
|
* |
|
* @param oct octeon device |
|
*/ |
|
void octeon_remove_consoles(struct octeon_device *oct) |
|
{ |
|
u32 i; |
|
struct octeon_console *console; |
|
|
|
for (i = 0; i < oct->num_consoles; i++) { |
|
console = &oct->console[i]; |
|
|
|
if (!console->active) |
|
continue; |
|
|
|
cancel_delayed_work_sync(&oct->console_poll_work[i]. |
|
work); |
|
console->addr = 0; |
|
console->buffer_size = 0; |
|
console->input_base_addr = 0; |
|
console->output_base_addr = 0; |
|
} |
|
|
|
oct->num_consoles = 0; |
|
} |
|
|
|
static inline int octeon_console_free_bytes(u32 buffer_size, |
|
u32 wr_idx, |
|
u32 rd_idx) |
|
{ |
|
if (rd_idx >= buffer_size || wr_idx >= buffer_size) |
|
return -1; |
|
|
|
return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size; |
|
} |
|
|
|
static inline int octeon_console_avail_bytes(u32 buffer_size, |
|
u32 wr_idx, |
|
u32 rd_idx) |
|
{ |
|
if (rd_idx >= buffer_size || wr_idx >= buffer_size) |
|
return -1; |
|
|
|
return buffer_size - 1 - |
|
octeon_console_free_bytes(buffer_size, wr_idx, rd_idx); |
|
} |
|
|
|
static int octeon_console_read(struct octeon_device *oct, u32 console_num, |
|
char *buffer, u32 buf_size) |
|
{ |
|
int bytes_to_read; |
|
u32 rd_idx, wr_idx; |
|
struct octeon_console *console; |
|
|
|
if (console_num >= oct->num_consoles) { |
|
dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n", |
|
console_num); |
|
return 0; |
|
} |
|
|
|
console = &oct->console[console_num]; |
|
|
|
/* Check to see if any data is available. |
|
* Maybe optimize this with 64-bit read. |
|
*/ |
|
rd_idx = octeon_read_device_mem32(oct, console->addr + |
|
offsetof(struct octeon_pci_console, output_read_index)); |
|
wr_idx = octeon_read_device_mem32(oct, console->addr + |
|
offsetof(struct octeon_pci_console, output_write_index)); |
|
|
|
bytes_to_read = octeon_console_avail_bytes(console->buffer_size, |
|
wr_idx, rd_idx); |
|
if (bytes_to_read <= 0) |
|
return bytes_to_read; |
|
|
|
bytes_to_read = min_t(s32, bytes_to_read, buf_size); |
|
|
|
/* Check to see if what we want to read is not contiguous, and limit |
|
* ourselves to the contiguous block |
|
*/ |
|
if (rd_idx + bytes_to_read >= console->buffer_size) |
|
bytes_to_read = console->buffer_size - rd_idx; |
|
|
|
octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx, |
|
(u8 *)buffer, bytes_to_read); |
|
octeon_write_device_mem32(oct, console->addr + |
|
offsetof(struct octeon_pci_console, |
|
output_read_index), |
|
(rd_idx + bytes_to_read) % |
|
console->buffer_size); |
|
|
|
return bytes_to_read; |
|
} |
|
|
|
#define FBUF_SIZE (4 * 1024 * 1024) |
|
#define MAX_BOOTTIME_SIZE 80 |
|
|
|
int octeon_download_firmware(struct octeon_device *oct, const u8 *data, |
|
size_t size) |
|
{ |
|
struct octeon_firmware_file_header *h; |
|
char boottime[MAX_BOOTTIME_SIZE]; |
|
struct timespec64 ts; |
|
u32 crc32_result; |
|
u64 load_addr; |
|
u32 image_len; |
|
int ret = 0; |
|
u32 i, rem; |
|
|
|
if (size < sizeof(struct octeon_firmware_file_header)) { |
|
dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n", |
|
(u32)size, |
|
(u32)sizeof(struct octeon_firmware_file_header)); |
|
return -EINVAL; |
|
} |
|
|
|
h = (struct octeon_firmware_file_header *)data; |
|
|
|
if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) { |
|
dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n"); |
|
return -EINVAL; |
|
} |
|
|
|
crc32_result = crc32((unsigned int)~0, data, |
|
sizeof(struct octeon_firmware_file_header) - |
|
sizeof(u32)) ^ ~0U; |
|
if (crc32_result != be32_to_cpu(h->crc32)) { |
|
dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n", |
|
crc32_result, be32_to_cpu(h->crc32)); |
|
return -EINVAL; |
|
} |
|
|
|
if (memcmp(LIQUIDIO_BASE_VERSION, h->version, |
|
strlen(LIQUIDIO_BASE_VERSION))) { |
|
dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s.x, got %s.\n", |
|
LIQUIDIO_BASE_VERSION, |
|
h->version); |
|
return -EINVAL; |
|
} |
|
|
|
if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) { |
|
dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n", |
|
be32_to_cpu(h->num_images)); |
|
return -EINVAL; |
|
} |
|
|
|
dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version); |
|
snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s", |
|
h->version); |
|
|
|
data += sizeof(struct octeon_firmware_file_header); |
|
|
|
dev_info(&oct->pci_dev->dev, "%s: Loading %d images\n", __func__, |
|
be32_to_cpu(h->num_images)); |
|
/* load all images */ |
|
for (i = 0; i < be32_to_cpu(h->num_images); i++) { |
|
load_addr = be64_to_cpu(h->desc[i].addr); |
|
image_len = be32_to_cpu(h->desc[i].len); |
|
|
|
dev_info(&oct->pci_dev->dev, "Loading firmware %d at %llx\n", |
|
image_len, load_addr); |
|
|
|
/* Write in 4MB chunks*/ |
|
rem = image_len; |
|
|
|
while (rem) { |
|
if (rem < FBUF_SIZE) |
|
size = rem; |
|
else |
|
size = FBUF_SIZE; |
|
|
|
/* download the image */ |
|
octeon_pci_write_core_mem(oct, load_addr, data, (u32)size); |
|
|
|
data += size; |
|
rem -= (u32)size; |
|
load_addr += size; |
|
} |
|
} |
|
|
|
/* Pass date and time information to NIC at the time of loading |
|
* firmware and periodically update the host time to NIC firmware. |
|
* This is to make NIC firmware use the same time reference as Host, |
|
* so that it is easy to correlate logs from firmware and host for |
|
* debugging. |
|
* |
|
* Octeon always uses UTC time. so timezone information is not sent. |
|
*/ |
|
ktime_get_real_ts64(&ts); |
|
ret = snprintf(boottime, MAX_BOOTTIME_SIZE, |
|
" time_sec=%lld time_nsec=%ld", |
|
(s64)ts.tv_sec, ts.tv_nsec); |
|
if ((sizeof(h->bootcmd) - strnlen(h->bootcmd, sizeof(h->bootcmd))) < |
|
ret) { |
|
dev_err(&oct->pci_dev->dev, "Boot command buffer too small\n"); |
|
return -EINVAL; |
|
} |
|
strncat(h->bootcmd, boottime, |
|
sizeof(h->bootcmd) - strnlen(h->bootcmd, sizeof(h->bootcmd))); |
|
|
|
dev_info(&oct->pci_dev->dev, "Writing boot command: %s\n", |
|
h->bootcmd); |
|
|
|
/* Invoke the bootcmd */ |
|
ret = octeon_console_send_cmd(oct, h->bootcmd, 50); |
|
if (ret) |
|
dev_info(&oct->pci_dev->dev, "Boot command send failed\n"); |
|
|
|
return ret; |
|
}
|
|
|