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704 lines
20 KiB
704 lines
20 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2014-2020 Broadcom |
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*/ |
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#ifndef __BCMGENET_H__ |
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#define __BCMGENET_H__ |
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#include <linux/skbuff.h> |
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#include <linux/netdevice.h> |
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#include <linux/spinlock.h> |
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#include <linux/clk.h> |
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#include <linux/mii.h> |
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#include <linux/if_vlan.h> |
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#include <linux/phy.h> |
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#include <linux/dim.h> |
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#include <linux/ethtool.h> |
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#include "../unimac.h" |
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/* total number of Buffer Descriptors, same for Rx/Tx */ |
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#define TOTAL_DESC 256 |
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/* which ring is descriptor based */ |
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#define DESC_INDEX 16 |
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/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. |
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* 1536 is multiple of 256 bytes |
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*/ |
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#define ENET_BRCM_TAG_LEN 6 |
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#define ENET_PAD 8 |
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#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ |
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ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) |
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#define DMA_MAX_BURST_LENGTH 0x08 |
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/* misc. configuration */ |
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#define MAX_NUM_OF_FS_RULES 16 |
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#define CLEAR_ALL_HFB 0xFF |
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#define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) |
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#define DMA_FC_THRESH_LO 5 |
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/* 64B receive/transmit status block */ |
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struct status_64 { |
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u32 length_status; /* length and peripheral status */ |
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u32 ext_status; /* Extended status*/ |
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u32 rx_csum; /* partial rx checksum */ |
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u32 unused1[9]; /* unused */ |
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u32 tx_csum_info; /* Tx checksum info. */ |
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u32 unused2[3]; /* unused */ |
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}; |
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/* Rx status bits */ |
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#define STATUS_RX_EXT_MASK 0x1FFFFF |
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#define STATUS_RX_CSUM_MASK 0xFFFF |
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#define STATUS_RX_CSUM_OK 0x10000 |
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#define STATUS_RX_CSUM_FR 0x20000 |
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#define STATUS_RX_PROTO_TCP 0 |
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#define STATUS_RX_PROTO_UDP 1 |
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#define STATUS_RX_PROTO_ICMP 2 |
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#define STATUS_RX_PROTO_OTHER 3 |
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#define STATUS_RX_PROTO_MASK 3 |
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#define STATUS_RX_PROTO_SHIFT 18 |
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#define STATUS_FILTER_INDEX_MASK 0xFFFF |
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/* Tx status bits */ |
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#define STATUS_TX_CSUM_START_MASK 0X7FFF |
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#define STATUS_TX_CSUM_START_SHIFT 16 |
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#define STATUS_TX_CSUM_PROTO_UDP 0x8000 |
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#define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF |
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#define STATUS_TX_CSUM_LV 0x80000000 |
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/* DMA Descriptor */ |
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#define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ |
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#define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ |
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#define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ |
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/* Rx/Tx common counter group */ |
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struct bcmgenet_pkt_counters { |
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u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ |
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u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ |
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u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ |
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u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ |
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u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ |
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u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ |
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u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ |
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u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ |
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u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ |
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u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ |
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}; |
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/* RSV, Receive Status Vector */ |
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struct bcmgenet_rx_counters { |
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struct bcmgenet_pkt_counters pkt_cnt; |
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u32 pkt; /* RO (0x428) Received pkt count*/ |
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u32 bytes; /* RO Received byte count */ |
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u32 mca; /* RO # of Received multicast pkt */ |
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u32 bca; /* RO # of Receive broadcast pkt */ |
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u32 fcs; /* RO # of Received FCS error */ |
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u32 cf; /* RO # of Received control frame pkt*/ |
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u32 pf; /* RO # of Received pause frame pkt */ |
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u32 uo; /* RO # of unknown op code pkt */ |
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u32 aln; /* RO # of alignment error count */ |
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u32 flr; /* RO # of frame length out of range count */ |
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u32 cde; /* RO # of code error pkt */ |
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u32 fcr; /* RO # of carrier sense error pkt */ |
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u32 ovr; /* RO # of oversize pkt*/ |
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u32 jbr; /* RO # of jabber count */ |
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u32 mtue; /* RO # of MTU error pkt*/ |
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u32 pok; /* RO # of Received good pkt */ |
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u32 uc; /* RO # of unicast pkt */ |
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u32 ppp; /* RO # of PPP pkt */ |
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u32 rcrc; /* RO (0x470),# of CRC match pkt */ |
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}; |
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/* TSV, Transmit Status Vector */ |
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struct bcmgenet_tx_counters { |
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struct bcmgenet_pkt_counters pkt_cnt; |
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u32 pkts; /* RO (0x4a8) Transmited pkt */ |
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u32 mca; /* RO # of xmited multicast pkt */ |
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u32 bca; /* RO # of xmited broadcast pkt */ |
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u32 pf; /* RO # of xmited pause frame count */ |
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u32 cf; /* RO # of xmited control frame count */ |
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u32 fcs; /* RO # of xmited FCS error count */ |
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u32 ovr; /* RO # of xmited oversize pkt */ |
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u32 drf; /* RO # of xmited deferral pkt */ |
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u32 edf; /* RO # of xmited Excessive deferral pkt*/ |
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u32 scl; /* RO # of xmited single collision pkt */ |
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u32 mcl; /* RO # of xmited multiple collision pkt*/ |
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u32 lcl; /* RO # of xmited late collision pkt */ |
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u32 ecl; /* RO # of xmited excessive collision pkt*/ |
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u32 frg; /* RO # of xmited fragments pkt*/ |
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u32 ncl; /* RO # of xmited total collision count */ |
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u32 jbr; /* RO # of xmited jabber count*/ |
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u32 bytes; /* RO # of xmited byte count */ |
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u32 pok; /* RO # of xmited good pkt */ |
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u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ |
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}; |
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struct bcmgenet_mib_counters { |
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struct bcmgenet_rx_counters rx; |
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struct bcmgenet_tx_counters tx; |
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u32 rx_runt_cnt; |
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u32 rx_runt_fcs; |
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u32 rx_runt_fcs_align; |
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u32 rx_runt_bytes; |
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u32 rbuf_ovflow_cnt; |
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u32 rbuf_err_cnt; |
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u32 mdf_err_cnt; |
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u32 alloc_rx_buff_failed; |
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u32 rx_dma_failed; |
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u32 tx_dma_failed; |
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u32 tx_realloc_tsb; |
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u32 tx_realloc_tsb_failed; |
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}; |
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#define UMAC_MIB_START 0x400 |
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#define UMAC_MDIO_CMD 0x614 |
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#define MDIO_START_BUSY (1 << 29) |
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#define MDIO_READ_FAIL (1 << 28) |
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#define MDIO_RD (2 << 26) |
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#define MDIO_WR (1 << 26) |
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#define MDIO_PMD_SHIFT 21 |
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#define MDIO_PMD_MASK 0x1F |
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#define MDIO_REG_SHIFT 16 |
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#define MDIO_REG_MASK 0x1F |
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#define UMAC_RBUF_OVFL_CNT_V1 0x61C |
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#define RBUF_OVFL_CNT_V2 0x80 |
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#define RBUF_OVFL_CNT_V3PLUS 0x94 |
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#define UMAC_MPD_CTRL 0x620 |
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#define MPD_EN (1 << 0) |
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#define MPD_PW_EN (1 << 27) |
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#define MPD_MSEQ_LEN_SHIFT 16 |
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#define MPD_MSEQ_LEN_MASK 0xFF |
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#define UMAC_MPD_PW_MS 0x624 |
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#define UMAC_MPD_PW_LS 0x628 |
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#define UMAC_RBUF_ERR_CNT_V1 0x634 |
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#define RBUF_ERR_CNT_V2 0x84 |
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#define RBUF_ERR_CNT_V3PLUS 0x98 |
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#define UMAC_MDF_ERR_CNT 0x638 |
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#define UMAC_MDF_CTRL 0x650 |
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#define UMAC_MDF_ADDR 0x654 |
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#define UMAC_MIB_CTRL 0x580 |
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#define MIB_RESET_RX (1 << 0) |
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#define MIB_RESET_RUNT (1 << 1) |
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#define MIB_RESET_TX (1 << 2) |
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#define RBUF_CTRL 0x00 |
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#define RBUF_64B_EN (1 << 0) |
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#define RBUF_ALIGN_2B (1 << 1) |
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#define RBUF_BAD_DIS (1 << 2) |
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#define RBUF_STATUS 0x0C |
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#define RBUF_STATUS_WOL (1 << 0) |
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#define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) |
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#define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) |
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#define RBUF_CHK_CTRL 0x14 |
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#define RBUF_RXCHK_EN (1 << 0) |
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#define RBUF_SKIP_FCS (1 << 4) |
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#define RBUF_L3_PARSE_DIS (1 << 5) |
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#define RBUF_ENERGY_CTRL 0x9c |
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#define RBUF_EEE_EN (1 << 0) |
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#define RBUF_PM_EN (1 << 1) |
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#define RBUF_TBUF_SIZE_CTRL 0xb4 |
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#define RBUF_HFB_CTRL_V1 0x38 |
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#define RBUF_HFB_FILTER_EN_SHIFT 16 |
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#define RBUF_HFB_FILTER_EN_MASK 0xffff0000 |
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#define RBUF_HFB_EN (1 << 0) |
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#define RBUF_HFB_256B (1 << 1) |
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#define RBUF_ACPI_EN (1 << 2) |
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#define RBUF_HFB_LEN_V1 0x3C |
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#define RBUF_FLTR_LEN_MASK 0xFF |
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#define RBUF_FLTR_LEN_SHIFT 8 |
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#define TBUF_CTRL 0x00 |
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#define TBUF_64B_EN (1 << 0) |
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#define TBUF_BP_MC 0x0C |
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#define TBUF_ENERGY_CTRL 0x14 |
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#define TBUF_EEE_EN (1 << 0) |
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#define TBUF_PM_EN (1 << 1) |
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#define TBUF_CTRL_V1 0x80 |
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#define TBUF_BP_MC_V1 0xA0 |
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#define HFB_CTRL 0x00 |
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#define HFB_FLT_ENABLE_V3PLUS 0x04 |
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#define HFB_FLT_LEN_V2 0x04 |
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#define HFB_FLT_LEN_V3PLUS 0x1C |
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/* uniMac intrl2 registers */ |
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#define INTRL2_CPU_STAT 0x00 |
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#define INTRL2_CPU_SET 0x04 |
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#define INTRL2_CPU_CLEAR 0x08 |
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#define INTRL2_CPU_MASK_STATUS 0x0C |
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#define INTRL2_CPU_MASK_SET 0x10 |
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#define INTRL2_CPU_MASK_CLEAR 0x14 |
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/* INTRL2 instance 0 definitions */ |
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#define UMAC_IRQ_SCB (1 << 0) |
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#define UMAC_IRQ_EPHY (1 << 1) |
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#define UMAC_IRQ_PHY_DET_R (1 << 2) |
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#define UMAC_IRQ_PHY_DET_F (1 << 3) |
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#define UMAC_IRQ_LINK_UP (1 << 4) |
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#define UMAC_IRQ_LINK_DOWN (1 << 5) |
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#define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) |
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#define UMAC_IRQ_UMAC (1 << 6) |
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#define UMAC_IRQ_UMAC_TSV (1 << 7) |
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#define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) |
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#define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) |
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#define UMAC_IRQ_HFB_SM (1 << 10) |
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#define UMAC_IRQ_HFB_MM (1 << 11) |
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#define UMAC_IRQ_MPD_R (1 << 12) |
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#define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \ |
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UMAC_IRQ_MPD_R) |
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#define UMAC_IRQ_RXDMA_MBDONE (1 << 13) |
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#define UMAC_IRQ_RXDMA_PDONE (1 << 14) |
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#define UMAC_IRQ_RXDMA_BDONE (1 << 15) |
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#define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE |
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#define UMAC_IRQ_TXDMA_MBDONE (1 << 16) |
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#define UMAC_IRQ_TXDMA_PDONE (1 << 17) |
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#define UMAC_IRQ_TXDMA_BDONE (1 << 18) |
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#define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE |
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/* Only valid for GENETv3+ */ |
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#define UMAC_IRQ_MDIO_DONE (1 << 23) |
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#define UMAC_IRQ_MDIO_ERROR (1 << 24) |
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/* INTRL2 instance 1 definitions */ |
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#define UMAC_IRQ1_TX_INTR_MASK 0xFFFF |
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#define UMAC_IRQ1_RX_INTR_MASK 0xFFFF |
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#define UMAC_IRQ1_RX_INTR_SHIFT 16 |
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/* Register block offsets */ |
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#define GENET_SYS_OFF 0x0000 |
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#define GENET_GR_BRIDGE_OFF 0x0040 |
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#define GENET_EXT_OFF 0x0080 |
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#define GENET_INTRL2_0_OFF 0x0200 |
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#define GENET_INTRL2_1_OFF 0x0240 |
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#define GENET_RBUF_OFF 0x0300 |
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#define GENET_UMAC_OFF 0x0800 |
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/* SYS block offsets and register definitions */ |
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#define SYS_REV_CTRL 0x00 |
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#define SYS_PORT_CTRL 0x04 |
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#define PORT_MODE_INT_EPHY 0 |
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#define PORT_MODE_INT_GPHY 1 |
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#define PORT_MODE_EXT_EPHY 2 |
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#define PORT_MODE_EXT_GPHY 3 |
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#define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) |
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#define PORT_MODE_EXT_RVMII_50 4 |
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#define LED_ACT_SOURCE_MAC (1 << 9) |
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#define SYS_RBUF_FLUSH_CTRL 0x08 |
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#define SYS_TBUF_FLUSH_CTRL 0x0C |
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#define RBUF_FLUSH_CTRL_V1 0x04 |
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/* Ext block register offsets and definitions */ |
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#define EXT_EXT_PWR_MGMT 0x00 |
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#define EXT_PWR_DOWN_BIAS (1 << 0) |
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#define EXT_PWR_DOWN_DLL (1 << 1) |
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#define EXT_PWR_DOWN_PHY (1 << 2) |
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#define EXT_PWR_DN_EN_LD (1 << 3) |
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#define EXT_ENERGY_DET (1 << 4) |
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#define EXT_IDDQ_FROM_PHY (1 << 5) |
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#define EXT_IDDQ_GLBL_PWR (1 << 7) |
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#define EXT_PHY_RESET (1 << 8) |
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#define EXT_ENERGY_DET_MASK (1 << 12) |
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#define EXT_PWR_DOWN_PHY_TX (1 << 16) |
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#define EXT_PWR_DOWN_PHY_RX (1 << 17) |
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#define EXT_PWR_DOWN_PHY_SD (1 << 18) |
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#define EXT_PWR_DOWN_PHY_RD (1 << 19) |
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#define EXT_PWR_DOWN_PHY_EN (1 << 20) |
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#define EXT_RGMII_OOB_CTRL 0x0C |
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#define RGMII_MODE_EN_V123 (1 << 0) |
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#define RGMII_LINK (1 << 4) |
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#define OOB_DISABLE (1 << 5) |
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#define RGMII_MODE_EN (1 << 6) |
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#define ID_MODE_DIS (1 << 16) |
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#define EXT_GPHY_CTRL 0x1C |
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#define EXT_CFG_IDDQ_BIAS (1 << 0) |
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#define EXT_CFG_PWR_DOWN (1 << 1) |
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#define EXT_CK25_DIS (1 << 4) |
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#define EXT_GPHY_RESET (1 << 5) |
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/* DMA rings size */ |
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#define DMA_RING_SIZE (0x40) |
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#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) |
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/* DMA registers common definitions */ |
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#define DMA_RW_POINTER_MASK 0x1FF |
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#define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF |
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#define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 |
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#define DMA_BUFFER_DONE_CNT_MASK 0xFFFF |
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#define DMA_BUFFER_DONE_CNT_SHIFT 16 |
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#define DMA_P_INDEX_MASK 0xFFFF |
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#define DMA_C_INDEX_MASK 0xFFFF |
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/* DMA ring size register */ |
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#define DMA_RING_SIZE_MASK 0xFFFF |
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#define DMA_RING_SIZE_SHIFT 16 |
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#define DMA_RING_BUFFER_SIZE_MASK 0xFFFF |
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/* DMA interrupt threshold register */ |
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#define DMA_INTR_THRESHOLD_MASK 0x01FF |
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/* DMA XON/XOFF register */ |
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#define DMA_XON_THREHOLD_MASK 0xFFFF |
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#define DMA_XOFF_THRESHOLD_MASK 0xFFFF |
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#define DMA_XOFF_THRESHOLD_SHIFT 16 |
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/* DMA flow period register */ |
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#define DMA_FLOW_PERIOD_MASK 0xFFFF |
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#define DMA_MAX_PKT_SIZE_MASK 0xFFFF |
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#define DMA_MAX_PKT_SIZE_SHIFT 16 |
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/* DMA control register */ |
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#define DMA_EN (1 << 0) |
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#define DMA_RING_BUF_EN_SHIFT 0x01 |
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#define DMA_RING_BUF_EN_MASK 0xFFFF |
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#define DMA_TSB_SWAP_EN (1 << 20) |
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/* DMA status register */ |
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#define DMA_DISABLED (1 << 0) |
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#define DMA_DESC_RAM_INIT_BUSY (1 << 1) |
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/* DMA SCB burst size register */ |
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#define DMA_SCB_BURST_SIZE_MASK 0x1F |
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/* DMA activity vector register */ |
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#define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF |
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/* DMA backpressure mask register */ |
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#define DMA_BACKPRESSURE_MASK 0x1FFFF |
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#define DMA_PFC_ENABLE (1 << 31) |
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/* DMA backpressure status register */ |
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#define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF |
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/* DMA override register */ |
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#define DMA_LITTLE_ENDIAN_MODE (1 << 0) |
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#define DMA_REGISTER_MODE (1 << 1) |
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/* DMA timeout register */ |
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#define DMA_TIMEOUT_MASK 0xFFFF |
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#define DMA_TIMEOUT_VAL 5000 /* micro seconds */ |
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/* TDMA rate limiting control register */ |
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#define DMA_RATE_LIMIT_EN_MASK 0xFFFF |
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/* TDMA arbitration control register */ |
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#define DMA_ARBITER_MODE_MASK 0x03 |
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#define DMA_RING_BUF_PRIORITY_MASK 0x1F |
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#define DMA_RING_BUF_PRIORITY_SHIFT 5 |
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#define DMA_PRIO_REG_INDEX(q) ((q) / 6) |
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#define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) |
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#define DMA_RATE_ADJ_MASK 0xFF |
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/* Tx/Rx Dma Descriptor common bits*/ |
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#define DMA_BUFLENGTH_MASK 0x0fff |
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#define DMA_BUFLENGTH_SHIFT 16 |
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#define DMA_OWN 0x8000 |
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#define DMA_EOP 0x4000 |
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#define DMA_SOP 0x2000 |
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#define DMA_WRAP 0x1000 |
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/* Tx specific Dma descriptor bits */ |
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#define DMA_TX_UNDERRUN 0x0200 |
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#define DMA_TX_APPEND_CRC 0x0040 |
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#define DMA_TX_OW_CRC 0x0020 |
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#define DMA_TX_DO_CSUM 0x0010 |
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#define DMA_TX_QTAG_SHIFT 7 |
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/* Rx Specific Dma descriptor bits */ |
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#define DMA_RX_CHK_V3PLUS 0x8000 |
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#define DMA_RX_CHK_V12 0x1000 |
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#define DMA_RX_BRDCAST 0x0040 |
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#define DMA_RX_MULT 0x0020 |
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#define DMA_RX_LG 0x0010 |
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#define DMA_RX_NO 0x0008 |
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#define DMA_RX_RXER 0x0004 |
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#define DMA_RX_CRC_ERROR 0x0002 |
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#define DMA_RX_OV 0x0001 |
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#define DMA_RX_FI_MASK 0x001F |
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#define DMA_RX_FI_SHIFT 0x0007 |
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#define DMA_DESC_ALLOC_MASK 0x00FF |
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#define DMA_ARBITER_RR 0x00 |
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#define DMA_ARBITER_WRR 0x01 |
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#define DMA_ARBITER_SP 0x02 |
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struct enet_cb { |
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struct sk_buff *skb; |
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void __iomem *bd_addr; |
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DEFINE_DMA_UNMAP_ADDR(dma_addr); |
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DEFINE_DMA_UNMAP_LEN(dma_len); |
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}; |
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/* power management mode */ |
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enum bcmgenet_power_mode { |
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GENET_POWER_CABLE_SENSE = 0, |
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GENET_POWER_PASSIVE, |
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GENET_POWER_WOL_MAGIC, |
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}; |
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struct bcmgenet_priv; |
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/* We support both runtime GENET detection and compile-time |
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* to optimize code-paths for a given hardware |
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*/ |
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enum bcmgenet_version { |
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GENET_V1 = 1, |
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GENET_V2, |
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GENET_V3, |
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GENET_V4, |
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GENET_V5 |
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}; |
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#define GENET_IS_V1(p) ((p)->version == GENET_V1) |
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#define GENET_IS_V2(p) ((p)->version == GENET_V2) |
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#define GENET_IS_V3(p) ((p)->version == GENET_V3) |
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#define GENET_IS_V4(p) ((p)->version == GENET_V4) |
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#define GENET_IS_V5(p) ((p)->version == GENET_V5) |
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/* Hardware flags */ |
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#define GENET_HAS_40BITS (1 << 0) |
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#define GENET_HAS_EXT (1 << 1) |
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#define GENET_HAS_MDIO_INTR (1 << 2) |
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#define GENET_HAS_MOCA_LINK_DET (1 << 3) |
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/* BCMGENET hardware parameters, keep this structure nicely aligned |
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* since it is going to be used in hot paths |
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*/ |
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struct bcmgenet_hw_params { |
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u8 tx_queues; |
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u8 tx_bds_per_q; |
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u8 rx_queues; |
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u8 rx_bds_per_q; |
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u8 bp_in_en_shift; |
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u32 bp_in_mask; |
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u8 hfb_filter_cnt; |
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u8 hfb_filter_size; |
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u8 qtag_mask; |
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u16 tbuf_offset; |
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u32 hfb_offset; |
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u32 hfb_reg_offset; |
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u32 rdma_offset; |
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u32 tdma_offset; |
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u32 words_per_bd; |
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u32 flags; |
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}; |
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struct bcmgenet_skb_cb { |
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struct enet_cb *first_cb; /* First control block of SKB */ |
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struct enet_cb *last_cb; /* Last control block of SKB */ |
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unsigned int bytes_sent; /* bytes on the wire (no TSB) */ |
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}; |
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#define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) |
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struct bcmgenet_tx_ring { |
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spinlock_t lock; /* ring lock */ |
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struct napi_struct napi; /* NAPI per tx queue */ |
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unsigned long packets; |
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unsigned long bytes; |
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unsigned int index; /* ring index */ |
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unsigned int queue; /* queue index */ |
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struct enet_cb *cbs; /* tx ring buffer control block*/ |
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unsigned int size; /* size of each tx ring */ |
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unsigned int clean_ptr; /* Tx ring clean pointer */ |
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unsigned int c_index; /* last consumer index of each ring*/ |
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unsigned int free_bds; /* # of free bds for each ring */ |
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unsigned int write_ptr; /* Tx ring write pointer SW copy */ |
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unsigned int prod_index; /* Tx ring producer index SW copy */ |
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unsigned int cb_ptr; /* Tx ring initial CB ptr */ |
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unsigned int end_ptr; /* Tx ring end CB ptr */ |
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void (*int_enable)(struct bcmgenet_tx_ring *); |
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void (*int_disable)(struct bcmgenet_tx_ring *); |
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struct bcmgenet_priv *priv; |
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}; |
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struct bcmgenet_net_dim { |
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u16 use_dim; |
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u16 event_ctr; |
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unsigned long packets; |
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unsigned long bytes; |
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struct dim dim; |
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}; |
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struct bcmgenet_rx_ring { |
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struct napi_struct napi; /* Rx NAPI struct */ |
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unsigned long bytes; |
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unsigned long packets; |
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unsigned long errors; |
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unsigned long dropped; |
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unsigned int index; /* Rx ring index */ |
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struct enet_cb *cbs; /* Rx ring buffer control block */ |
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unsigned int size; /* Rx ring size */ |
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unsigned int c_index; /* Rx last consumer index */ |
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unsigned int read_ptr; /* Rx ring read pointer */ |
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unsigned int cb_ptr; /* Rx ring initial CB ptr */ |
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unsigned int end_ptr; /* Rx ring end CB ptr */ |
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unsigned int old_discards; |
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struct bcmgenet_net_dim dim; |
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u32 rx_max_coalesced_frames; |
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u32 rx_coalesce_usecs; |
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void (*int_enable)(struct bcmgenet_rx_ring *); |
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void (*int_disable)(struct bcmgenet_rx_ring *); |
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struct bcmgenet_priv *priv; |
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}; |
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enum bcmgenet_rxnfc_state { |
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BCMGENET_RXNFC_STATE_UNUSED = 0, |
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BCMGENET_RXNFC_STATE_DISABLED, |
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BCMGENET_RXNFC_STATE_ENABLED |
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}; |
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struct bcmgenet_rxnfc_rule { |
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struct list_head list; |
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struct ethtool_rx_flow_spec fs; |
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enum bcmgenet_rxnfc_state state; |
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}; |
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/* device context */ |
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struct bcmgenet_priv { |
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void __iomem *base; |
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enum bcmgenet_version version; |
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struct net_device *dev; |
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/* transmit variables */ |
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void __iomem *tx_bds; |
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struct enet_cb *tx_cbs; |
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unsigned int num_tx_bds; |
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struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; |
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/* receive variables */ |
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void __iomem *rx_bds; |
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struct enet_cb *rx_cbs; |
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unsigned int num_rx_bds; |
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unsigned int rx_buf_len; |
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struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES]; |
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struct list_head rxnfc_list; |
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struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1]; |
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/* other misc variables */ |
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struct bcmgenet_hw_params *hw_params; |
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/* MDIO bus variables */ |
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wait_queue_head_t wq; |
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bool internal_phy; |
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struct device_node *phy_dn; |
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struct device_node *mdio_dn; |
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struct mii_bus *mii_bus; |
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u16 gphy_rev; |
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struct clk *clk_eee; |
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bool clk_eee_enabled; |
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/* PHY device variables */ |
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int old_link; |
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int old_speed; |
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int old_duplex; |
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int old_pause; |
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phy_interface_t phy_interface; |
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int phy_addr; |
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int ext_phy; |
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/* Interrupt variables */ |
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struct work_struct bcmgenet_irq_work; |
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int irq0; |
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int irq1; |
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int wol_irq; |
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bool wol_irq_disabled; |
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/* shared status */ |
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spinlock_t lock; |
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unsigned int irq0_stat; |
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/* HW descriptors/checksum variables */ |
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bool crc_fwd_en; |
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u32 dma_max_burst_length; |
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u32 msg_enable; |
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struct clk *clk; |
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struct platform_device *pdev; |
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struct platform_device *mii_pdev; |
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/* WOL */ |
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struct clk *clk_wol; |
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u32 wolopts; |
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u8 sopass[SOPASS_MAX]; |
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bool wol_active; |
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struct bcmgenet_mib_counters mib; |
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struct ethtool_eee eee; |
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}; |
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#define GENET_IO_MACRO(name, offset) \ |
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static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ |
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u32 off) \ |
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{ \ |
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/* MIPS chips strapped for BE will automagically configure the \ |
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* peripheral registers for CPU-native byte order. \ |
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*/ \ |
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ |
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return __raw_readl(priv->base + offset + off); \ |
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else \ |
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return readl_relaxed(priv->base + offset + off); \ |
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} \ |
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static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ |
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u32 val, u32 off) \ |
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{ \ |
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ |
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__raw_writel(val, priv->base + offset + off); \ |
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else \ |
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writel_relaxed(val, priv->base + offset + off); \ |
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} |
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GENET_IO_MACRO(ext, GENET_EXT_OFF); |
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GENET_IO_MACRO(umac, GENET_UMAC_OFF); |
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GENET_IO_MACRO(sys, GENET_SYS_OFF); |
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|
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/* interrupt l2 registers accessors */ |
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GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); |
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GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); |
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|
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/* HFB register accessors */ |
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GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); |
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|
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/* GENET v2+ HFB control and filter len helpers */ |
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GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); |
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|
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/* RBUF register accessors */ |
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GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); |
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|
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/* MDIO routines */ |
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int bcmgenet_mii_init(struct net_device *dev); |
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int bcmgenet_mii_config(struct net_device *dev, bool init); |
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int bcmgenet_mii_probe(struct net_device *dev); |
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void bcmgenet_mii_exit(struct net_device *dev); |
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void bcmgenet_phy_power_set(struct net_device *dev, bool enable); |
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void bcmgenet_mii_setup(struct net_device *dev); |
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|
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/* Wake-on-LAN routines */ |
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void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); |
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int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); |
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int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, |
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enum bcmgenet_power_mode mode); |
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void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, |
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enum bcmgenet_power_mode mode); |
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#endif /* __BCMGENET_H__ */
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