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764 lines
22 KiB
764 lines
22 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Broadcom BCM7xxx System Port Ethernet MAC driver |
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* |
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* Copyright (C) 2014 Broadcom Corporation |
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*/ |
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#ifndef __BCM_SYSPORT_H |
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#define __BCM_SYSPORT_H |
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#include <linux/bitmap.h> |
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#include <linux/ethtool.h> |
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#include <linux/if_vlan.h> |
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#include <linux/dim.h> |
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#include "unimac.h" |
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/* Receive/transmit descriptor format */ |
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#define DESC_ADDR_HI_STATUS_LEN 0x00 |
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#define DESC_ADDR_HI_SHIFT 0 |
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#define DESC_ADDR_HI_MASK 0xff |
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#define DESC_STATUS_SHIFT 8 |
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#define DESC_STATUS_MASK 0x3ff |
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#define DESC_LEN_SHIFT 18 |
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#define DESC_LEN_MASK 0x7fff |
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#define DESC_ADDR_LO 0x04 |
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/* HW supports 40-bit addressing hence the */ |
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#define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) |
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/* Default RX buffer allocation size */ |
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#define RX_BUF_LENGTH 2048 |
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/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. |
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* 1536 is multiple of 256 bytes |
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*/ |
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#define ENET_BRCM_TAG_LEN 4 |
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#define ENET_PAD 10 |
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#define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ |
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ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) |
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/* Transmit status block */ |
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struct bcm_tsb { |
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u32 pcp_dei_vid; |
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#define PCP_DEI_MASK 0xf |
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#define VID_SHIFT 4 |
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#define VID_MASK 0xfff |
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u32 l4_ptr_dest_map; |
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#define L4_CSUM_PTR_MASK 0x1ff |
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#define L4_PTR_SHIFT 9 |
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#define L4_PTR_MASK 0x1ff |
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#define L4_UDP (1 << 18) |
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#define L4_LENGTH_VALID (1 << 19) |
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#define DEST_MAP_SHIFT 20 |
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#define DEST_MAP_MASK 0x1ff |
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}; |
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/* Receive status block uses the same |
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* definitions as the DMA descriptor |
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*/ |
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struct bcm_rsb { |
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u32 rx_status_len; |
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u32 brcm_egress_tag; |
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}; |
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/* Common Receive/Transmit status bits */ |
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#define DESC_L4_CSUM (1 << 7) |
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#define DESC_SOP (1 << 8) |
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#define DESC_EOP (1 << 9) |
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/* Receive Status bits */ |
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#define RX_STATUS_UCAST 0 |
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#define RX_STATUS_BCAST 0x04 |
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#define RX_STATUS_MCAST 0x08 |
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#define RX_STATUS_L2_MCAST 0x0c |
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#define RX_STATUS_ERR (1 << 4) |
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#define RX_STATUS_OVFLOW (1 << 5) |
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#define RX_STATUS_PARSE_FAIL (1 << 6) |
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/* Transmit Status bits */ |
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#define TX_STATUS_VLAN_NO_ACT 0x00 |
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#define TX_STATUS_VLAN_PCP_TSB 0x01 |
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#define TX_STATUS_VLAN_QUEUE 0x02 |
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#define TX_STATUS_VLAN_VID_TSB 0x03 |
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#define TX_STATUS_OWR_CRC (1 << 2) |
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#define TX_STATUS_APP_CRC (1 << 3) |
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#define TX_STATUS_BRCM_TAG_NO_ACT 0 |
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#define TX_STATUS_BRCM_TAG_ZERO 0x10 |
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#define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 |
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#define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 |
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#define TX_STATUS_SKIP_BYTES (1 << 6) |
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/* Specific register definitions */ |
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#define SYS_PORT_TOPCTRL_OFFSET 0 |
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#define REV_CNTL 0x00 |
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#define REV_MASK 0xffff |
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#define RX_FLUSH_CNTL 0x04 |
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#define RX_FLUSH (1 << 0) |
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#define TX_FLUSH_CNTL 0x08 |
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#define TX_FLUSH (1 << 0) |
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#define MISC_CNTL 0x0c |
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#define SYS_CLK_SEL (1 << 0) |
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#define TDMA_EOP_SEL (1 << 1) |
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/* Level-2 Interrupt controller offsets and defines */ |
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#define SYS_PORT_INTRL2_0_OFFSET 0x200 |
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#define SYS_PORT_INTRL2_1_OFFSET 0x240 |
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#define INTRL2_CPU_STATUS 0x00 |
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#define INTRL2_CPU_SET 0x04 |
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#define INTRL2_CPU_CLEAR 0x08 |
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#define INTRL2_CPU_MASK_STATUS 0x0c |
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#define INTRL2_CPU_MASK_SET 0x10 |
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#define INTRL2_CPU_MASK_CLEAR 0x14 |
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/* Level-2 instance 0 interrupt bits */ |
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#define INTRL2_0_GISB_ERR (1 << 0) |
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#define INTRL2_0_RBUF_OVFLOW (1 << 1) |
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#define INTRL2_0_TBUF_UNDFLOW (1 << 2) |
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#define INTRL2_0_MPD (1 << 3) |
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#define INTRL2_0_BRCM_MATCH_TAG (1 << 4) |
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#define INTRL2_0_RDMA_MBDONE (1 << 5) |
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#define INTRL2_0_OVER_MAX_THRESH (1 << 6) |
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#define INTRL2_0_BELOW_HYST_THRESH (1 << 7) |
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#define INTRL2_0_FREE_LIST_EMPTY (1 << 8) |
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#define INTRL2_0_TX_RING_FULL (1 << 9) |
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#define INTRL2_0_DESC_ALLOC_ERR (1 << 10) |
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#define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) |
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/* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ |
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#define INTRL2_0_TDMA_MBDONE_SHIFT 12 |
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#define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT) |
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/* RXCHK offset and defines */ |
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#define SYS_PORT_RXCHK_OFFSET 0x300 |
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#define RXCHK_CONTROL 0x00 |
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#define RXCHK_EN (1 << 0) |
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#define RXCHK_SKIP_FCS (1 << 1) |
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#define RXCHK_BAD_CSUM_DIS (1 << 2) |
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#define RXCHK_BRCM_TAG_EN (1 << 3) |
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#define RXCHK_BRCM_TAG_MATCH_SHIFT 4 |
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#define RXCHK_BRCM_TAG_MATCH_MASK 0xff |
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#define RXCHK_PARSE_TNL (1 << 12) |
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#define RXCHK_VIOL_EN (1 << 13) |
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#define RXCHK_VIOL_DIS (1 << 14) |
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#define RXCHK_INCOM_PKT (1 << 15) |
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#define RXCHK_V6_DUPEXT_EN (1 << 16) |
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#define RXCHK_V6_DUPEXT_DIS (1 << 17) |
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#define RXCHK_ETHERTYPE_DIS (1 << 18) |
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#define RXCHK_L2_HDR_DIS (1 << 19) |
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#define RXCHK_L3_HDR_DIS (1 << 20) |
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#define RXCHK_MAC_RX_ERR_DIS (1 << 21) |
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#define RXCHK_PARSE_AUTH (1 << 22) |
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#define RXCHK_BRCM_TAG0 0x04 |
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#define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0) |
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#define RXCHK_BRCM_TAG0_MASK 0x24 |
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#define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK) |
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#define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 |
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#define RXCHK_ETHERTYPE 0x48 |
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#define RXCHK_BAD_CSUM_CNTR 0x4C |
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#define RXCHK_OTHER_DISC_CNTR 0x50 |
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#define RXCHK_BRCM_TAG_MAX 8 |
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#define RXCHK_BRCM_TAG_CID_SHIFT 16 |
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#define RXCHK_BRCM_TAG_CID_MASK 0xff |
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/* TXCHCK offsets and defines */ |
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#define SYS_PORT_TXCHK_OFFSET 0x380 |
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#define TXCHK_PKT_RDY_THRESH 0x00 |
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/* Receive buffer offset and defines */ |
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#define SYS_PORT_RBUF_OFFSET 0x400 |
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#define RBUF_CONTROL 0x00 |
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#define RBUF_RSB_EN (1 << 0) |
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#define RBUF_4B_ALGN (1 << 1) |
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#define RBUF_BRCM_TAG_STRIP (1 << 2) |
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#define RBUF_BAD_PKT_DISC (1 << 3) |
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#define RBUF_RESUME_THRESH_SHIFT 4 |
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#define RBUF_RESUME_THRESH_MASK 0xff |
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#define RBUF_OK_TO_SEND_SHIFT 12 |
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#define RBUF_OK_TO_SEND_MASK 0xff |
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#define RBUF_CRC_REPLACE (1 << 20) |
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#define RBUF_OK_TO_SEND_MODE (1 << 21) |
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/* SYSTEMPORT Lite uses two bits here */ |
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#define RBUF_RSB_SWAP0 (1 << 22) |
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#define RBUF_RSB_SWAP1 (1 << 23) |
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#define RBUF_ACPI_EN (1 << 23) |
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#define RBUF_ACPI_EN_LITE (1 << 24) |
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#define RBUF_PKT_RDY_THRESH 0x04 |
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#define RBUF_STATUS 0x08 |
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#define RBUF_WOL_MODE (1 << 0) |
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#define RBUF_MPD (1 << 1) |
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#define RBUF_ACPI (1 << 2) |
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#define RBUF_OVFL_DISC_CNTR 0x0c |
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#define RBUF_ERR_PKT_CNTR 0x10 |
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/* Transmit buffer offset and defines */ |
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#define SYS_PORT_TBUF_OFFSET 0x600 |
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#define TBUF_CONTROL 0x00 |
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#define TBUF_BP_EN (1 << 0) |
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#define TBUF_MAX_PKT_THRESH_SHIFT 1 |
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#define TBUF_MAX_PKT_THRESH_MASK 0x1f |
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#define TBUF_FULL_THRESH_SHIFT 8 |
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#define TBUF_FULL_THRESH_MASK 0x1f |
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/* UniMAC offset and defines */ |
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#define SYS_PORT_UMAC_OFFSET 0x800 |
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#define UMAC_MIB_START 0x400 |
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/* There is a 0xC gap between the end of RX and beginning of TX stats and then |
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* between the end of TX stats and the beginning of the RX RUNT |
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*/ |
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#define UMAC_MIB_STAT_OFFSET 0xc |
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#define UMAC_MIB_CTRL 0x580 |
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#define MIB_RX_CNT_RST (1 << 0) |
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#define MIB_RUNT_CNT_RST (1 << 1) |
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#define MIB_TX_CNT_RST (1 << 2) |
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/* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ |
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#define UMAC_MPD_CTRL 0x620 |
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#define MPD_EN (1 << 0) |
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#define MSEQ_LEN_SHIFT 16 |
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#define MSEQ_LEN_MASK 0xff |
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#define PSW_EN (1 << 27) |
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#define UMAC_PSW_MS 0x624 |
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#define UMAC_PSW_LS 0x628 |
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#define UMAC_MDF_CTRL 0x650 |
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#define UMAC_MDF_ADDR 0x654 |
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/* Only valid on SYSTEMPORT Lite */ |
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#define SYS_PORT_GIB_OFFSET 0x1000 |
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#define GIB_CONTROL 0x00 |
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#define GIB_TX_EN (1 << 0) |
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#define GIB_RX_EN (1 << 1) |
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#define GIB_TX_FLUSH (1 << 2) |
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#define GIB_RX_FLUSH (1 << 3) |
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#define GIB_GTX_CLK_SEL_SHIFT 4 |
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#define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT) |
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#define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT) |
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#define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT) |
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#define GIB_FCS_STRIP_SHIFT 6 |
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#define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT) |
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#define GIB_LCL_LOOP_EN (1 << 7) |
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#define GIB_LCL_LOOP_TXEN (1 << 8) |
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#define GIB_RMT_LOOP_EN (1 << 9) |
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#define GIB_RMT_LOOP_RXEN (1 << 10) |
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#define GIB_RX_PAUSE_EN (1 << 11) |
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#define GIB_PREAMBLE_LEN_SHIFT 12 |
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#define GIB_PREAMBLE_LEN_MASK 0xf |
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#define GIB_IPG_LEN_SHIFT 16 |
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#define GIB_IPG_LEN_MASK 0x3f |
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#define GIB_PAD_EXTENSION_SHIFT 22 |
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#define GIB_PAD_EXTENSION_MASK 0x3f |
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#define GIB_MAC1 0x08 |
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#define GIB_MAC0 0x0c |
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/* Receive DMA offset and defines */ |
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#define SYS_PORT_RDMA_OFFSET 0x2000 |
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#define RDMA_CONTROL 0x1000 |
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#define RDMA_EN (1 << 0) |
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#define RDMA_RING_CFG (1 << 1) |
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#define RDMA_DISC_EN (1 << 2) |
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#define RDMA_BUF_DATA_OFFSET_SHIFT 4 |
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#define RDMA_BUF_DATA_OFFSET_MASK 0x3ff |
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#define RDMA_STATUS 0x1004 |
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#define RDMA_DISABLED (1 << 0) |
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#define RDMA_DESC_RAM_INIT_BUSY (1 << 1) |
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#define RDMA_BP_STATUS (1 << 2) |
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#define RDMA_SCB_BURST_SIZE 0x1008 |
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#define RDMA_RING_BUF_SIZE 0x100c |
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#define RDMA_RING_SIZE_SHIFT 16 |
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#define RDMA_WRITE_PTR_HI 0x1010 |
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#define RDMA_WRITE_PTR_LO 0x1014 |
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#define RDMA_PROD_INDEX 0x1018 |
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#define RDMA_PROD_INDEX_MASK 0xffff |
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#define RDMA_CONS_INDEX 0x101c |
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#define RDMA_CONS_INDEX_MASK 0xffff |
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#define RDMA_START_ADDR_HI 0x1020 |
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#define RDMA_START_ADDR_LO 0x1024 |
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#define RDMA_END_ADDR_HI 0x1028 |
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#define RDMA_END_ADDR_LO 0x102c |
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#define RDMA_MBDONE_INTR 0x1030 |
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#define RDMA_INTR_THRESH_MASK 0x1ff |
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#define RDMA_TIMEOUT_SHIFT 16 |
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#define RDMA_TIMEOUT_MASK 0xffff |
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#define RDMA_XON_XOFF_THRESH 0x1034 |
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#define RDMA_XON_XOFF_THRESH_MASK 0xffff |
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#define RDMA_XOFF_THRESH_SHIFT 16 |
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#define RDMA_READ_PTR_HI 0x1038 |
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#define RDMA_READ_PTR_LO 0x103c |
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#define RDMA_OVERRIDE 0x1040 |
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#define RDMA_LE_MODE (1 << 0) |
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#define RDMA_REG_MODE (1 << 1) |
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#define RDMA_TEST 0x1044 |
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#define RDMA_TP_OUT_SEL (1 << 0) |
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#define RDMA_MEM_SEL (1 << 1) |
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#define RDMA_DEBUG 0x1048 |
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/* Transmit DMA offset and defines */ |
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#define TDMA_NUM_RINGS 32 /* rings = queues */ |
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#define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ |
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#define SYS_PORT_TDMA_OFFSET 0x4000 |
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#define TDMA_WRITE_PORT_OFFSET 0x0000 |
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#define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ |
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(i) * TDMA_PORT_SIZE) |
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#define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ |
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sizeof(u32) + (i) * TDMA_PORT_SIZE) |
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#define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ |
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(TDMA_NUM_RINGS * TDMA_PORT_SIZE)) |
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#define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ |
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(i) * TDMA_PORT_SIZE) |
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#define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ |
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sizeof(u32) + (i) * TDMA_PORT_SIZE) |
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#define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ |
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(TDMA_NUM_RINGS * TDMA_PORT_SIZE)) |
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#define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ |
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(i) * sizeof(u32)) |
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#define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ |
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(TDMA_NUM_RINGS * sizeof(u32))) |
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/* Register offsets and defines relatives to a specific ring number */ |
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#define RING_HEAD_TAIL_PTR 0x00 |
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#define RING_HEAD_MASK 0x7ff |
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#define RING_TAIL_SHIFT 11 |
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#define RING_TAIL_MASK 0x7ff |
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#define RING_FLUSH (1 << 24) |
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#define RING_EN (1 << 25) |
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#define RING_COUNT 0x04 |
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#define RING_COUNT_MASK 0x7ff |
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#define RING_BUFF_DONE_SHIFT 11 |
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#define RING_BUFF_DONE_MASK 0x7ff |
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#define RING_MAX_HYST 0x08 |
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#define RING_MAX_THRESH_MASK 0x7ff |
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#define RING_HYST_THRESH_SHIFT 11 |
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#define RING_HYST_THRESH_MASK 0x7ff |
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#define RING_INTR_CONTROL 0x0c |
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#define RING_INTR_THRESH_MASK 0x7ff |
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#define RING_EMPTY_INTR_EN (1 << 15) |
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#define RING_TIMEOUT_SHIFT 16 |
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#define RING_TIMEOUT_MASK 0xffff |
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#define RING_PROD_CONS_INDEX 0x10 |
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#define RING_PROD_INDEX_MASK 0xffff |
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#define RING_CONS_INDEX_SHIFT 16 |
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#define RING_CONS_INDEX_MASK 0xffff |
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#define RING_MAPPING 0x14 |
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#define RING_QID_MASK 0x7 |
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#define RING_PORT_ID_SHIFT 3 |
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#define RING_PORT_ID_MASK 0x7 |
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#define RING_IGNORE_STATUS (1 << 6) |
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#define RING_FAILOVER_EN (1 << 7) |
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#define RING_CREDIT_SHIFT 8 |
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#define RING_CREDIT_MASK 0xffff |
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#define RING_PCP_DEI_VID 0x18 |
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#define RING_VID_MASK 0x7ff |
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#define RING_DEI (1 << 12) |
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#define RING_PCP_SHIFT 13 |
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#define RING_PCP_MASK 0x7 |
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#define RING_PKT_SIZE_ADJ_SHIFT 16 |
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#define RING_PKT_SIZE_ADJ_MASK 0xf |
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#define TDMA_DESC_RING_SIZE 28 |
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/* Defininition for a given TX ring base address */ |
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#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ |
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((i) * TDMA_DESC_RING_SIZE)) |
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/* Ring indexed register addreses */ |
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#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_HEAD_TAIL_PTR) |
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#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_COUNT) |
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#define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_MAX_HYST) |
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#define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_INTR_CONTROL) |
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#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ |
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(TDMA_DESC_RING_BASE(i) + \ |
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RING_PROD_CONS_INDEX) |
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#define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_MAPPING) |
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#define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ |
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RING_PCP_DEI_VID) |
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#define TDMA_CONTROL 0x600 |
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#define TDMA_EN 0 |
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#define TSB_EN 1 |
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/* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we |
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* keep the SYSTEMPORT layout here and adjust with tdma_control_bit() |
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*/ |
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#define TSB_SWAP0 2 |
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#define TSB_SWAP1 3 |
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#define ACB_ALGO 3 |
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#define BUF_DATA_OFFSET_SHIFT 4 |
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#define BUF_DATA_OFFSET_MASK 0x3ff |
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#define VLAN_EN 14 |
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#define SW_BRCM_TAG 15 |
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#define WNC_KPT_SIZE_UPDATE 16 |
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#define SYNC_PKT_SIZE 17 |
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#define ACH_TXDONE_DELAY_SHIFT 18 |
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#define ACH_TXDONE_DELAY_MASK 0xff |
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#define TDMA_STATUS 0x604 |
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#define TDMA_DISABLED (1 << 0) |
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#define TDMA_LL_RAM_INIT_BUSY (1 << 1) |
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#define TDMA_SCB_BURST_SIZE 0x608 |
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#define TDMA_OVER_MAX_THRESH_STATUS 0x60c |
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#define TDMA_OVER_HYST_THRESH_STATUS 0x610 |
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#define TDMA_TPID 0x614 |
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#define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 |
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#define TDMA_FREE_HEAD_MASK 0x7ff |
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#define TDMA_FREE_TAIL_SHIFT 11 |
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#define TDMA_FREE_TAIL_MASK 0x7ff |
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#define TDMA_FREE_LIST_COUNT 0x61c |
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#define TDMA_FREE_LIST_COUNT_MASK 0x7ff |
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#define TDMA_TIER2_ARB_CTRL 0x620 |
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#define TDMA_ARB_MODE_RR 0 |
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#define TDMA_ARB_MODE_WEIGHT_RR 0x1 |
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#define TDMA_ARB_MODE_STRICT 0x2 |
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#define TDMA_ARB_MODE_DEFICIT_RR 0x3 |
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#define TDMA_CREDIT_SHIFT 4 |
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#define TDMA_CREDIT_MASK 0xffff |
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#define TDMA_TIER1_ARB_0_CTRL 0x624 |
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#define TDMA_ARB_EN (1 << 0) |
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#define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 |
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#define TDMA_TIER1_ARB_1_CTRL 0x62c |
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#define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 |
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#define TDMA_TIER1_ARB_2_CTRL 0x634 |
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#define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 |
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#define TDMA_TIER1_ARB_3_CTRL 0x63c |
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#define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 |
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#define TDMA_SCB_ENDIAN_OVERRIDE 0x644 |
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#define TDMA_LE_MODE (1 << 0) |
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#define TDMA_REG_MODE (1 << 1) |
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#define TDMA_TEST 0x648 |
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#define TDMA_TP_OUT_SEL (1 << 0) |
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#define TDMA_MEM_TM (1 << 1) |
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#define TDMA_DEBUG 0x64c |
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/* Number of Receive hardware descriptor words */ |
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#define SP_NUM_HW_RX_DESC_WORDS 1024 |
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#define SP_LT_NUM_HW_RX_DESC_WORDS 256 |
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/* Internal linked-list RAM size */ |
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#define SP_NUM_TX_DESC 1536 |
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#define SP_LT_NUM_TX_DESC 256 |
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#define WORDS_PER_DESC 2 |
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/* Rx/Tx common counter group.*/ |
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struct bcm_sysport_pkt_counters { |
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u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ |
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u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ |
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u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ |
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u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ |
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u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ |
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u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ |
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u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ |
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u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ |
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u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ |
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u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ |
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}; |
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/* RSV, Receive Status Vector */ |
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struct bcm_sysport_rx_counters { |
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struct bcm_sysport_pkt_counters pkt_cnt; |
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u32 pkt; /* RO (0x428) Received pkt count*/ |
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u32 bytes; /* RO Received byte count */ |
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u32 mca; /* RO # of Received multicast pkt */ |
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u32 bca; /* RO # of Receive broadcast pkt */ |
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u32 fcs; /* RO # of Received FCS error */ |
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u32 cf; /* RO # of Received control frame pkt*/ |
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u32 pf; /* RO # of Received pause frame pkt */ |
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u32 uo; /* RO # of unknown op code pkt */ |
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u32 aln; /* RO # of alignment error count */ |
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u32 flr; /* RO # of frame length out of range count */ |
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u32 cde; /* RO # of code error pkt */ |
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u32 fcr; /* RO # of carrier sense error pkt */ |
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u32 ovr; /* RO # of oversize pkt*/ |
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u32 jbr; /* RO # of jabber count */ |
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u32 mtue; /* RO # of MTU error pkt*/ |
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u32 pok; /* RO # of Received good pkt */ |
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u32 uc; /* RO # of unicast pkt */ |
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u32 ppp; /* RO # of PPP pkt */ |
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u32 rcrc; /* RO (0x470),# of CRC match pkt */ |
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}; |
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/* TSV, Transmit Status Vector */ |
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struct bcm_sysport_tx_counters { |
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struct bcm_sysport_pkt_counters pkt_cnt; |
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u32 pkts; /* RO (0x4a8) Transmited pkt */ |
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u32 mca; /* RO # of xmited multicast pkt */ |
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u32 bca; /* RO # of xmited broadcast pkt */ |
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u32 pf; /* RO # of xmited pause frame count */ |
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u32 cf; /* RO # of xmited control frame count */ |
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u32 fcs; /* RO # of xmited FCS error count */ |
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u32 ovr; /* RO # of xmited oversize pkt */ |
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u32 drf; /* RO # of xmited deferral pkt */ |
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u32 edf; /* RO # of xmited Excessive deferral pkt*/ |
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u32 scl; /* RO # of xmited single collision pkt */ |
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u32 mcl; /* RO # of xmited multiple collision pkt*/ |
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u32 lcl; /* RO # of xmited late collision pkt */ |
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u32 ecl; /* RO # of xmited excessive collision pkt*/ |
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u32 frg; /* RO # of xmited fragments pkt*/ |
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u32 ncl; /* RO # of xmited total collision count */ |
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u32 jbr; /* RO # of xmited jabber count*/ |
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u32 bytes; /* RO # of xmited byte count */ |
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u32 pok; /* RO # of xmited good pkt */ |
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u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ |
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}; |
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struct bcm_sysport_mib { |
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struct bcm_sysport_rx_counters rx; |
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struct bcm_sysport_tx_counters tx; |
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u32 rx_runt_cnt; |
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u32 rx_runt_fcs; |
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u32 rx_runt_fcs_align; |
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u32 rx_runt_bytes; |
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u32 rxchk_bad_csum; |
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u32 rxchk_other_pkt_disc; |
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u32 rbuf_ovflow_cnt; |
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u32 rbuf_err_cnt; |
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u32 alloc_rx_buff_failed; |
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u32 rx_dma_failed; |
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u32 tx_dma_failed; |
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u32 tx_realloc_tsb; |
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u32 tx_realloc_tsb_failed; |
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}; |
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/* HW maintains a large list of counters */ |
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enum bcm_sysport_stat_type { |
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BCM_SYSPORT_STAT_NETDEV = -1, |
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BCM_SYSPORT_STAT_NETDEV64, |
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BCM_SYSPORT_STAT_MIB_RX, |
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BCM_SYSPORT_STAT_MIB_TX, |
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BCM_SYSPORT_STAT_RUNT, |
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BCM_SYSPORT_STAT_RXCHK, |
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BCM_SYSPORT_STAT_RBUF, |
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BCM_SYSPORT_STAT_SOFT, |
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}; |
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/* Macros to help define ethtool statistics */ |
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#define STAT_NETDEV(m) { \ |
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.stat_string = __stringify(m), \ |
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.stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ |
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.stat_offset = offsetof(struct net_device_stats, m), \ |
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.type = BCM_SYSPORT_STAT_NETDEV, \ |
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} |
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#define STAT_NETDEV64(m) { \ |
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.stat_string = __stringify(m), \ |
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.stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \ |
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.stat_offset = offsetof(struct bcm_sysport_stats64, m), \ |
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.type = BCM_SYSPORT_STAT_NETDEV64, \ |
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} |
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#define STAT_MIB(str, m, _type) { \ |
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.stat_string = str, \ |
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.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ |
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.stat_offset = offsetof(struct bcm_sysport_priv, m), \ |
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.type = _type, \ |
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} |
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#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) |
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#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) |
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#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) |
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#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) |
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#define STAT_RXCHK(str, m, ofs) { \ |
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.stat_string = str, \ |
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.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ |
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.stat_offset = offsetof(struct bcm_sysport_priv, m), \ |
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.type = BCM_SYSPORT_STAT_RXCHK, \ |
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.reg_offset = ofs, \ |
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} |
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#define STAT_RBUF(str, m, ofs) { \ |
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.stat_string = str, \ |
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.stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ |
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.stat_offset = offsetof(struct bcm_sysport_priv, m), \ |
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.type = BCM_SYSPORT_STAT_RBUF, \ |
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.reg_offset = ofs, \ |
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} |
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/* TX bytes and packets */ |
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#define NUM_SYSPORT_TXQ_STAT 2 |
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struct bcm_sysport_stats { |
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char stat_string[ETH_GSTRING_LEN]; |
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int stat_sizeof; |
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int stat_offset; |
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enum bcm_sysport_stat_type type; |
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/* reg offset from UMAC base for misc counters */ |
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u16 reg_offset; |
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}; |
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struct bcm_sysport_stats64 { |
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/* 64bit stats on 32bit/64bit Machine */ |
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u64 rx_packets; |
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u64 rx_bytes; |
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u64 tx_packets; |
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u64 tx_bytes; |
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}; |
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/* Software house keeping helper structure */ |
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struct bcm_sysport_cb { |
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struct sk_buff *skb; /* SKB for RX packets */ |
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void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ |
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DEFINE_DMA_UNMAP_ADDR(dma_addr); |
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DEFINE_DMA_UNMAP_LEN(dma_len); |
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}; |
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enum bcm_sysport_type { |
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SYSTEMPORT = 0, |
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SYSTEMPORT_LITE, |
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}; |
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struct bcm_sysport_hw_params { |
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bool is_lite; |
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unsigned int num_rx_desc_words; |
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}; |
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struct bcm_sysport_net_dim { |
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u16 use_dim; |
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u16 event_ctr; |
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unsigned long packets; |
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unsigned long bytes; |
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struct dim dim; |
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}; |
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/* Software view of the TX ring */ |
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struct bcm_sysport_tx_ring { |
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spinlock_t lock; /* Ring lock for tx reclaim/xmit */ |
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struct napi_struct napi; /* NAPI per tx queue */ |
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unsigned int index; /* Ring index */ |
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unsigned int size; /* Ring current size */ |
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unsigned int alloc_size; /* Ring one-time allocated size */ |
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unsigned int desc_count; /* Number of descriptors */ |
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unsigned int curr_desc; /* Current descriptor */ |
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unsigned int c_index; /* Last consumer index */ |
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unsigned int clean_index; /* Current clean index */ |
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struct bcm_sysport_cb *cbs; /* Transmit control blocks */ |
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struct bcm_sysport_priv *priv; /* private context backpointer */ |
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unsigned long packets; /* packets statistics */ |
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unsigned long bytes; /* bytes statistics */ |
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unsigned int switch_queue; /* switch port queue number */ |
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unsigned int switch_port; /* switch port queue number */ |
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bool inspect; /* inspect switch port and queue */ |
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}; |
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/* Driver private structure */ |
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struct bcm_sysport_priv { |
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void __iomem *base; |
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u32 irq0_stat; |
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u32 irq0_mask; |
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u32 irq1_stat; |
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u32 irq1_mask; |
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bool is_lite; |
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unsigned int num_rx_desc_words; |
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struct napi_struct napi ____cacheline_aligned; |
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struct net_device *netdev; |
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struct platform_device *pdev; |
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int irq0; |
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int irq1; |
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int wol_irq; |
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/* Transmit rings */ |
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struct bcm_sysport_tx_ring *tx_rings; |
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/* Receive queue */ |
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void __iomem *rx_bds; |
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struct bcm_sysport_cb *rx_cbs; |
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unsigned int num_rx_bds; |
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unsigned int rx_read_ptr; |
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unsigned int rx_c_index; |
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struct bcm_sysport_net_dim dim; |
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u32 rx_max_coalesced_frames; |
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u32 rx_coalesce_usecs; |
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/* PHY device */ |
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struct device_node *phy_dn; |
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phy_interface_t phy_interface; |
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int old_pause; |
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int old_link; |
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int old_duplex; |
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/* Misc fields */ |
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unsigned int rx_chk_en:1; |
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unsigned int tsb_en:1; |
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unsigned int crc_fwd:1; |
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u16 rev; |
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u32 wolopts; |
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u8 sopass[SOPASS_MAX]; |
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unsigned int wol_irq_disabled:1; |
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struct clk *clk; |
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struct clk *wol_clk; |
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/* MIB related fields */ |
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struct bcm_sysport_mib mib; |
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/* Ethtool */ |
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u32 msg_enable; |
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DECLARE_BITMAP(filters, RXCHK_BRCM_TAG_MAX); |
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u32 filters_loc[RXCHK_BRCM_TAG_MAX]; |
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struct bcm_sysport_stats64 stats64; |
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/* For atomic update generic 64bit value on 32bit Machine */ |
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struct u64_stats_sync syncp; |
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/* map information between switch port queues and local queues */ |
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struct notifier_block netdev_notifier; |
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unsigned int per_port_num_tx_queues; |
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struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8]; |
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}; |
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#endif /* __BCM_SYSPORT_H */
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