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104 lines
2.7 KiB
104 lines
2.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Applied Micro X-Gene SoC Ethernet v2 Driver |
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* |
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* Copyright (c) 2017, Applied Micro Circuits Corporation |
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* Author(s): Iyappan Subramanian <[email protected]> |
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* Keyur Chudgar <[email protected]> |
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*/ |
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#include "main.h" |
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void xge_mac_reset(struct xge_pdata *pdata) |
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{ |
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xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET); |
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xge_wr_csr(pdata, MAC_CONFIG_1, 0); |
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} |
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void xge_mac_set_speed(struct xge_pdata *pdata) |
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{ |
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u32 icm0, icm2, ecm0, mc2; |
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u32 intf_ctrl, rgmii; |
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icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0); |
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icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0); |
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ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0); |
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rgmii = xge_rd_csr(pdata, RGMII_REG_0); |
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mc2 = xge_rd_csr(pdata, MAC_CONFIG_2); |
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intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL); |
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icm2 |= CFG_WAITASYNCRD_EN; |
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switch (pdata->phy_speed) { |
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case SPEED_10: |
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SET_REG_BITS(&mc2, INTF_MODE, 1); |
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SET_REG_BITS(&intf_ctrl, HD_MODE, 0); |
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SET_REG_BITS(&icm0, CFG_MACMODE, 0); |
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SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500); |
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SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); |
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break; |
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case SPEED_100: |
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SET_REG_BITS(&mc2, INTF_MODE, 1); |
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SET_REG_BITS(&intf_ctrl, HD_MODE, 1); |
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SET_REG_BITS(&icm0, CFG_MACMODE, 1); |
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SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80); |
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SET_REG_BIT(&rgmii, CFG_SPEED_125, 0); |
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break; |
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default: |
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SET_REG_BITS(&mc2, INTF_MODE, 2); |
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SET_REG_BITS(&intf_ctrl, HD_MODE, 2); |
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SET_REG_BITS(&icm0, CFG_MACMODE, 2); |
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SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16); |
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SET_REG_BIT(&rgmii, CFG_SPEED_125, 1); |
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break; |
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} |
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mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC; |
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SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32); |
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xge_wr_csr(pdata, MAC_CONFIG_2, mc2); |
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xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl); |
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xge_wr_csr(pdata, RGMII_REG_0, rgmii); |
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xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0); |
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xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2); |
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xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0); |
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} |
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void xge_mac_set_station_addr(struct xge_pdata *pdata) |
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{ |
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u8 *dev_addr = pdata->ndev->dev_addr; |
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u32 addr0, addr1; |
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addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | |
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(dev_addr[1] << 8) | dev_addr[0]; |
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addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16); |
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xge_wr_csr(pdata, STATION_ADDR0, addr0); |
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xge_wr_csr(pdata, STATION_ADDR1, addr1); |
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} |
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void xge_mac_init(struct xge_pdata *pdata) |
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{ |
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xge_mac_reset(pdata); |
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xge_mac_set_speed(pdata); |
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xge_mac_set_station_addr(pdata); |
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} |
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void xge_mac_enable(struct xge_pdata *pdata) |
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{ |
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u32 data; |
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data = xge_rd_csr(pdata, MAC_CONFIG_1); |
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data |= TX_EN | RX_EN; |
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xge_wr_csr(pdata, MAC_CONFIG_1, data); |
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data = xge_rd_csr(pdata, MAC_CONFIG_1); |
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} |
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void xge_mac_disable(struct xge_pdata *pdata) |
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{ |
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u32 data; |
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data = xge_rd_csr(pdata, MAC_CONFIG_1); |
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data &= ~(TX_EN | RX_EN); |
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xge_wr_csr(pdata, MAC_CONFIG_1, data); |
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}
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