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727 lines
18 KiB
727 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2016 Sigma Designs |
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*/ |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/clk.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/platform_device.h> |
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/* Offsets relative to chip->base */ |
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#define PBUS_CMD 0 |
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#define PBUS_ADDR 4 |
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#define PBUS_DATA 8 |
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/* Offsets relative to reg_base */ |
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#define NFC_STATUS 0x00 |
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#define NFC_FLASH_CMD 0x04 |
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#define NFC_DEVICE_CFG 0x08 |
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#define NFC_TIMING1 0x0c |
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#define NFC_TIMING2 0x10 |
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#define NFC_XFER_CFG 0x14 |
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#define NFC_PKT_0_CFG 0x18 |
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#define NFC_PKT_N_CFG 0x1c |
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#define NFC_BB_CFG 0x20 |
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#define NFC_ADDR_PAGE 0x24 |
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#define NFC_ADDR_OFFSET 0x28 |
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#define NFC_XFER_STATUS 0x2c |
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/* NFC_STATUS values */ |
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#define CMD_READY BIT(31) |
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/* NFC_FLASH_CMD values */ |
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#define NFC_READ 1 |
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#define NFC_WRITE 2 |
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/* NFC_XFER_STATUS values */ |
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#define PAGE_IS_EMPTY BIT(16) |
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/* Offsets relative to mem_base */ |
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#define METADATA 0x000 |
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#define ERROR_REPORT 0x1c0 |
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/* |
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* Error reports are split in two bytes: |
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* byte 0 for the first packet in the page (PKT_0) |
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* byte 1 for other packets in the page (PKT_N, for N > 0) |
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* ERR_COUNT_PKT_N is the max error count over all but the first packet. |
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*/ |
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#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f) |
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#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f) |
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#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0) |
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#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0) |
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/* Offsets relative to pbus_base */ |
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#define PBUS_CS_CTRL 0x83c |
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#define PBUS_PAD_MODE 0x8f0 |
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/* PBUS_CS_CTRL values */ |
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#define PBUS_IORDY BIT(31) |
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/* |
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* PBUS_PAD_MODE values |
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* In raw mode, the driver communicates directly with the NAND chips. |
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* In NFC mode, the NAND Flash controller manages the communication. |
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* We use NFC mode for read and write; raw mode for everything else. |
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*/ |
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#define MODE_RAW 0 |
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#define MODE_NFC BIT(31) |
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#define METADATA_SIZE 4 |
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#define BBM_SIZE 6 |
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#define FIELD_ORDER 15 |
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#define MAX_CS 4 |
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struct tango_nfc { |
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struct nand_controller hw; |
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void __iomem *reg_base; |
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void __iomem *mem_base; |
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void __iomem *pbus_base; |
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struct tango_chip *chips[MAX_CS]; |
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struct dma_chan *chan; |
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int freq_kHz; |
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}; |
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#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw) |
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struct tango_chip { |
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struct nand_chip nand_chip; |
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void __iomem *base; |
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u32 timing1; |
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u32 timing2; |
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u32 xfer_cfg; |
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u32 pkt_0_cfg; |
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u32 pkt_n_cfg; |
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u32 bb_cfg; |
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}; |
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#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip) |
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#define XFER_CFG(cs, page_count, steps, metadata_size) \ |
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((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size)) |
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#define PKT_CFG(size, strength) ((size) << 16 | (strength)) |
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#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size)) |
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#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3)) |
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static void tango_select_target(struct nand_chip *chip, unsigned int cs) |
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{ |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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struct tango_chip *tchip = to_tango_chip(chip); |
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writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1); |
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writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2); |
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writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG); |
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writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG); |
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writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG); |
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writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG); |
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} |
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static int tango_waitrdy(struct nand_chip *chip, unsigned int timeout_ms) |
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{ |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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u32 status; |
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return readl_relaxed_poll_timeout(nfc->pbus_base + PBUS_CS_CTRL, |
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status, status & PBUS_IORDY, 20, |
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timeout_ms); |
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} |
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static int tango_exec_instr(struct nand_chip *chip, |
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const struct nand_op_instr *instr) |
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{ |
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struct tango_chip *tchip = to_tango_chip(chip); |
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unsigned int i; |
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switch (instr->type) { |
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case NAND_OP_CMD_INSTR: |
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writeb_relaxed(instr->ctx.cmd.opcode, tchip->base + PBUS_CMD); |
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return 0; |
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case NAND_OP_ADDR_INSTR: |
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for (i = 0; i < instr->ctx.addr.naddrs; i++) |
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writeb_relaxed(instr->ctx.addr.addrs[i], |
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tchip->base + PBUS_ADDR); |
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return 0; |
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case NAND_OP_DATA_IN_INSTR: |
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ioread8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.in, |
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instr->ctx.data.len); |
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return 0; |
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case NAND_OP_DATA_OUT_INSTR: |
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iowrite8_rep(tchip->base + PBUS_DATA, instr->ctx.data.buf.out, |
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instr->ctx.data.len); |
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return 0; |
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case NAND_OP_WAITRDY_INSTR: |
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return tango_waitrdy(chip, |
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instr->ctx.waitrdy.timeout_ms); |
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default: |
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break; |
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} |
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return -EINVAL; |
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} |
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static int tango_exec_op(struct nand_chip *chip, |
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const struct nand_operation *op, |
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bool check_only) |
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{ |
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unsigned int i; |
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int ret = 0; |
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if (check_only) |
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return 0; |
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tango_select_target(chip, op->cs); |
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for (i = 0; i < op->ninstrs; i++) { |
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ret = tango_exec_instr(chip, &op->instrs[i]); |
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if (ret) |
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break; |
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} |
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return ret; |
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} |
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/* |
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* The controller does not check for bitflips in erased pages, |
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* therefore software must check instead. |
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*/ |
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static int check_erased_page(struct nand_chip *chip, u8 *buf) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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u8 *meta = chip->oob_poi + BBM_SIZE; |
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u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE; |
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const int ecc_size = chip->ecc.bytes; |
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const int pkt_size = chip->ecc.size; |
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int i, res, meta_len, bitflips = 0; |
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for (i = 0; i < chip->ecc.steps; ++i) { |
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meta_len = i ? 0 : METADATA_SIZE; |
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res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size, |
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meta, meta_len, |
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chip->ecc.strength); |
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if (res < 0) |
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mtd->ecc_stats.failed++; |
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else |
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mtd->ecc_stats.corrected += res; |
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bitflips = max(res, bitflips); |
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buf += pkt_size; |
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ecc += ecc_size; |
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} |
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return bitflips; |
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} |
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static int decode_error_report(struct nand_chip *chip) |
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{ |
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u32 status, res; |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS); |
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if (status & PAGE_IS_EMPTY) |
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return 0; |
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res = readl_relaxed(nfc->mem_base + ERROR_REPORT); |
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if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res)) |
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return -EBADMSG; |
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/* ERR_COUNT_PKT_N is max, not sum, but that's all we have */ |
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mtd->ecc_stats.corrected += |
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ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res); |
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return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res)); |
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} |
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static void tango_dma_callback(void *arg) |
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{ |
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complete(arg); |
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} |
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static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd, |
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const void *buf, int len, int page) |
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{ |
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void __iomem *addr = nfc->reg_base + NFC_STATUS; |
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struct dma_chan *chan = nfc->chan; |
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struct dma_async_tx_descriptor *desc; |
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enum dma_transfer_direction tdir; |
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struct scatterlist sg; |
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struct completion tx_done; |
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int err = -EIO; |
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u32 res, val; |
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sg_init_one(&sg, buf, len); |
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if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1) |
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return -EIO; |
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tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; |
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desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT); |
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if (!desc) |
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goto dma_unmap; |
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desc->callback = tango_dma_callback; |
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desc->callback_param = &tx_done; |
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init_completion(&tx_done); |
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writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE); |
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writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE); |
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writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET); |
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writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD); |
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dmaengine_submit(desc); |
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dma_async_issue_pending(chan); |
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res = wait_for_completion_timeout(&tx_done, HZ); |
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if (res > 0) |
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err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000); |
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writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); |
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dma_unmap: |
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dma_unmap_sg(chan->device->dev, &sg, 1, dir); |
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return err; |
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} |
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static int tango_read_page(struct nand_chip *chip, u8 *buf, |
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int oob_required, int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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int err, res, len = mtd->writesize; |
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tango_select_target(chip, chip->cur_cs); |
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if (oob_required) |
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chip->ecc.read_oob(chip, page); |
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err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page); |
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if (err) |
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return err; |
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res = decode_error_report(chip); |
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if (res < 0) { |
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chip->ecc.read_oob_raw(chip, page); |
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res = check_erased_page(chip, buf); |
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} |
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return res; |
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} |
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static int tango_write_page(struct nand_chip *chip, const u8 *buf, |
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int oob_required, int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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const struct nand_sdr_timings *timings; |
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int err, len = mtd->writesize; |
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u8 status; |
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/* Calling tango_write_oob() would send PAGEPROG twice */ |
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if (oob_required) |
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return -ENOTSUPP; |
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tango_select_target(chip, chip->cur_cs); |
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writel_relaxed(0xffffffff, nfc->mem_base + METADATA); |
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err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page); |
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if (err) |
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return err; |
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timings = nand_get_sdr_timings(nand_get_interface_config(chip)); |
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err = tango_waitrdy(chip, PSEC_TO_MSEC(timings->tR_max)); |
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if (err) |
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return err; |
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err = nand_status_op(chip, &status); |
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if (err) |
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return err; |
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return (status & NAND_STATUS_FAIL) ? -EIO : 0; |
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} |
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static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos) |
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{ |
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*pos += len; |
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if (!*buf) { |
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/* skip over "len" bytes */ |
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nand_change_read_column_op(chip, *pos, NULL, 0, false); |
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} else { |
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struct tango_chip *tchip = to_tango_chip(chip); |
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ioread8_rep(tchip->base + PBUS_DATA, *buf, len); |
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*buf += len; |
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} |
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} |
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static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos) |
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{ |
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*pos += len; |
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if (!*buf) { |
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/* skip over "len" bytes */ |
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nand_change_write_column_op(chip, *pos, NULL, 0, false); |
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} else { |
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struct tango_chip *tchip = to_tango_chip(chip); |
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iowrite8_rep(tchip->base + PBUS_DATA, *buf, len); |
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*buf += len; |
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} |
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} |
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/* |
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* Physical page layout (not drawn to scale) |
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* |
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* NB: Bad Block Marker area splits PKT_N in two (N1, N2). |
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* |
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* +---+-----------------+-------+-----+-----------+-----+----+-------+ |
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* | M | PKT_0 | ECC_0 | ... | N1 | BBM | N2 | ECC_N | |
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* +---+-----------------+-------+-----+-----------+-----+----+-------+ |
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* |
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* Logical page layout: |
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* |
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* +-----+---+-------+-----+-------+ |
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* oob = | BBM | M | ECC_0 | ... | ECC_N | |
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* +-----+---+-------+-----+-------+ |
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* |
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* +-----------------+-----+-----------------+ |
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* buf = | PKT_0 | ... | PKT_N | |
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* +-----------------+-----+-----------------+ |
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*/ |
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static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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u8 *oob_orig = oob; |
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const int page_size = mtd->writesize; |
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const int ecc_size = chip->ecc.bytes; |
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const int pkt_size = chip->ecc.size; |
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int pos = 0; /* position within physical page */ |
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int rem = page_size; /* bytes remaining until BBM area */ |
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if (oob) |
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oob += BBM_SIZE; |
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aux_read(chip, &oob, METADATA_SIZE, &pos); |
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while (rem > pkt_size) { |
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aux_read(chip, &buf, pkt_size, &pos); |
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aux_read(chip, &oob, ecc_size, &pos); |
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rem = page_size - pos; |
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} |
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aux_read(chip, &buf, rem, &pos); |
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aux_read(chip, &oob_orig, BBM_SIZE, &pos); |
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aux_read(chip, &buf, pkt_size - rem, &pos); |
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aux_read(chip, &oob, ecc_size, &pos); |
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} |
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static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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const u8 *oob_orig = oob; |
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const int page_size = mtd->writesize; |
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const int ecc_size = chip->ecc.bytes; |
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const int pkt_size = chip->ecc.size; |
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int pos = 0; /* position within physical page */ |
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int rem = page_size; /* bytes remaining until BBM area */ |
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if (oob) |
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oob += BBM_SIZE; |
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aux_write(chip, &oob, METADATA_SIZE, &pos); |
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while (rem > pkt_size) { |
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aux_write(chip, &buf, pkt_size, &pos); |
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aux_write(chip, &oob, ecc_size, &pos); |
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rem = page_size - pos; |
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} |
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aux_write(chip, &buf, rem, &pos); |
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aux_write(chip, &oob_orig, BBM_SIZE, &pos); |
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aux_write(chip, &buf, pkt_size - rem, &pos); |
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aux_write(chip, &oob, ecc_size, &pos); |
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} |
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static int tango_read_page_raw(struct nand_chip *chip, u8 *buf, |
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int oob_required, int page) |
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{ |
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tango_select_target(chip, chip->cur_cs); |
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nand_read_page_op(chip, page, 0, NULL, 0); |
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raw_read(chip, buf, chip->oob_poi); |
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return 0; |
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} |
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static int tango_write_page_raw(struct nand_chip *chip, const u8 *buf, |
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int oob_required, int page) |
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{ |
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tango_select_target(chip, chip->cur_cs); |
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nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
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raw_write(chip, buf, chip->oob_poi); |
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return nand_prog_page_end_op(chip); |
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} |
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static int tango_read_oob(struct nand_chip *chip, int page) |
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{ |
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tango_select_target(chip, chip->cur_cs); |
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nand_read_page_op(chip, page, 0, NULL, 0); |
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raw_read(chip, NULL, chip->oob_poi); |
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return 0; |
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} |
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static int tango_write_oob(struct nand_chip *chip, int page) |
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{ |
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tango_select_target(chip, chip->cur_cs); |
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nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
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raw_write(chip, NULL, chip->oob_poi); |
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return nand_prog_page_end_op(chip); |
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} |
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static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct nand_ecc_ctrl *ecc = &chip->ecc; |
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if (idx >= ecc->steps) |
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return -ERANGE; |
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res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx; |
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res->length = ecc->bytes; |
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return 0; |
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} |
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static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res) |
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{ |
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return -ERANGE; /* no free space in spare area */ |
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} |
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static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = { |
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.ecc = oob_ecc, |
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.free = oob_free, |
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}; |
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static u32 to_ticks(int kHz, int ps) |
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{ |
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return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC); |
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} |
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static int tango_set_timings(struct nand_chip *chip, int csline, |
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const struct nand_interface_config *conf) |
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{ |
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const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf); |
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struct tango_nfc *nfc = to_tango_nfc(chip->controller); |
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struct tango_chip *tchip = to_tango_chip(chip); |
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u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr; |
|
int kHz = nfc->freq_kHz; |
|
|
|
if (IS_ERR(sdr)) |
|
return PTR_ERR(sdr); |
|
|
|
if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
|
return 0; |
|
|
|
Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max); |
|
Textw = to_ticks(kHz, sdr->tWB_max); |
|
Twc = to_ticks(kHz, sdr->tWC_min); |
|
Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min); |
|
|
|
Tacc = to_ticks(kHz, sdr->tREA_max); |
|
Thold = to_ticks(kHz, sdr->tREH_min); |
|
Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min); |
|
Textr = to_ticks(kHz, sdr->tRHZ_max); |
|
|
|
tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw); |
|
tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr); |
|
|
|
return 0; |
|
} |
|
|
|
static int tango_attach_chip(struct nand_chip *chip) |
|
{ |
|
struct nand_ecc_ctrl *ecc = &chip->ecc; |
|
|
|
ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; |
|
ecc->algo = NAND_ECC_ALGO_BCH; |
|
ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); |
|
|
|
ecc->read_page_raw = tango_read_page_raw; |
|
ecc->write_page_raw = tango_write_page_raw; |
|
ecc->read_page = tango_read_page; |
|
ecc->write_page = tango_write_page; |
|
ecc->read_oob = tango_read_oob; |
|
ecc->write_oob = tango_write_oob; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct nand_controller_ops tango_controller_ops = { |
|
.attach_chip = tango_attach_chip, |
|
.setup_interface = tango_set_timings, |
|
.exec_op = tango_exec_op, |
|
}; |
|
|
|
static int chip_init(struct device *dev, struct device_node *np) |
|
{ |
|
u32 cs; |
|
int err, res; |
|
struct mtd_info *mtd; |
|
struct nand_chip *chip; |
|
struct tango_chip *tchip; |
|
struct nand_ecc_ctrl *ecc; |
|
struct tango_nfc *nfc = dev_get_drvdata(dev); |
|
|
|
tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL); |
|
if (!tchip) |
|
return -ENOMEM; |
|
|
|
res = of_property_count_u32_elems(np, "reg"); |
|
if (res < 0) |
|
return res; |
|
|
|
if (res != 1) |
|
return -ENOTSUPP; /* Multi-CS chips are not supported */ |
|
|
|
err = of_property_read_u32_index(np, "reg", 0, &cs); |
|
if (err) |
|
return err; |
|
|
|
if (cs >= MAX_CS) |
|
return -EINVAL; |
|
|
|
chip = &tchip->nand_chip; |
|
ecc = &chip->ecc; |
|
mtd = nand_to_mtd(chip); |
|
|
|
chip->options = NAND_USES_DMA | |
|
NAND_NO_SUBPAGE_WRITE | |
|
NAND_WAIT_TCCS; |
|
chip->controller = &nfc->hw; |
|
tchip->base = nfc->pbus_base + (cs * 256); |
|
|
|
nand_set_flash_node(chip, np); |
|
mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops); |
|
mtd->dev.parent = dev; |
|
|
|
err = nand_scan(chip, 1); |
|
if (err) |
|
return err; |
|
|
|
tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE); |
|
tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength); |
|
tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength); |
|
tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE); |
|
|
|
err = mtd_device_register(mtd, NULL, 0); |
|
if (err) { |
|
nand_cleanup(chip); |
|
return err; |
|
} |
|
|
|
nfc->chips[cs] = tchip; |
|
|
|
return 0; |
|
} |
|
|
|
static int tango_nand_remove(struct platform_device *pdev) |
|
{ |
|
struct tango_nfc *nfc = platform_get_drvdata(pdev); |
|
struct nand_chip *chip; |
|
int cs, ret; |
|
|
|
dma_release_channel(nfc->chan); |
|
|
|
for (cs = 0; cs < MAX_CS; ++cs) { |
|
if (nfc->chips[cs]) { |
|
chip = &nfc->chips[cs]->nand_chip; |
|
ret = mtd_device_unregister(nand_to_mtd(chip)); |
|
WARN_ON(ret); |
|
nand_cleanup(chip); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int tango_nand_probe(struct platform_device *pdev) |
|
{ |
|
int err; |
|
struct clk *clk; |
|
struct resource *res; |
|
struct tango_nfc *nfc; |
|
struct device_node *np; |
|
|
|
nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); |
|
if (!nfc) |
|
return -ENOMEM; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
nfc->reg_base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(nfc->reg_base)) |
|
return PTR_ERR(nfc->reg_base); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
|
nfc->mem_base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(nfc->mem_base)) |
|
return PTR_ERR(nfc->mem_base); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
|
nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(nfc->pbus_base)) |
|
return PTR_ERR(nfc->pbus_base); |
|
|
|
writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE); |
|
|
|
clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(clk)) |
|
return PTR_ERR(clk); |
|
|
|
nfc->chan = dma_request_chan(&pdev->dev, "rxtx"); |
|
if (IS_ERR(nfc->chan)) |
|
return PTR_ERR(nfc->chan); |
|
|
|
platform_set_drvdata(pdev, nfc); |
|
nand_controller_init(&nfc->hw); |
|
nfc->hw.ops = &tango_controller_ops; |
|
nfc->freq_kHz = clk_get_rate(clk) / 1000; |
|
|
|
for_each_child_of_node(pdev->dev.of_node, np) { |
|
err = chip_init(&pdev->dev, np); |
|
if (err) { |
|
tango_nand_remove(pdev); |
|
of_node_put(np); |
|
return err; |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id tango_nand_ids[] = { |
|
{ .compatible = "sigma,smp8758-nand" }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, tango_nand_ids); |
|
|
|
static struct platform_driver tango_nand_driver = { |
|
.probe = tango_nand_probe, |
|
.remove = tango_nand_remove, |
|
.driver = { |
|
.name = "tango-nand", |
|
.of_match_table = tango_nand_ids, |
|
}, |
|
}; |
|
|
|
module_platform_driver(tango_nand_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Sigma Designs"); |
|
MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");
|
|
|