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721 lines
17 KiB
721 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2017 Free Electrons |
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* Copyright (C) 2017 NextThing Co |
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* |
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* Author: Boris Brezillon <[email protected]> |
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*/ |
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|
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#include <linux/sizes.h> |
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#include <linux/slab.h> |
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|
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#include "internals.h" |
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|
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#define NAND_HYNIX_CMD_SET_PARAMS 0x36 |
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#define NAND_HYNIX_CMD_APPLY_PARAMS 0x16 |
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|
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#define NAND_HYNIX_1XNM_RR_REPEAT 8 |
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|
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/** |
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* struct hynix_read_retry - read-retry data |
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* @nregs: number of register to set when applying a new read-retry mode |
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* @regs: register offsets (NAND chip dependent) |
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* @values: array of values to set in registers. The array size is equal to |
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* (nregs * nmodes) |
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*/ |
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struct hynix_read_retry { |
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int nregs; |
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const u8 *regs; |
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u8 values[]; |
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}; |
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|
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/** |
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* struct hynix_nand - private Hynix NAND struct |
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* @nand_technology: manufacturing process expressed in picometer |
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* @read_retry: read-retry information |
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*/ |
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struct hynix_nand { |
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const struct hynix_read_retry *read_retry; |
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}; |
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|
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/** |
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* struct hynix_read_retry_otp - structure describing how the read-retry OTP |
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* area |
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* @nregs: number of hynix private registers to set before reading the reading |
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* the OTP area |
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* @regs: registers that should be configured |
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* @values: values that should be set in regs |
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* @page: the address to pass to the READ_PAGE command. Depends on the NAND |
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* chip |
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* @size: size of the read-retry OTP section |
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*/ |
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struct hynix_read_retry_otp { |
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int nregs; |
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const u8 *regs; |
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const u8 *values; |
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int page; |
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int size; |
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}; |
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|
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static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip) |
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{ |
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u8 jedecid[5] = { }; |
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int ret; |
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|
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ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid)); |
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if (ret) |
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return false; |
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|
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return !strncmp("JEDEC", jedecid, sizeof(jedecid)); |
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} |
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|
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static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd) |
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{ |
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if (nand_has_exec_op(chip)) { |
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struct nand_op_instr instrs[] = { |
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NAND_OP_CMD(cmd, 0), |
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}; |
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struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); |
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|
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return nand_exec_op(chip, &op); |
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} |
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|
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chip->legacy.cmdfunc(chip, cmd, -1, -1); |
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return 0; |
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} |
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static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val) |
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{ |
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u16 column = ((u16)addr << 8) | addr; |
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|
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if (nand_has_exec_op(chip)) { |
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struct nand_op_instr instrs[] = { |
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NAND_OP_ADDR(1, &addr, 0), |
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NAND_OP_8BIT_DATA_OUT(1, &val, 0), |
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}; |
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struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); |
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|
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return nand_exec_op(chip, &op); |
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} |
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chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1); |
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chip->legacy.write_byte(chip, val); |
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|
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return 0; |
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} |
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static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode) |
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{ |
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struct hynix_nand *hynix = nand_get_manufacturer_data(chip); |
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const u8 *values; |
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int i, ret; |
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values = hynix->read_retry->values + |
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(retry_mode * hynix->read_retry->nregs); |
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|
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/* Enter 'Set Hynix Parameters' mode */ |
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ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); |
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if (ret) |
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return ret; |
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|
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/* |
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* Configure the NAND in the requested read-retry mode. |
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* This is done by setting pre-defined values in internal NAND |
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* registers. |
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* |
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* The set of registers is NAND specific, and the values are either |
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* predefined or extracted from an OTP area on the NAND (values are |
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* probably tweaked at production in this case). |
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*/ |
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for (i = 0; i < hynix->read_retry->nregs; i++) { |
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ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i], |
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values[i]); |
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if (ret) |
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return ret; |
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} |
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|
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/* Apply the new settings. */ |
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return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); |
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} |
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|
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/** |
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* hynix_get_majority - get the value that is occurring the most in a given |
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* set of values |
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* @in: the array of values to test |
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* @repeat: the size of the in array |
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* @out: pointer used to store the output value |
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* |
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* This function implements the 'majority check' logic that is supposed to |
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* overcome the unreliability of MLC NANDs when reading the OTP area storing |
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* the read-retry parameters. |
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* |
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* It's based on a pretty simple assumption: if we repeat the same value |
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* several times and then take the one that is occurring the most, we should |
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* find the correct value. |
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* Let's hope this dummy algorithm prevents us from losing the read-retry |
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* parameters. |
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*/ |
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static int hynix_get_majority(const u8 *in, int repeat, u8 *out) |
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{ |
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int i, j, half = repeat / 2; |
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|
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/* |
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* We only test the first half of the in array because we must ensure |
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* that the value is at least occurring repeat / 2 times. |
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* |
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* This loop is suboptimal since we may count the occurrences of the |
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* same value several time, but we are doing that on small sets, which |
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* makes it acceptable. |
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*/ |
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for (i = 0; i < half; i++) { |
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int cnt = 0; |
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u8 val = in[i]; |
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|
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/* Count all values that are matching the one at index i. */ |
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for (j = i + 1; j < repeat; j++) { |
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if (in[j] == val) |
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cnt++; |
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} |
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|
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/* We found a value occurring more than repeat / 2. */ |
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if (cnt > half) { |
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*out = val; |
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return 0; |
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} |
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} |
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return -EIO; |
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} |
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static int hynix_read_rr_otp(struct nand_chip *chip, |
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const struct hynix_read_retry_otp *info, |
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void *buf) |
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{ |
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int i, ret; |
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|
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ret = nand_reset_op(chip); |
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if (ret) |
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return ret; |
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ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); |
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if (ret) |
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return ret; |
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|
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for (i = 0; i < info->nregs; i++) { |
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ret = hynix_nand_reg_write_op(chip, info->regs[i], |
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info->values[i]); |
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if (ret) |
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return ret; |
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} |
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ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); |
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if (ret) |
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return ret; |
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/* Sequence to enter OTP mode? */ |
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ret = hynix_nand_cmd_op(chip, 0x17); |
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if (ret) |
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return ret; |
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ret = hynix_nand_cmd_op(chip, 0x4); |
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if (ret) |
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return ret; |
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ret = hynix_nand_cmd_op(chip, 0x19); |
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if (ret) |
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return ret; |
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/* Now read the page */ |
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ret = nand_read_page_op(chip, info->page, 0, buf, info->size); |
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if (ret) |
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return ret; |
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|
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/* Put everything back to normal */ |
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ret = nand_reset_op(chip); |
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if (ret) |
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return ret; |
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ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); |
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if (ret) |
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return ret; |
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ret = hynix_nand_reg_write_op(chip, 0x38, 0); |
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if (ret) |
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return ret; |
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ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); |
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if (ret) |
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return ret; |
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return nand_read_page_op(chip, 0, 0, NULL, 0); |
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} |
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#define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0 |
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#define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8 |
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#define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \ |
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(16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize))) |
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static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs, |
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int mode, int reg, bool inv, u8 *val) |
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{ |
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u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT]; |
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int val_offs = (mode * nregs) + reg; |
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int set_size = nmodes * nregs; |
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int i, ret; |
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for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) { |
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int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv); |
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tmp[i] = buf[val_offs + set_offs]; |
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} |
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ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val); |
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if (ret) |
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return ret; |
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if (inv) |
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*val = ~*val; |
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return 0; |
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} |
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static u8 hynix_1xnm_mlc_read_retry_regs[] = { |
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0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf |
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}; |
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static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip, |
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const struct hynix_read_retry_otp *info) |
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{ |
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struct hynix_nand *hynix = nand_get_manufacturer_data(chip); |
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struct hynix_read_retry *rr = NULL; |
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int ret, i, j; |
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u8 nregs, nmodes; |
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u8 *buf; |
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buf = kmalloc(info->size, GFP_KERNEL); |
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if (!buf) |
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return -ENOMEM; |
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ret = hynix_read_rr_otp(chip, info, buf); |
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if (ret) |
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goto out; |
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ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT, |
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&nmodes); |
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if (ret) |
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goto out; |
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ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT, |
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NAND_HYNIX_1XNM_RR_REPEAT, |
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&nregs); |
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if (ret) |
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goto out; |
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rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL); |
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if (!rr) { |
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ret = -ENOMEM; |
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goto out; |
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} |
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for (i = 0; i < nmodes; i++) { |
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for (j = 0; j < nregs; j++) { |
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u8 *val = rr->values + (i * nregs); |
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ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j, |
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false, val); |
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if (!ret) |
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continue; |
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ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j, |
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true, val); |
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if (ret) |
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goto out; |
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} |
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} |
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rr->nregs = nregs; |
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rr->regs = hynix_1xnm_mlc_read_retry_regs; |
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hynix->read_retry = rr; |
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chip->ops.setup_read_retry = hynix_nand_setup_read_retry; |
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chip->read_retries = nmodes; |
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out: |
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kfree(buf); |
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if (ret) |
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kfree(rr); |
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return ret; |
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} |
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static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 }; |
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static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 }; |
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|
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static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = { |
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{ |
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.nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs), |
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.regs = hynix_mlc_1xnm_rr_otp_regs, |
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.values = hynix_mlc_1xnm_rr_otp_values, |
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.page = 0x21f, |
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.size = 784 |
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}, |
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{ |
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.nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs), |
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.regs = hynix_mlc_1xnm_rr_otp_regs, |
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.values = hynix_mlc_1xnm_rr_otp_values, |
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.page = 0x200, |
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.size = 528, |
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}, |
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}; |
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|
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static int hynix_nand_rr_init(struct nand_chip *chip) |
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{ |
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int i, ret = 0; |
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bool valid_jedecid; |
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|
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valid_jedecid = hynix_nand_has_valid_jedecid(chip); |
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|
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/* |
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* We only support read-retry for 1xnm NANDs, and those NANDs all |
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* expose a valid JEDEC ID. |
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*/ |
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if (valid_jedecid) { |
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u8 nand_tech = chip->id.data[5] >> 4; |
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|
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/* 1xnm technology */ |
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if (nand_tech == 4) { |
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for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps); |
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i++) { |
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/* |
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* FIXME: Hynix recommend to copy the |
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* read-retry OTP area into a normal page. |
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*/ |
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ret = hynix_mlc_1xnm_rr_init(chip, |
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hynix_mlc_1xnm_rr_otps); |
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if (!ret) |
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break; |
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} |
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} |
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} |
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|
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if (ret) |
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pr_warn("failed to initialize read-retry infrastructure"); |
|
|
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return 0; |
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} |
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|
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static void hynix_nand_extract_oobsize(struct nand_chip *chip, |
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bool valid_jedecid) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct nand_memory_organization *memorg; |
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u8 oobsize; |
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|
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memorg = nanddev_get_memorg(&chip->base); |
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|
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oobsize = ((chip->id.data[3] >> 2) & 0x3) | |
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((chip->id.data[3] >> 4) & 0x4); |
|
|
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if (valid_jedecid) { |
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switch (oobsize) { |
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case 0: |
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memorg->oobsize = 2048; |
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break; |
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case 1: |
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memorg->oobsize = 1664; |
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break; |
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case 2: |
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memorg->oobsize = 1024; |
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break; |
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case 3: |
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memorg->oobsize = 640; |
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break; |
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default: |
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/* |
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* We should never reach this case, but if that |
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* happens, this probably means Hynix decided to use |
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* a different extended ID format, and we should find |
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* a way to support it. |
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*/ |
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WARN(1, "Invalid OOB size"); |
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break; |
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} |
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} else { |
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switch (oobsize) { |
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case 0: |
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memorg->oobsize = 128; |
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break; |
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case 1: |
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memorg->oobsize = 224; |
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break; |
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case 2: |
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memorg->oobsize = 448; |
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break; |
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case 3: |
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memorg->oobsize = 64; |
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break; |
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case 4: |
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memorg->oobsize = 32; |
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break; |
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case 5: |
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memorg->oobsize = 16; |
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break; |
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case 6: |
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memorg->oobsize = 640; |
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break; |
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default: |
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/* |
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* We should never reach this case, but if that |
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* happens, this probably means Hynix decided to use |
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* a different extended ID format, and we should find |
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* a way to support it. |
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*/ |
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WARN(1, "Invalid OOB size"); |
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break; |
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} |
|
|
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/* |
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* The datasheet of H27UCG8T2BTR mentions that the "Redundant |
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* Area Size" is encoded "per 8KB" (page size). This chip uses |
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* a page size of 16KiB. The datasheet mentions an OOB size of |
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* 1.280 bytes, but the OOB size encoded in the ID bytes (using |
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* the existing logic above) is 640 bytes. |
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* Update the OOB size for this chip by taking the value |
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* determined above and scaling it to the actual page size (so |
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* the actual OOB size for this chip is: 640 * 16k / 8k). |
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*/ |
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if (chip->id.data[1] == 0xde) |
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memorg->oobsize *= memorg->pagesize / SZ_8K; |
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} |
|
|
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mtd->oobsize = memorg->oobsize; |
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} |
|
|
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static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, |
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bool valid_jedecid) |
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{ |
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struct nand_device *base = &chip->base; |
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struct nand_ecc_props requirements = {}; |
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u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; |
|
|
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if (valid_jedecid) { |
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/* Reference: H27UCG8T2E datasheet */ |
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requirements.step_size = 1024; |
|
|
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switch (ecc_level) { |
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case 0: |
|
requirements.step_size = 0; |
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requirements.strength = 0; |
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break; |
|
case 1: |
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requirements.strength = 4; |
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break; |
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case 2: |
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requirements.strength = 24; |
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break; |
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case 3: |
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requirements.strength = 32; |
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break; |
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case 4: |
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requirements.strength = 40; |
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break; |
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case 5: |
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requirements.strength = 50; |
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break; |
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case 6: |
|
requirements.strength = 60; |
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break; |
|
default: |
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/* |
|
* We should never reach this case, but if that |
|
* happens, this probably means Hynix decided to use |
|
* a different extended ID format, and we should find |
|
* a way to support it. |
|
*/ |
|
WARN(1, "Invalid ECC requirements"); |
|
} |
|
} else { |
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/* |
|
* The ECC requirements field meaning depends on the |
|
* NAND technology. |
|
*/ |
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u8 nand_tech = chip->id.data[5] & 0x7; |
|
|
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if (nand_tech < 3) { |
|
/* > 26nm, reference: H27UBG8T2A datasheet */ |
|
if (ecc_level < 5) { |
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requirements.step_size = 512; |
|
requirements.strength = 1 << ecc_level; |
|
} else if (ecc_level < 7) { |
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if (ecc_level == 5) |
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requirements.step_size = 2048; |
|
else |
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requirements.step_size = 1024; |
|
requirements.strength = 24; |
|
} else { |
|
/* |
|
* We should never reach this case, but if that |
|
* happens, this probably means Hynix decided |
|
* to use a different extended ID format, and |
|
* we should find a way to support it. |
|
*/ |
|
WARN(1, "Invalid ECC requirements"); |
|
} |
|
} else { |
|
/* <= 26nm, reference: H27UBG8T2B datasheet */ |
|
if (!ecc_level) { |
|
requirements.step_size = 0; |
|
requirements.strength = 0; |
|
} else if (ecc_level < 5) { |
|
requirements.step_size = 512; |
|
requirements.strength = 1 << (ecc_level - 1); |
|
} else { |
|
requirements.step_size = 1024; |
|
requirements.strength = 24 + |
|
(8 * (ecc_level - 5)); |
|
} |
|
} |
|
} |
|
|
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nanddev_set_ecc_requirements(base, &requirements); |
|
} |
|
|
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static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip, |
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bool valid_jedecid) |
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{ |
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u8 nand_tech; |
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|
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/* We need scrambling on all TLC NANDs*/ |
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if (nanddev_bits_per_cell(&chip->base) > 2) |
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chip->options |= NAND_NEED_SCRAMBLING; |
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|
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/* And on MLC NANDs with sub-3xnm process */ |
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if (valid_jedecid) { |
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nand_tech = chip->id.data[5] >> 4; |
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|
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/* < 3xnm */ |
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if (nand_tech > 0) |
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chip->options |= NAND_NEED_SCRAMBLING; |
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} else { |
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nand_tech = chip->id.data[5] & 0x7; |
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|
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/* < 32nm */ |
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if (nand_tech > 2) |
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chip->options |= NAND_NEED_SCRAMBLING; |
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} |
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} |
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|
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static void hynix_nand_decode_id(struct nand_chip *chip) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct nand_memory_organization *memorg; |
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bool valid_jedecid; |
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u8 tmp; |
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|
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memorg = nanddev_get_memorg(&chip->base); |
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|
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/* |
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* Exclude all SLC NANDs from this advanced detection scheme. |
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* According to the ranges defined in several datasheets, it might |
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* appear that even SLC NANDs could fall in this extended ID scheme. |
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* If that the case rework the test to let SLC NANDs go through the |
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* detection process. |
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*/ |
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if (chip->id.len < 6 || nand_is_slc(chip)) { |
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nand_decode_ext_id(chip); |
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return; |
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} |
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|
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/* Extract pagesize */ |
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memorg->pagesize = 2048 << (chip->id.data[3] & 0x03); |
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mtd->writesize = memorg->pagesize; |
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|
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tmp = (chip->id.data[3] >> 4) & 0x3; |
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/* |
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* When bit7 is set that means we start counting at 1MiB, otherwise |
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* we start counting at 128KiB and shift this value the content of |
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* ID[3][4:5]. |
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* The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in |
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* this case the erasesize is set to 768KiB. |
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*/ |
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if (chip->id.data[3] & 0x80) { |
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memorg->pages_per_eraseblock = (SZ_1M << tmp) / |
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memorg->pagesize; |
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mtd->erasesize = SZ_1M << tmp; |
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} else if (tmp == 3) { |
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memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) / |
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memorg->pagesize; |
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mtd->erasesize = SZ_512K + SZ_256K; |
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} else { |
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memorg->pages_per_eraseblock = (SZ_128K << tmp) / |
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memorg->pagesize; |
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mtd->erasesize = SZ_128K << tmp; |
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} |
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|
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/* |
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* Modern Toggle DDR NANDs have a valid JEDECID even though they are |
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* not exposing a valid JEDEC parameter table. |
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* These NANDs use a different NAND ID scheme. |
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*/ |
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valid_jedecid = hynix_nand_has_valid_jedecid(chip); |
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|
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hynix_nand_extract_oobsize(chip, valid_jedecid); |
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hynix_nand_extract_ecc_requirements(chip, valid_jedecid); |
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hynix_nand_extract_scrambling_requirements(chip, valid_jedecid); |
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} |
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|
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static void hynix_nand_cleanup(struct nand_chip *chip) |
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{ |
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struct hynix_nand *hynix = nand_get_manufacturer_data(chip); |
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|
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if (!hynix) |
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return; |
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|
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kfree(hynix->read_retry); |
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kfree(hynix); |
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nand_set_manufacturer_data(chip, NULL); |
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} |
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|
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static int |
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h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip, |
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struct nand_interface_config *iface) |
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{ |
|
onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4); |
|
|
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return nand_choose_best_sdr_timings(chip, iface, NULL); |
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} |
|
|
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static int hynix_nand_init(struct nand_chip *chip) |
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{ |
|
struct hynix_nand *hynix; |
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int ret; |
|
|
|
if (!nand_is_slc(chip)) |
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chip->options |= NAND_BBM_LASTPAGE; |
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else |
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE; |
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|
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hynix = kzalloc(sizeof(*hynix), GFP_KERNEL); |
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if (!hynix) |
|
return -ENOMEM; |
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|
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nand_set_manufacturer_data(chip, hynix); |
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|
|
if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model, |
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sizeof("H27UCG8T2ATR-BC") - 1)) |
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chip->ops.choose_interface_config = |
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h27ucg8t2atrbc_choose_interface_config; |
|
|
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ret = hynix_nand_rr_init(chip); |
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if (ret) |
|
hynix_nand_cleanup(chip); |
|
|
|
return ret; |
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} |
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|
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const struct nand_manufacturer_ops hynix_nand_manuf_ops = { |
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.detect = hynix_nand_decode_id, |
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.init = hynix_nand_init, |
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.cleanup = hynix_nand_cleanup, |
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};
|
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