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53 lines
1.4 KiB
53 lines
1.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2017 Free Electrons |
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* Copyright (C) 2017 NextThing Co |
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* |
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* Author: Boris Brezillon <[email protected]> |
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*/ |
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#include "internals.h" |
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static void amd_nand_decode_id(struct nand_chip *chip) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct nand_memory_organization *memorg; |
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memorg = nanddev_get_memorg(&chip->base); |
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nand_decode_ext_id(chip); |
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/* |
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* Check for Spansion/AMD ID + repeating 5th, 6th byte since |
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* some Spansion chips have erasesize that conflicts with size |
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* listed in nand_ids table. |
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* Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39) |
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*/ |
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if (chip->id.data[4] != 0x00 && chip->id.data[5] == 0x00 && |
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chip->id.data[6] == 0x00 && chip->id.data[7] == 0x00 && |
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memorg->pagesize == 512) { |
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memorg->pages_per_eraseblock = 256; |
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memorg->pages_per_eraseblock <<= ((chip->id.data[3] & 0x03) << 1); |
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mtd->erasesize = memorg->pages_per_eraseblock * |
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memorg->pagesize; |
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} |
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} |
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static int amd_nand_init(struct nand_chip *chip) |
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{ |
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if (nand_is_slc(chip)) |
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/* |
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* According to the datasheet of some Cypress SLC NANDs, |
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* the bad block markers can be in the first, second or last |
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* page of a block. So let's check all three locations. |
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*/ |
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE | |
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NAND_BBM_LASTPAGE; |
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return 0; |
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} |
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const struct nand_manufacturer_ops amd_nand_manuf_ops = { |
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.detect = amd_nand_decode_id, |
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.init = amd_nand_init, |
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};
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