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909 lines
24 KiB
909 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for NAND MLC Controller in LPC32xx |
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* |
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* Author: Roland Stigge <[email protected]> |
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* |
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* Copyright © 2011 WORK Microwave GmbH |
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* Copyright © 2011, 2012 Roland Stigge |
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* |
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* NAND Flash Controller Operation: |
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* - Read: Auto Decode |
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* - Write: Auto Encode |
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* - Tested Page Sizes: 2048, 4096 |
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*/ |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/delay.h> |
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#include <linux/completion.h> |
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#include <linux/interrupt.h> |
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#include <linux/of.h> |
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#include <linux/of_gpio.h> |
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#include <linux/mtd/lpc32xx_mlc.h> |
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#include <linux/io.h> |
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#include <linux/mm.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmaengine.h> |
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#define DRV_NAME "lpc32xx_mlc" |
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/********************************************************************** |
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* MLC NAND controller register offsets |
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**********************************************************************/ |
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#define MLC_BUFF(x) (x + 0x00000) |
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#define MLC_DATA(x) (x + 0x08000) |
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#define MLC_CMD(x) (x + 0x10000) |
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#define MLC_ADDR(x) (x + 0x10004) |
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#define MLC_ECC_ENC_REG(x) (x + 0x10008) |
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#define MLC_ECC_DEC_REG(x) (x + 0x1000C) |
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#define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010) |
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#define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014) |
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#define MLC_RPR(x) (x + 0x10018) |
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#define MLC_WPR(x) (x + 0x1001C) |
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#define MLC_RUBP(x) (x + 0x10020) |
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#define MLC_ROBP(x) (x + 0x10024) |
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#define MLC_SW_WP_ADD_LOW(x) (x + 0x10028) |
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#define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C) |
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#define MLC_ICR(x) (x + 0x10030) |
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#define MLC_TIME_REG(x) (x + 0x10034) |
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#define MLC_IRQ_MR(x) (x + 0x10038) |
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#define MLC_IRQ_SR(x) (x + 0x1003C) |
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#define MLC_LOCK_PR(x) (x + 0x10044) |
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#define MLC_ISR(x) (x + 0x10048) |
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#define MLC_CEH(x) (x + 0x1004C) |
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/********************************************************************** |
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* MLC_CMD bit definitions |
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**********************************************************************/ |
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#define MLCCMD_RESET 0xFF |
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/********************************************************************** |
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* MLC_ICR bit definitions |
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**********************************************************************/ |
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#define MLCICR_WPROT (1 << 3) |
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#define MLCICR_LARGEBLOCK (1 << 2) |
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#define MLCICR_LONGADDR (1 << 1) |
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#define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */ |
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/********************************************************************** |
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* MLC_TIME_REG bit definitions |
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**********************************************************************/ |
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#define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24) |
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#define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19) |
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#define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16) |
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#define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12) |
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#define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8) |
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#define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4) |
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#define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0) |
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/********************************************************************** |
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* MLC_IRQ_MR and MLC_IRQ_SR bit definitions |
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**********************************************************************/ |
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#define MLCIRQ_NAND_READY (1 << 5) |
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#define MLCIRQ_CONTROLLER_READY (1 << 4) |
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#define MLCIRQ_DECODE_FAILURE (1 << 3) |
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#define MLCIRQ_DECODE_ERROR (1 << 2) |
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#define MLCIRQ_ECC_READY (1 << 1) |
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#define MLCIRQ_WRPROT_FAULT (1 << 0) |
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/********************************************************************** |
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* MLC_LOCK_PR bit definitions |
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**********************************************************************/ |
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#define MLCLOCKPR_MAGIC 0xA25E |
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/********************************************************************** |
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* MLC_ISR bit definitions |
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**********************************************************************/ |
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#define MLCISR_DECODER_FAILURE (1 << 6) |
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#define MLCISR_ERRORS ((1 << 4) | (1 << 5)) |
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#define MLCISR_ERRORS_DETECTED (1 << 3) |
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#define MLCISR_ECC_READY (1 << 2) |
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#define MLCISR_CONTROLLER_READY (1 << 1) |
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#define MLCISR_NAND_READY (1 << 0) |
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/********************************************************************** |
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* MLC_CEH bit definitions |
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**********************************************************************/ |
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#define MLCCEH_NORMAL (1 << 0) |
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struct lpc32xx_nand_cfg_mlc { |
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uint32_t tcea_delay; |
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uint32_t busy_delay; |
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uint32_t nand_ta; |
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uint32_t rd_high; |
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uint32_t rd_low; |
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uint32_t wr_high; |
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uint32_t wr_low; |
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int wp_gpio; |
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struct mtd_partition *parts; |
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unsigned num_parts; |
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}; |
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static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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if (section >= nand_chip->ecc.steps) |
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return -ERANGE; |
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oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes; |
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oobregion->length = nand_chip->ecc.bytes; |
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return 0; |
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} |
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static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *nand_chip = mtd_to_nand(mtd); |
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if (section >= nand_chip->ecc.steps) |
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return -ERANGE; |
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oobregion->offset = 16 * section; |
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oobregion->length = 16 - nand_chip->ecc.bytes; |
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return 0; |
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} |
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static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = { |
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.ecc = lpc32xx_ooblayout_ecc, |
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.free = lpc32xx_ooblayout_free, |
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}; |
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static struct nand_bbt_descr lpc32xx_nand_bbt = { |
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.options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | |
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NAND_BBT_WRITE, |
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.pages = { 524224, 0, 0, 0, 0, 0, 0, 0 }, |
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}; |
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static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = { |
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.options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB | |
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NAND_BBT_WRITE, |
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.pages = { 524160, 0, 0, 0, 0, 0, 0, 0 }, |
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}; |
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struct lpc32xx_nand_host { |
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struct platform_device *pdev; |
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struct nand_chip nand_chip; |
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struct lpc32xx_mlc_platform_data *pdata; |
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struct clk *clk; |
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void __iomem *io_base; |
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int irq; |
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struct lpc32xx_nand_cfg_mlc *ncfg; |
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struct completion comp_nand; |
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struct completion comp_controller; |
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uint32_t llptr; |
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/* |
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* Physical addresses of ECC buffer, DMA data buffers, OOB data buffer |
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*/ |
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dma_addr_t oob_buf_phy; |
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/* |
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* Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer |
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*/ |
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uint8_t *oob_buf; |
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/* Physical address of DMA base address */ |
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dma_addr_t io_base_phy; |
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struct completion comp_dma; |
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struct dma_chan *dma_chan; |
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struct dma_slave_config dma_slave_config; |
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struct scatterlist sgl; |
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uint8_t *dma_buf; |
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uint8_t *dummy_buf; |
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int mlcsubpages; /* number of 512bytes-subpages */ |
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}; |
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/* |
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* Activate/Deactivate DMA Operation: |
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* |
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* Using the PL080 DMA Controller for transferring the 512 byte subpages |
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* instead of doing readl() / writel() in a loop slows it down significantly. |
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* Measurements via getnstimeofday() upon 512 byte subpage reads reveal: |
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* |
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* - readl() of 128 x 32 bits in a loop: ~20us |
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* - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us |
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* - DMA read of 512 bytes (32 bit, no bursts): ~100us |
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* |
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* This applies to the transfer itself. In the DMA case: only the |
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* wait_for_completion() (DMA setup _not_ included). |
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* |
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* Note that the 512 bytes subpage transfer is done directly from/to a |
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* FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a |
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* 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND |
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* controller transferring data between its internal buffer to/from the NAND |
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* chip.) |
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* |
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* Therefore, using the PL080 DMA is disabled by default, for now. |
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* |
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*/ |
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static int use_dma; |
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static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host) |
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{ |
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uint32_t clkrate, tmp; |
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/* Reset MLC controller */ |
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writel(MLCCMD_RESET, MLC_CMD(host->io_base)); |
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udelay(1000); |
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/* Get base clock for MLC block */ |
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clkrate = clk_get_rate(host->clk); |
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if (clkrate == 0) |
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clkrate = 104000000; |
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/* Unlock MLC_ICR |
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* (among others, will be locked again automatically) */ |
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writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); |
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/* Configure MLC Controller: Large Block, 5 Byte Address */ |
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tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR; |
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writel(tmp, MLC_ICR(host->io_base)); |
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/* Unlock MLC_TIME_REG |
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* (among others, will be locked again automatically) */ |
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writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); |
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/* Compute clock setup values, see LPC and NAND manual */ |
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tmp = 0; |
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tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1); |
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tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1); |
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tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1); |
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tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1); |
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tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low); |
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tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1); |
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tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low); |
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writel(tmp, MLC_TIME_REG(host->io_base)); |
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/* Enable IRQ for CONTROLLER_READY and NAND_READY */ |
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writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY, |
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MLC_IRQ_MR(host->io_base)); |
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/* Normal nCE operation: nCE controlled by controller */ |
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writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); |
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} |
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/* |
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* Hardware specific access to control lines |
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*/ |
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static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd, |
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unsigned int ctrl) |
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{ |
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struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip); |
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if (cmd != NAND_CMD_NONE) { |
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if (ctrl & NAND_CLE) |
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writel(cmd, MLC_CMD(host->io_base)); |
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else |
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writel(cmd, MLC_ADDR(host->io_base)); |
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} |
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} |
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/* |
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* Read Device Ready (NAND device _and_ controller ready) |
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*/ |
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static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip) |
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{ |
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struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip); |
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if ((readb(MLC_ISR(host->io_base)) & |
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(MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) == |
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(MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) |
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return 1; |
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return 0; |
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} |
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static irqreturn_t lpc3xxx_nand_irq(int irq, struct lpc32xx_nand_host *host) |
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{ |
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uint8_t sr; |
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/* Clear interrupt flag by reading status */ |
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sr = readb(MLC_IRQ_SR(host->io_base)); |
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if (sr & MLCIRQ_NAND_READY) |
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complete(&host->comp_nand); |
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if (sr & MLCIRQ_CONTROLLER_READY) |
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complete(&host->comp_controller); |
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return IRQ_HANDLED; |
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} |
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static int lpc32xx_waitfunc_nand(struct nand_chip *chip) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
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if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY) |
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goto exit; |
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wait_for_completion(&host->comp_nand); |
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while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) { |
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/* Seems to be delayed sometimes by controller */ |
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dev_dbg(&mtd->dev, "Warning: NAND not ready.\n"); |
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cpu_relax(); |
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} |
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exit: |
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return NAND_STATUS_READY; |
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} |
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static int lpc32xx_waitfunc_controller(struct nand_chip *chip) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
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if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY) |
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goto exit; |
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wait_for_completion(&host->comp_controller); |
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while (!(readb(MLC_ISR(host->io_base)) & |
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MLCISR_CONTROLLER_READY)) { |
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dev_dbg(&mtd->dev, "Warning: Controller not ready.\n"); |
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cpu_relax(); |
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} |
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exit: |
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return NAND_STATUS_READY; |
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} |
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static int lpc32xx_waitfunc(struct nand_chip *chip) |
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{ |
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lpc32xx_waitfunc_nand(chip); |
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lpc32xx_waitfunc_controller(chip); |
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return NAND_STATUS_READY; |
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} |
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/* |
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* Enable NAND write protect |
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*/ |
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static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host) |
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{ |
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if (gpio_is_valid(host->ncfg->wp_gpio)) |
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gpio_set_value(host->ncfg->wp_gpio, 0); |
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} |
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/* |
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* Disable NAND write protect |
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*/ |
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static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host) |
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{ |
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if (gpio_is_valid(host->ncfg->wp_gpio)) |
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gpio_set_value(host->ncfg->wp_gpio, 1); |
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} |
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static void lpc32xx_dma_complete_func(void *completion) |
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{ |
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complete(completion); |
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} |
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static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len, |
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enum dma_transfer_direction dir) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
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struct dma_async_tx_descriptor *desc; |
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int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
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int res; |
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sg_init_one(&host->sgl, mem, len); |
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res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1, |
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DMA_BIDIRECTIONAL); |
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if (res != 1) { |
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dev_err(mtd->dev.parent, "Failed to map sg list\n"); |
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return -ENXIO; |
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} |
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desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir, |
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flags); |
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if (!desc) { |
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dev_err(mtd->dev.parent, "Failed to prepare slave sg\n"); |
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goto out1; |
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} |
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init_completion(&host->comp_dma); |
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desc->callback = lpc32xx_dma_complete_func; |
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desc->callback_param = &host->comp_dma; |
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dmaengine_submit(desc); |
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dma_async_issue_pending(host->dma_chan); |
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wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000)); |
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dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
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DMA_BIDIRECTIONAL); |
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return 0; |
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out1: |
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dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1, |
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DMA_BIDIRECTIONAL); |
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return -ENXIO; |
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} |
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static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf, |
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int oob_required, int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
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int i, j; |
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uint8_t *oobbuf = chip->oob_poi; |
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uint32_t mlc_isr; |
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int res; |
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uint8_t *dma_buf; |
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bool dma_mapped; |
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if ((void *)buf <= high_memory) { |
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dma_buf = buf; |
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dma_mapped = true; |
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} else { |
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dma_buf = host->dma_buf; |
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dma_mapped = false; |
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} |
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/* Writing Command and Address */ |
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nand_read_page_op(chip, page, 0, NULL, 0); |
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/* For all sub-pages */ |
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for (i = 0; i < host->mlcsubpages; i++) { |
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/* Start Auto Decode Command */ |
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writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base)); |
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/* Wait for Controller Ready */ |
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lpc32xx_waitfunc_controller(chip); |
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/* Check ECC Error status */ |
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mlc_isr = readl(MLC_ISR(host->io_base)); |
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if (mlc_isr & MLCISR_DECODER_FAILURE) { |
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mtd->ecc_stats.failed++; |
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dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__); |
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} else if (mlc_isr & MLCISR_ERRORS_DETECTED) { |
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mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1; |
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} |
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/* Read 512 + 16 Bytes */ |
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if (use_dma) { |
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res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, |
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DMA_DEV_TO_MEM); |
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if (res) |
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return res; |
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} else { |
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for (j = 0; j < (512 >> 2); j++) { |
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*((uint32_t *)(buf)) = |
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readl(MLC_BUFF(host->io_base)); |
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buf += 4; |
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} |
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} |
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for (j = 0; j < (16 >> 2); j++) { |
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*((uint32_t *)(oobbuf)) = |
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readl(MLC_BUFF(host->io_base)); |
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oobbuf += 4; |
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} |
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} |
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if (use_dma && !dma_mapped) |
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memcpy(buf, dma_buf, mtd->writesize); |
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return 0; |
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} |
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static int lpc32xx_write_page_lowlevel(struct nand_chip *chip, |
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const uint8_t *buf, int oob_required, |
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int page) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
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const uint8_t *oobbuf = chip->oob_poi; |
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uint8_t *dma_buf = (uint8_t *)buf; |
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int res; |
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int i, j; |
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|
|
if (use_dma && (void *)buf >= high_memory) { |
|
dma_buf = host->dma_buf; |
|
memcpy(dma_buf, buf, mtd->writesize); |
|
} |
|
|
|
nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
|
|
|
for (i = 0; i < host->mlcsubpages; i++) { |
|
/* Start Encode */ |
|
writeb(0x00, MLC_ECC_ENC_REG(host->io_base)); |
|
|
|
/* Write 512 + 6 Bytes to Buffer */ |
|
if (use_dma) { |
|
res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512, |
|
DMA_MEM_TO_DEV); |
|
if (res) |
|
return res; |
|
} else { |
|
for (j = 0; j < (512 >> 2); j++) { |
|
writel(*((uint32_t *)(buf)), |
|
MLC_BUFF(host->io_base)); |
|
buf += 4; |
|
} |
|
} |
|
writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base)); |
|
oobbuf += 4; |
|
writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base)); |
|
oobbuf += 12; |
|
|
|
/* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */ |
|
writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base)); |
|
|
|
/* Wait for Controller Ready */ |
|
lpc32xx_waitfunc_controller(chip); |
|
} |
|
|
|
return nand_prog_page_end_op(chip); |
|
} |
|
|
|
static int lpc32xx_read_oob(struct nand_chip *chip, int page) |
|
{ |
|
struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
|
|
|
/* Read whole page - necessary with MLC controller! */ |
|
lpc32xx_read_page(chip, host->dummy_buf, 1, page); |
|
|
|
return 0; |
|
} |
|
|
|
static int lpc32xx_write_oob(struct nand_chip *chip, int page) |
|
{ |
|
/* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */ |
|
return 0; |
|
} |
|
|
|
/* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */ |
|
static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode) |
|
{ |
|
/* Always enabled! */ |
|
} |
|
|
|
static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(&host->nand_chip); |
|
dma_cap_mask_t mask; |
|
|
|
if (!host->pdata || !host->pdata->dma_filter) { |
|
dev_err(mtd->dev.parent, "no DMA platform data\n"); |
|
return -ENOENT; |
|
} |
|
|
|
dma_cap_zero(mask); |
|
dma_cap_set(DMA_SLAVE, mask); |
|
host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, |
|
"nand-mlc"); |
|
if (!host->dma_chan) { |
|
dev_err(mtd->dev.parent, "Failed to request DMA channel\n"); |
|
return -EBUSY; |
|
} |
|
|
|
/* |
|
* Set direction to a sensible value even if the dmaengine driver |
|
* should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x |
|
* driver criticizes it as "alien transfer direction". |
|
*/ |
|
host->dma_slave_config.direction = DMA_DEV_TO_MEM; |
|
host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
|
host->dma_slave_config.src_maxburst = 128; |
|
host->dma_slave_config.dst_maxburst = 128; |
|
/* DMA controller does flow control: */ |
|
host->dma_slave_config.device_fc = false; |
|
host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy); |
|
host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy); |
|
if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) { |
|
dev_err(mtd->dev.parent, "Failed to setup DMA slave\n"); |
|
goto out1; |
|
} |
|
|
|
return 0; |
|
out1: |
|
dma_release_channel(host->dma_chan); |
|
return -ENXIO; |
|
} |
|
|
|
static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev) |
|
{ |
|
struct lpc32xx_nand_cfg_mlc *ncfg; |
|
struct device_node *np = dev->of_node; |
|
|
|
ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL); |
|
if (!ncfg) |
|
return NULL; |
|
|
|
of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay); |
|
of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay); |
|
of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta); |
|
of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high); |
|
of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low); |
|
of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high); |
|
of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low); |
|
|
|
if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta || |
|
!ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high || |
|
!ncfg->wr_low) { |
|
dev_err(dev, "chip parameters not specified correctly\n"); |
|
return NULL; |
|
} |
|
|
|
ncfg->wp_gpio = of_get_named_gpio(np, "gpios", 0); |
|
|
|
return ncfg; |
|
} |
|
|
|
static int lpc32xx_nand_attach_chip(struct nand_chip *chip) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
struct lpc32xx_nand_host *host = nand_get_controller_data(chip); |
|
struct device *dev = &host->pdev->dev; |
|
|
|
if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) |
|
return 0; |
|
|
|
host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); |
|
if (!host->dma_buf) |
|
return -ENOMEM; |
|
|
|
host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL); |
|
if (!host->dummy_buf) |
|
return -ENOMEM; |
|
|
|
chip->ecc.size = 512; |
|
chip->ecc.hwctl = lpc32xx_ecc_enable; |
|
chip->ecc.read_page_raw = lpc32xx_read_page; |
|
chip->ecc.read_page = lpc32xx_read_page; |
|
chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel; |
|
chip->ecc.write_page = lpc32xx_write_page_lowlevel; |
|
chip->ecc.write_oob = lpc32xx_write_oob; |
|
chip->ecc.read_oob = lpc32xx_read_oob; |
|
chip->ecc.strength = 4; |
|
chip->ecc.bytes = 10; |
|
|
|
mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); |
|
host->mlcsubpages = mtd->writesize / 512; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct nand_controller_ops lpc32xx_nand_controller_ops = { |
|
.attach_chip = lpc32xx_nand_attach_chip, |
|
}; |
|
|
|
/* |
|
* Probe for NAND controller |
|
*/ |
|
static int lpc32xx_nand_probe(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_nand_host *host; |
|
struct mtd_info *mtd; |
|
struct nand_chip *nand_chip; |
|
struct resource *rc; |
|
int res; |
|
|
|
/* Allocate memory for the device structure (and zero it) */ |
|
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
|
if (!host) |
|
return -ENOMEM; |
|
|
|
host->pdev = pdev; |
|
|
|
rc = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
host->io_base = devm_ioremap_resource(&pdev->dev, rc); |
|
if (IS_ERR(host->io_base)) |
|
return PTR_ERR(host->io_base); |
|
|
|
host->io_base_phy = rc->start; |
|
|
|
nand_chip = &host->nand_chip; |
|
mtd = nand_to_mtd(nand_chip); |
|
if (pdev->dev.of_node) |
|
host->ncfg = lpc32xx_parse_dt(&pdev->dev); |
|
if (!host->ncfg) { |
|
dev_err(&pdev->dev, |
|
"Missing or bad NAND config from device tree\n"); |
|
return -ENOENT; |
|
} |
|
if (host->ncfg->wp_gpio == -EPROBE_DEFER) |
|
return -EPROBE_DEFER; |
|
if (gpio_is_valid(host->ncfg->wp_gpio) && |
|
gpio_request(host->ncfg->wp_gpio, "NAND WP")) { |
|
dev_err(&pdev->dev, "GPIO not available\n"); |
|
return -EBUSY; |
|
} |
|
lpc32xx_wp_disable(host); |
|
|
|
host->pdata = dev_get_platdata(&pdev->dev); |
|
|
|
/* link the private data structures */ |
|
nand_set_controller_data(nand_chip, host); |
|
nand_set_flash_node(nand_chip, pdev->dev.of_node); |
|
mtd->dev.parent = &pdev->dev; |
|
|
|
/* Get NAND clock */ |
|
host->clk = clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(host->clk)) { |
|
dev_err(&pdev->dev, "Clock initialization failure\n"); |
|
res = -ENOENT; |
|
goto free_gpio; |
|
} |
|
res = clk_prepare_enable(host->clk); |
|
if (res) |
|
goto put_clk; |
|
|
|
nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl; |
|
nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready; |
|
nand_chip->legacy.chip_delay = 25; /* us */ |
|
nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base); |
|
nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base); |
|
|
|
/* Init NAND controller */ |
|
lpc32xx_nand_setup(host); |
|
|
|
platform_set_drvdata(pdev, host); |
|
|
|
/* Initialize function pointers */ |
|
nand_chip->legacy.waitfunc = lpc32xx_waitfunc; |
|
|
|
nand_chip->options = NAND_NO_SUBPAGE_WRITE; |
|
nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; |
|
nand_chip->bbt_td = &lpc32xx_nand_bbt; |
|
nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror; |
|
|
|
if (use_dma) { |
|
res = lpc32xx_dma_setup(host); |
|
if (res) { |
|
res = -EIO; |
|
goto unprepare_clk; |
|
} |
|
} |
|
|
|
/* initially clear interrupt status */ |
|
readb(MLC_IRQ_SR(host->io_base)); |
|
|
|
init_completion(&host->comp_nand); |
|
init_completion(&host->comp_controller); |
|
|
|
host->irq = platform_get_irq(pdev, 0); |
|
if (host->irq < 0) { |
|
res = -EINVAL; |
|
goto release_dma_chan; |
|
} |
|
|
|
if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq, |
|
IRQF_TRIGGER_HIGH, DRV_NAME, host)) { |
|
dev_err(&pdev->dev, "Error requesting NAND IRQ\n"); |
|
res = -ENXIO; |
|
goto release_dma_chan; |
|
} |
|
|
|
/* |
|
* Scan to find existence of the device and get the type of NAND device: |
|
* SMALL block or LARGE block. |
|
*/ |
|
nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops; |
|
res = nand_scan(nand_chip, 1); |
|
if (res) |
|
goto free_irq; |
|
|
|
mtd->name = DRV_NAME; |
|
|
|
res = mtd_device_register(mtd, host->ncfg->parts, |
|
host->ncfg->num_parts); |
|
if (res) |
|
goto cleanup_nand; |
|
|
|
return 0; |
|
|
|
cleanup_nand: |
|
nand_cleanup(nand_chip); |
|
free_irq: |
|
free_irq(host->irq, host); |
|
release_dma_chan: |
|
if (use_dma) |
|
dma_release_channel(host->dma_chan); |
|
unprepare_clk: |
|
clk_disable_unprepare(host->clk); |
|
put_clk: |
|
clk_put(host->clk); |
|
free_gpio: |
|
lpc32xx_wp_enable(host); |
|
gpio_free(host->ncfg->wp_gpio); |
|
|
|
return res; |
|
} |
|
|
|
/* |
|
* Remove NAND device |
|
*/ |
|
static int lpc32xx_nand_remove(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
|
struct nand_chip *chip = &host->nand_chip; |
|
int ret; |
|
|
|
ret = mtd_device_unregister(nand_to_mtd(chip)); |
|
WARN_ON(ret); |
|
nand_cleanup(chip); |
|
|
|
free_irq(host->irq, host); |
|
if (use_dma) |
|
dma_release_channel(host->dma_chan); |
|
|
|
clk_disable_unprepare(host->clk); |
|
clk_put(host->clk); |
|
|
|
lpc32xx_wp_enable(host); |
|
gpio_free(host->ncfg->wp_gpio); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int lpc32xx_nand_resume(struct platform_device *pdev) |
|
{ |
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
|
int ret; |
|
|
|
/* Re-enable NAND clock */ |
|
ret = clk_prepare_enable(host->clk); |
|
if (ret) |
|
return ret; |
|
|
|
/* Fresh init of NAND controller */ |
|
lpc32xx_nand_setup(host); |
|
|
|
/* Disable write protect */ |
|
lpc32xx_wp_disable(host); |
|
|
|
return 0; |
|
} |
|
|
|
static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm) |
|
{ |
|
struct lpc32xx_nand_host *host = platform_get_drvdata(pdev); |
|
|
|
/* Enable write protect for safety */ |
|
lpc32xx_wp_enable(host); |
|
|
|
/* Disable clock */ |
|
clk_disable_unprepare(host->clk); |
|
return 0; |
|
} |
|
|
|
#else |
|
#define lpc32xx_nand_resume NULL |
|
#define lpc32xx_nand_suspend NULL |
|
#endif |
|
|
|
static const struct of_device_id lpc32xx_nand_match[] = { |
|
{ .compatible = "nxp,lpc3220-mlc" }, |
|
{ /* sentinel */ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, lpc32xx_nand_match); |
|
|
|
static struct platform_driver lpc32xx_nand_driver = { |
|
.probe = lpc32xx_nand_probe, |
|
.remove = lpc32xx_nand_remove, |
|
.resume = lpc32xx_nand_resume, |
|
.suspend = lpc32xx_nand_suspend, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = lpc32xx_nand_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(lpc32xx_nand_driver); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Roland Stigge <[email protected]>"); |
|
MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
|
|
|