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197 lines
5.0 KiB
197 lines
5.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* JZ4740 ECC controller driver |
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* |
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* Copyright (c) 2019 Paul Cercueil <[email protected]> |
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* |
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* based on jz4740-nand.c |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/device.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include "ingenic_ecc.h" |
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#define JZ_REG_NAND_ECC_CTRL 0x00 |
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#define JZ_REG_NAND_DATA 0x04 |
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#define JZ_REG_NAND_PAR0 0x08 |
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#define JZ_REG_NAND_PAR1 0x0C |
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#define JZ_REG_NAND_PAR2 0x10 |
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#define JZ_REG_NAND_IRQ_STAT 0x14 |
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#define JZ_REG_NAND_IRQ_CTRL 0x18 |
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#define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2)) |
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#define JZ_NAND_ECC_CTRL_PAR_READY BIT(4) |
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#define JZ_NAND_ECC_CTRL_ENCODING BIT(3) |
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#define JZ_NAND_ECC_CTRL_RS BIT(2) |
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#define JZ_NAND_ECC_CTRL_RESET BIT(1) |
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#define JZ_NAND_ECC_CTRL_ENABLE BIT(0) |
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#define JZ_NAND_STATUS_ERR_COUNT (BIT(31) | BIT(30) | BIT(29)) |
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#define JZ_NAND_STATUS_PAD_FINISH BIT(4) |
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#define JZ_NAND_STATUS_DEC_FINISH BIT(3) |
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#define JZ_NAND_STATUS_ENC_FINISH BIT(2) |
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#define JZ_NAND_STATUS_UNCOR_ERROR BIT(1) |
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#define JZ_NAND_STATUS_ERROR BIT(0) |
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static const uint8_t empty_block_ecc[] = { |
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0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f |
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}; |
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static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) |
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{ |
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uint32_t reg; |
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/* Clear interrupt status */ |
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writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); |
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/* Initialize and enable ECC hardware */ |
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reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); |
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reg |= JZ_NAND_ECC_CTRL_RESET; |
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reg |= JZ_NAND_ECC_CTRL_ENABLE; |
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reg |= JZ_NAND_ECC_CTRL_RS; |
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if (calc_ecc) /* calculate ECC from data */ |
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reg |= JZ_NAND_ECC_CTRL_ENCODING; |
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else /* correct data from ECC */ |
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reg &= ~JZ_NAND_ECC_CTRL_ENCODING; |
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writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); |
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} |
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static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, |
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struct ingenic_ecc_params *params, |
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const u8 *buf, u8 *ecc_code) |
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{ |
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uint32_t reg, status; |
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unsigned int timeout = 1000; |
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int i; |
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jz4740_ecc_reset(ecc, true); |
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do { |
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status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); |
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} while (!(status & JZ_NAND_STATUS_ENC_FINISH) && --timeout); |
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if (timeout == 0) |
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return -ETIMEDOUT; |
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reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); |
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE; |
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writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); |
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for (i = 0; i < params->bytes; ++i) |
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ecc_code[i] = readb(ecc->base + JZ_REG_NAND_PAR0 + i); |
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/* |
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* If the written data is completely 0xff, we also want to write 0xff as |
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* ECC, otherwise we will get in trouble when doing subpage writes. |
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*/ |
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if (memcmp(ecc_code, empty_block_ecc, sizeof(empty_block_ecc)) == 0) |
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memset(ecc_code, 0xff, sizeof(empty_block_ecc)); |
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return 0; |
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} |
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static void jz_nand_correct_data(uint8_t *buf, int index, int mask) |
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{ |
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int offset = index & 0x7; |
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uint16_t data; |
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index += (index >> 3); |
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data = buf[index]; |
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data |= buf[index + 1] << 8; |
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mask ^= (data >> offset) & 0x1ff; |
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data &= ~(0x1ff << offset); |
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data |= (mask << offset); |
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buf[index] = data & 0xff; |
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buf[index + 1] = (data >> 8) & 0xff; |
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} |
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static int jz4740_ecc_correct(struct ingenic_ecc *ecc, |
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struct ingenic_ecc_params *params, |
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u8 *buf, u8 *ecc_code) |
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{ |
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int i, error_count, index; |
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uint32_t reg, status, error; |
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unsigned int timeout = 1000; |
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jz4740_ecc_reset(ecc, false); |
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for (i = 0; i < params->bytes; ++i) |
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writeb(ecc_code[i], ecc->base + JZ_REG_NAND_PAR0 + i); |
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reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); |
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reg |= JZ_NAND_ECC_CTRL_PAR_READY; |
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writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); |
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do { |
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status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); |
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} while (!(status & JZ_NAND_STATUS_DEC_FINISH) && --timeout); |
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if (timeout == 0) |
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return -ETIMEDOUT; |
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reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); |
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE; |
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writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); |
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if (status & JZ_NAND_STATUS_ERROR) { |
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if (status & JZ_NAND_STATUS_UNCOR_ERROR) |
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return -EBADMSG; |
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error_count = (status & JZ_NAND_STATUS_ERR_COUNT) >> 29; |
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for (i = 0; i < error_count; ++i) { |
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error = readl(ecc->base + JZ_REG_NAND_ERR(i)); |
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index = ((error >> 16) & 0x1ff) - 1; |
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if (index >= 0 && index < params->size) |
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jz_nand_correct_data(buf, index, error & 0x1ff); |
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} |
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return error_count; |
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} |
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return 0; |
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} |
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static void jz4740_ecc_disable(struct ingenic_ecc *ecc) |
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{ |
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u32 reg; |
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writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); |
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reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); |
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reg &= ~JZ_NAND_ECC_CTRL_ENABLE; |
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writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); |
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} |
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static const struct ingenic_ecc_ops jz4740_ecc_ops = { |
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.disable = jz4740_ecc_disable, |
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.calculate = jz4740_ecc_calculate, |
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.correct = jz4740_ecc_correct, |
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}; |
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static const struct of_device_id jz4740_ecc_dt_match[] = { |
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{ .compatible = "ingenic,jz4740-ecc", .data = &jz4740_ecc_ops }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, jz4740_ecc_dt_match); |
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static struct platform_driver jz4740_ecc_driver = { |
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.probe = ingenic_ecc_probe, |
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.driver = { |
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.name = "jz4740-ecc", |
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.of_match_table = jz4740_ecc_dt_match, |
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}, |
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}; |
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module_platform_driver(jz4740_ecc_driver); |
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MODULE_AUTHOR("Paul Cercueil <[email protected]>"); |
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MODULE_DESCRIPTION("Ingenic JZ4740 ECC controller driver"); |
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MODULE_LICENSE("GPL v2");
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