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175 lines
5.2 KiB
175 lines
5.2 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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/* |
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* Freescale GPMI NAND Flash Driver |
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* |
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* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. |
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* Copyright (C) 2008 Embedded Alley Solutions, Inc. |
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*/ |
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#ifndef __DRIVERS_MTD_NAND_GPMI_NAND_H |
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#define __DRIVERS_MTD_NAND_GPMI_NAND_H |
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#include <linux/mtd/rawnand.h> |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmaengine.h> |
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#define GPMI_CLK_MAX 5 /* MX6Q needs five clocks */ |
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struct resources { |
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void __iomem *gpmi_regs; |
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void __iomem *bch_regs; |
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unsigned int dma_low_channel; |
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unsigned int dma_high_channel; |
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struct clk *clock[GPMI_CLK_MAX]; |
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}; |
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/** |
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* struct bch_geometry - BCH geometry description. |
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* @gf_len: The length of Galois Field. (e.g., 13 or 14) |
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* @ecc_strength: A number that describes the strength of the ECC |
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* algorithm. |
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* @page_size: The size, in bytes, of a physical page, including |
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* both data and OOB. |
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* @metadata_size: The size, in bytes, of the metadata. |
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* @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note |
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* the first chunk in the page includes both data and |
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* metadata, so it's a bit larger than this value. |
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* @ecc_chunk_count: The number of ECC chunks in the page, |
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* @payload_size: The size, in bytes, of the payload buffer. |
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* @auxiliary_size: The size, in bytes, of the auxiliary buffer. |
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* @auxiliary_status_offset: The offset into the auxiliary buffer at which |
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* the ECC status appears. |
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* @block_mark_byte_offset: The byte offset in the ECC-based page view at |
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* which the underlying physical block mark appears. |
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* @block_mark_bit_offset: The bit offset into the ECC-based page view at |
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* which the underlying physical block mark appears. |
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*/ |
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struct bch_geometry { |
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unsigned int gf_len; |
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unsigned int ecc_strength; |
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unsigned int page_size; |
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unsigned int metadata_size; |
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unsigned int ecc_chunk_size; |
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unsigned int ecc_chunk_count; |
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unsigned int payload_size; |
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unsigned int auxiliary_size; |
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unsigned int auxiliary_status_offset; |
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unsigned int block_mark_byte_offset; |
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unsigned int block_mark_bit_offset; |
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}; |
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/** |
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* struct boot_rom_geometry - Boot ROM geometry description. |
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* @stride_size_in_pages: The size of a boot block stride, in pages. |
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* @search_area_stride_exponent: The logarithm to base 2 of the size of a |
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* search area in boot block strides. |
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*/ |
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struct boot_rom_geometry { |
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unsigned int stride_size_in_pages; |
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unsigned int search_area_stride_exponent; |
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}; |
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enum gpmi_type { |
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IS_MX23, |
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IS_MX28, |
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IS_MX6Q, |
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IS_MX6SX, |
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IS_MX7D, |
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}; |
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struct gpmi_devdata { |
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enum gpmi_type type; |
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int bch_max_ecc_strength; |
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int max_chain_delay; /* See the SDR EDO mode */ |
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const char * const *clks; |
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const int clks_count; |
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}; |
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/** |
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* struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters. |
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* @must_apply_timings: Whether controller timings have already been |
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* applied or not (useful only while there is |
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* support for only one chip select) |
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* @clk_rate: The clock rate that must be used to derive the |
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* following parameters |
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* @timing0: HW_GPMI_TIMING0 register |
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* @timing1: HW_GPMI_TIMING1 register |
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* @ctrl1n: HW_GPMI_CTRL1n register |
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*/ |
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struct gpmi_nfc_hardware_timing { |
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bool must_apply_timings; |
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unsigned long int clk_rate; |
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u32 timing0; |
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u32 timing1; |
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u32 ctrl1n; |
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}; |
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#define GPMI_MAX_TRANSFERS 8 |
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struct gpmi_transfer { |
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u8 cmdbuf[8]; |
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struct scatterlist sgl; |
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enum dma_data_direction direction; |
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}; |
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struct gpmi_nand_data { |
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/* Devdata */ |
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const struct gpmi_devdata *devdata; |
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/* System Interface */ |
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struct device *dev; |
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struct platform_device *pdev; |
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/* Resources */ |
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struct resources resources; |
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/* Flash Hardware */ |
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struct gpmi_nfc_hardware_timing hw; |
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/* BCH */ |
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struct bch_geometry bch_geometry; |
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struct completion bch_done; |
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/* NAND Boot issue */ |
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bool swap_block_mark; |
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struct boot_rom_geometry rom_geometry; |
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/* MTD / NAND */ |
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struct nand_controller base; |
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struct nand_chip nand; |
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struct gpmi_transfer transfers[GPMI_MAX_TRANSFERS]; |
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int ntransfers; |
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bool bch; |
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uint32_t bch_flashlayout0; |
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uint32_t bch_flashlayout1; |
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char *data_buffer_dma; |
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void *auxiliary_virt; |
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dma_addr_t auxiliary_phys; |
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void *raw_buffer; |
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/* DMA channels */ |
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#define DMA_CHANS 8 |
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struct dma_chan *dma_chans[DMA_CHANS]; |
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struct completion dma_done; |
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}; |
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/* BCH : Status Block Completion Codes */ |
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#define STATUS_GOOD 0x00 |
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#define STATUS_ERASED 0xff |
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#define STATUS_UNCORRECTABLE 0xfe |
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/* Use the devdata to distinguish different Archs. */ |
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#define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23) |
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#define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28) |
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#define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q) |
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#define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX) |
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#define GPMI_IS_MX7D(x) ((x)->devdata->type == IS_MX7D) |
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#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x) || \ |
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GPMI_IS_MX7D(x)) |
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#define GPMI_IS_MXS(x) (GPMI_IS_MX23(x) || GPMI_IS_MX28(x)) |
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#endif
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