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403 lines
9.6 KiB
403 lines
9.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Updated, and converted to generic GPIO based driver by Russell King. |
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* |
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* Written by Ben Dooks <[email protected]> |
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* Based on 2.4 version by Mark Whittaker |
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* |
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* © 2004 Simtec Electronics |
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* |
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* Device driver for NAND flash that uses a memory mapped interface to |
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* read/write the NAND commands and data, and GPIO pins for control signals |
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* (the DT binding refers to this as "GPIO assisted NAND flash") |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/err.h> |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/io.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/mtd/nand-gpio.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/delay.h> |
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struct gpiomtd { |
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struct nand_controller base; |
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void __iomem *io; |
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void __iomem *io_sync; |
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struct nand_chip nand_chip; |
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struct gpio_nand_platdata plat; |
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struct gpio_desc *nce; /* Optional chip enable */ |
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struct gpio_desc *cle; |
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struct gpio_desc *ale; |
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struct gpio_desc *rdy; |
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struct gpio_desc *nwp; /* Optional write protection */ |
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}; |
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static inline struct gpiomtd *gpio_nand_getpriv(struct mtd_info *mtd) |
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{ |
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return container_of(mtd_to_nand(mtd), struct gpiomtd, nand_chip); |
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} |
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#ifdef CONFIG_ARM |
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/* gpio_nand_dosync() |
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* |
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* Make sure the GPIO state changes occur in-order with writes to NAND |
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* memory region. |
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* Needed on PXA due to bus-reordering within the SoC itself (see section on |
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* I/O ordering in PXA manual (section 2.3, p35) |
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*/ |
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static void gpio_nand_dosync(struct gpiomtd *gpiomtd) |
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{ |
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unsigned long tmp; |
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if (gpiomtd->io_sync) { |
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/* |
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* Linux memory barriers don't cater for what's required here. |
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* What's required is what's here - a read from a separate |
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* region with a dependency on that read. |
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*/ |
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tmp = readl(gpiomtd->io_sync); |
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asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp)); |
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} |
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} |
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#else |
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static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {} |
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#endif |
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static int gpio_nand_exec_instr(struct nand_chip *chip, |
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const struct nand_op_instr *instr) |
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{ |
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); |
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unsigned int i; |
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switch (instr->type) { |
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case NAND_OP_CMD_INSTR: |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->cle, 1); |
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gpio_nand_dosync(gpiomtd); |
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writeb(instr->ctx.cmd.opcode, gpiomtd->io); |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->cle, 0); |
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return 0; |
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case NAND_OP_ADDR_INSTR: |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->ale, 1); |
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gpio_nand_dosync(gpiomtd); |
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for (i = 0; i < instr->ctx.addr.naddrs; i++) |
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writeb(instr->ctx.addr.addrs[i], gpiomtd->io); |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->ale, 0); |
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return 0; |
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case NAND_OP_DATA_IN_INSTR: |
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gpio_nand_dosync(gpiomtd); |
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if ((chip->options & NAND_BUSWIDTH_16) && |
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!instr->ctx.data.force_8bit) |
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ioread16_rep(gpiomtd->io, instr->ctx.data.buf.in, |
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instr->ctx.data.len / 2); |
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else |
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ioread8_rep(gpiomtd->io, instr->ctx.data.buf.in, |
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instr->ctx.data.len); |
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return 0; |
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case NAND_OP_DATA_OUT_INSTR: |
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gpio_nand_dosync(gpiomtd); |
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if ((chip->options & NAND_BUSWIDTH_16) && |
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!instr->ctx.data.force_8bit) |
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iowrite16_rep(gpiomtd->io, instr->ctx.data.buf.out, |
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instr->ctx.data.len / 2); |
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else |
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iowrite8_rep(gpiomtd->io, instr->ctx.data.buf.out, |
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instr->ctx.data.len); |
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return 0; |
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case NAND_OP_WAITRDY_INSTR: |
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if (!gpiomtd->rdy) |
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return nand_soft_waitrdy(chip, instr->ctx.waitrdy.timeout_ms); |
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return nand_gpio_waitrdy(chip, gpiomtd->rdy, |
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instr->ctx.waitrdy.timeout_ms); |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int gpio_nand_exec_op(struct nand_chip *chip, |
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const struct nand_operation *op, |
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bool check_only) |
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{ |
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struct gpiomtd *gpiomtd = gpio_nand_getpriv(nand_to_mtd(chip)); |
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unsigned int i; |
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int ret = 0; |
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if (check_only) |
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return 0; |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->nce, 0); |
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for (i = 0; i < op->ninstrs; i++) { |
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ret = gpio_nand_exec_instr(chip, &op->instrs[i]); |
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if (ret) |
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break; |
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if (op->instrs[i].delay_ns) |
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ndelay(op->instrs[i].delay_ns); |
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} |
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gpio_nand_dosync(gpiomtd); |
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gpiod_set_value(gpiomtd->nce, 1); |
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return ret; |
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} |
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static int gpio_nand_attach_chip(struct nand_chip *chip) |
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{ |
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chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; |
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if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) |
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chip->ecc.algo = NAND_ECC_ALGO_HAMMING; |
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return 0; |
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} |
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static const struct nand_controller_ops gpio_nand_ops = { |
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.exec_op = gpio_nand_exec_op, |
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.attach_chip = gpio_nand_attach_chip, |
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}; |
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#ifdef CONFIG_OF |
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static const struct of_device_id gpio_nand_id_table[] = { |
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{ .compatible = "gpio-control-nand" }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, gpio_nand_id_table); |
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static int gpio_nand_get_config_of(const struct device *dev, |
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struct gpio_nand_platdata *plat) |
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{ |
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u32 val; |
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if (!dev->of_node) |
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return -ENODEV; |
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if (!of_property_read_u32(dev->of_node, "bank-width", &val)) { |
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if (val == 2) { |
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plat->options |= NAND_BUSWIDTH_16; |
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} else if (val != 1) { |
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dev_err(dev, "invalid bank-width %u\n", val); |
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return -EINVAL; |
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} |
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} |
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if (!of_property_read_u32(dev->of_node, "chip-delay", &val)) |
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plat->chip_delay = val; |
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return 0; |
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} |
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static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev) |
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{ |
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struct resource *r; |
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u64 addr; |
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if (of_property_read_u64(pdev->dev.of_node, |
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"gpio-control-nand,io-sync-reg", &addr)) |
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return NULL; |
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r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL); |
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if (!r) |
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return NULL; |
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r->start = addr; |
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r->end = r->start + 0x3; |
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r->flags = IORESOURCE_MEM; |
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return r; |
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} |
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#else /* CONFIG_OF */ |
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static inline int gpio_nand_get_config_of(const struct device *dev, |
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struct gpio_nand_platdata *plat) |
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{ |
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return -ENOSYS; |
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} |
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static inline struct resource * |
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gpio_nand_get_io_sync_of(struct platform_device *pdev) |
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{ |
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return NULL; |
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} |
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#endif /* CONFIG_OF */ |
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static inline int gpio_nand_get_config(const struct device *dev, |
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struct gpio_nand_platdata *plat) |
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{ |
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int ret = gpio_nand_get_config_of(dev, plat); |
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if (!ret) |
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return ret; |
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if (dev_get_platdata(dev)) { |
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memcpy(plat, dev_get_platdata(dev), sizeof(*plat)); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static inline struct resource * |
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gpio_nand_get_io_sync(struct platform_device *pdev) |
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{ |
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struct resource *r = gpio_nand_get_io_sync_of(pdev); |
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if (r) |
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return r; |
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return platform_get_resource(pdev, IORESOURCE_MEM, 1); |
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} |
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static int gpio_nand_remove(struct platform_device *pdev) |
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{ |
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struct gpiomtd *gpiomtd = platform_get_drvdata(pdev); |
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struct nand_chip *chip = &gpiomtd->nand_chip; |
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int ret; |
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ret = mtd_device_unregister(nand_to_mtd(chip)); |
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WARN_ON(ret); |
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nand_cleanup(chip); |
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/* Enable write protection and disable the chip */ |
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if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) |
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gpiod_set_value(gpiomtd->nwp, 0); |
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if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) |
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gpiod_set_value(gpiomtd->nce, 0); |
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return 0; |
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} |
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static int gpio_nand_probe(struct platform_device *pdev) |
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{ |
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struct gpiomtd *gpiomtd; |
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struct nand_chip *chip; |
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struct mtd_info *mtd; |
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struct resource *res; |
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struct device *dev = &pdev->dev; |
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int ret = 0; |
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if (!dev->of_node && !dev_get_platdata(dev)) |
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return -EINVAL; |
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gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL); |
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if (!gpiomtd) |
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return -ENOMEM; |
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chip = &gpiomtd->nand_chip; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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gpiomtd->io = devm_ioremap_resource(dev, res); |
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if (IS_ERR(gpiomtd->io)) |
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return PTR_ERR(gpiomtd->io); |
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res = gpio_nand_get_io_sync(pdev); |
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if (res) { |
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gpiomtd->io_sync = devm_ioremap_resource(dev, res); |
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if (IS_ERR(gpiomtd->io_sync)) |
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return PTR_ERR(gpiomtd->io_sync); |
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} |
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ret = gpio_nand_get_config(dev, &gpiomtd->plat); |
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if (ret) |
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return ret; |
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/* Just enable the chip */ |
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gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH); |
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if (IS_ERR(gpiomtd->nce)) |
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return PTR_ERR(gpiomtd->nce); |
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/* We disable write protection once we know probe() will succeed */ |
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gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW); |
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if (IS_ERR(gpiomtd->nwp)) { |
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ret = PTR_ERR(gpiomtd->nwp); |
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goto out_ce; |
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} |
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gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW); |
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if (IS_ERR(gpiomtd->ale)) { |
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ret = PTR_ERR(gpiomtd->ale); |
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goto out_ce; |
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} |
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gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW); |
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if (IS_ERR(gpiomtd->cle)) { |
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ret = PTR_ERR(gpiomtd->cle); |
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goto out_ce; |
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} |
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gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN); |
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if (IS_ERR(gpiomtd->rdy)) { |
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ret = PTR_ERR(gpiomtd->rdy); |
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goto out_ce; |
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} |
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nand_controller_init(&gpiomtd->base); |
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gpiomtd->base.ops = &gpio_nand_ops; |
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nand_set_flash_node(chip, pdev->dev.of_node); |
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chip->options = gpiomtd->plat.options; |
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chip->controller = &gpiomtd->base; |
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mtd = nand_to_mtd(chip); |
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mtd->dev.parent = dev; |
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platform_set_drvdata(pdev, gpiomtd); |
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/* Disable write protection, if wired up */ |
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if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) |
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gpiod_direction_output(gpiomtd->nwp, 1); |
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ret = nand_scan(chip, 1); |
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if (ret) |
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goto err_wp; |
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if (gpiomtd->plat.adjust_parts) |
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gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size); |
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ret = mtd_device_register(mtd, gpiomtd->plat.parts, |
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gpiomtd->plat.num_parts); |
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if (!ret) |
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return 0; |
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err_wp: |
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if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) |
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gpiod_set_value(gpiomtd->nwp, 0); |
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out_ce: |
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if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) |
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gpiod_set_value(gpiomtd->nce, 0); |
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return ret; |
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} |
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static struct platform_driver gpio_nand_driver = { |
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.probe = gpio_nand_probe, |
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.remove = gpio_nand_remove, |
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.driver = { |
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.name = "gpio-nand", |
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.of_match_table = of_match_ptr(gpio_nand_id_table), |
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}, |
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}; |
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module_platform_driver(gpio_nand_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Ben Dooks <[email protected]>"); |
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MODULE_DESCRIPTION("GPIO NAND Driver");
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