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998 lines
29 KiB
998 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* Freescale Enhanced Local Bus Controller NAND driver |
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* |
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* Copyright © 2006-2007, 2010 Freescale Semiconductor |
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* |
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* Authors: Nick Spence <[email protected]>, |
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* Scott Wood <[email protected]> |
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* Jack Lan <[email protected]> |
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* Roy Zang <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/kernel.h> |
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#include <linux/string.h> |
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#include <linux/ioport.h> |
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#include <linux/of_address.h> |
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#include <linux/of_platform.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/interrupt.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <asm/io.h> |
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#include <asm/fsl_lbc.h> |
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#define MAX_BANKS 8 |
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#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ |
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#define FCM_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait for FCM */ |
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/* mtd information per set */ |
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struct fsl_elbc_mtd { |
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struct nand_chip chip; |
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struct fsl_lbc_ctrl *ctrl; |
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struct device *dev; |
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int bank; /* Chip select bank number */ |
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u8 __iomem *vbase; /* Chip select base virtual address */ |
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int page_size; /* NAND page size (0=512, 1=2048) */ |
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unsigned int fmr; /* FCM Flash Mode Register value */ |
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}; |
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/* Freescale eLBC FCM controller information */ |
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struct fsl_elbc_fcm_ctrl { |
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struct nand_controller controller; |
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struct fsl_elbc_mtd *chips[MAX_BANKS]; |
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u8 __iomem *addr; /* Address of assigned FCM buffer */ |
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unsigned int page; /* Last page written to / read from */ |
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unsigned int read_bytes; /* Number of bytes read during command */ |
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unsigned int column; /* Saved column from SEQIN */ |
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unsigned int index; /* Pointer to next byte to 'read' */ |
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unsigned int status; /* status read from LTESR after last op */ |
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unsigned int mdr; /* UPM/FCM Data Register value */ |
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unsigned int use_mdr; /* Non zero if the MDR is to be set */ |
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unsigned int oob; /* Non zero if operating on OOB data */ |
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unsigned int counter; /* counter for the initializations */ |
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unsigned int max_bitflips; /* Saved during READ0 cmd */ |
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}; |
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/* These map to the positions used by the FCM hardware ECC generator */ |
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static int fsl_elbc_ooblayout_ecc(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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if (section >= chip->ecc.steps) |
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return -ERANGE; |
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oobregion->offset = (16 * section) + 6; |
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if (priv->fmr & FMR_ECCM) |
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oobregion->offset += 2; |
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oobregion->length = chip->ecc.bytes; |
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return 0; |
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} |
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static int fsl_elbc_ooblayout_free(struct mtd_info *mtd, int section, |
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struct mtd_oob_region *oobregion) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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if (section > chip->ecc.steps) |
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return -ERANGE; |
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if (!section) { |
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oobregion->offset = 0; |
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if (mtd->writesize > 512) |
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oobregion->offset++; |
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oobregion->length = (priv->fmr & FMR_ECCM) ? 7 : 5; |
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} else { |
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oobregion->offset = (16 * section) - |
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((priv->fmr & FMR_ECCM) ? 5 : 7); |
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if (section < chip->ecc.steps) |
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oobregion->length = 13; |
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else |
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oobregion->length = mtd->oobsize - oobregion->offset; |
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} |
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return 0; |
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} |
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static const struct mtd_ooblayout_ops fsl_elbc_ooblayout_ops = { |
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.ecc = fsl_elbc_ooblayout_ecc, |
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.free = fsl_elbc_ooblayout_free, |
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}; |
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/* |
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* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, |
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* interfere with ECC positions, that's why we implement our own descriptors. |
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* OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. |
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*/ |
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; |
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; |
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static struct nand_bbt_descr bbt_main_descr = { |
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
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NAND_BBT_2BIT | NAND_BBT_VERSION, |
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.offs = 11, |
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.len = 4, |
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.veroffs = 15, |
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.maxblocks = 4, |
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.pattern = bbt_pattern, |
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}; |
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static struct nand_bbt_descr bbt_mirror_descr = { |
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | |
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NAND_BBT_2BIT | NAND_BBT_VERSION, |
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.offs = 11, |
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.len = 4, |
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.veroffs = 15, |
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.maxblocks = 4, |
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.pattern = mirror_pattern, |
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}; |
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/*=================================*/ |
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/* |
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* Set up the FCM hardware block and page address fields, and the fcm |
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* structure addr field to point to the correct FCM buffer in memory |
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*/ |
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static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
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int buf_num; |
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elbc_fcm_ctrl->page = page_addr; |
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if (priv->page_size) { |
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/* |
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* large page size chip : FPAR[PI] save the lowest 6 bits, |
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* FBAR[BLK] save the other bits. |
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*/ |
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out_be32(&lbc->fbar, page_addr >> 6); |
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out_be32(&lbc->fpar, |
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((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | |
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(oob ? FPAR_LP_MS : 0) | column); |
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buf_num = (page_addr & 1) << 2; |
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} else { |
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/* |
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* small page size chip : FPAR[PI] save the lowest 5 bits, |
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* FBAR[BLK] save the other bits. |
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*/ |
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out_be32(&lbc->fbar, page_addr >> 5); |
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out_be32(&lbc->fpar, |
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((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | |
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(oob ? FPAR_SP_MS : 0) | column); |
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buf_num = page_addr & 7; |
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} |
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elbc_fcm_ctrl->addr = priv->vbase + buf_num * 1024; |
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elbc_fcm_ctrl->index = column; |
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/* for OOB data point to the second half of the buffer */ |
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if (oob) |
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elbc_fcm_ctrl->index += priv->page_size ? 2048 : 512; |
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dev_vdbg(priv->dev, "set_addr: bank=%d, " |
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"elbc_fcm_ctrl->addr=0x%p (0x%p), " |
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"index %x, pes %d ps %d\n", |
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buf_num, elbc_fcm_ctrl->addr, priv->vbase, |
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elbc_fcm_ctrl->index, |
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chip->phys_erase_shift, chip->page_shift); |
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} |
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/* |
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* execute FCM command and wait for it to complete |
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*/ |
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static int fsl_elbc_run_command(struct mtd_info *mtd) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
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/* Setup the FMR[OP] to execute without write protection */ |
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out_be32(&lbc->fmr, priv->fmr | 3); |
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if (elbc_fcm_ctrl->use_mdr) |
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out_be32(&lbc->mdr, elbc_fcm_ctrl->mdr); |
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dev_vdbg(priv->dev, |
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"fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", |
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in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); |
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dev_vdbg(priv->dev, |
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"fsl_elbc_run_command: fbar=%08x fpar=%08x " |
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"fbcr=%08x bank=%d\n", |
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in_be32(&lbc->fbar), in_be32(&lbc->fpar), |
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in_be32(&lbc->fbcr), priv->bank); |
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ctrl->irq_status = 0; |
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/* execute special operation */ |
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out_be32(&lbc->lsor, priv->bank); |
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/* wait for FCM complete flag or timeout */ |
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wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, |
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FCM_TIMEOUT_MSECS * HZ/1000); |
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elbc_fcm_ctrl->status = ctrl->irq_status; |
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/* store mdr value in case it was needed */ |
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if (elbc_fcm_ctrl->use_mdr) |
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elbc_fcm_ctrl->mdr = in_be32(&lbc->mdr); |
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elbc_fcm_ctrl->use_mdr = 0; |
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if (elbc_fcm_ctrl->status != LTESR_CC) { |
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dev_info(priv->dev, |
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"command failed: fir %x fcr %x status %x mdr %x\n", |
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in_be32(&lbc->fir), in_be32(&lbc->fcr), |
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elbc_fcm_ctrl->status, elbc_fcm_ctrl->mdr); |
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return -EIO; |
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} |
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if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) |
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return 0; |
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elbc_fcm_ctrl->max_bitflips = 0; |
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if (elbc_fcm_ctrl->read_bytes == mtd->writesize + mtd->oobsize) { |
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uint32_t lteccr = in_be32(&lbc->lteccr); |
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/* |
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* if command was a full page read and the ELBC |
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* has the LTECCR register, then bits 12-15 (ppc order) of |
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* LTECCR indicates which 512 byte sub-pages had fixed errors. |
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* bits 28-31 are uncorrectable errors, marked elsewhere. |
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* for small page nand only 1 bit is used. |
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* if the ELBC doesn't have the lteccr register it reads 0 |
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* FIXME: 4 bits can be corrected on NANDs with 2k pages, so |
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* count the number of sub-pages with bitflips and update |
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* ecc_stats.corrected accordingly. |
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*/ |
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if (lteccr & 0x000F000F) |
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out_be32(&lbc->lteccr, 0x000F000F); /* clear lteccr */ |
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if (lteccr & 0x000F0000) { |
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mtd->ecc_stats.corrected++; |
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elbc_fcm_ctrl->max_bitflips = 1; |
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} |
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} |
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return 0; |
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} |
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static void fsl_elbc_do_read(struct nand_chip *chip, int oob) |
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{ |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
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if (priv->page_size) { |
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out_be32(&lbc->fir, |
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(FIR_OP_CM0 << FIR_OP0_SHIFT) | |
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(FIR_OP_CA << FIR_OP1_SHIFT) | |
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(FIR_OP_PA << FIR_OP2_SHIFT) | |
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(FIR_OP_CM1 << FIR_OP3_SHIFT) | |
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(FIR_OP_RBW << FIR_OP4_SHIFT)); |
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out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | |
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(NAND_CMD_READSTART << FCR_CMD1_SHIFT)); |
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} else { |
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out_be32(&lbc->fir, |
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(FIR_OP_CM0 << FIR_OP0_SHIFT) | |
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(FIR_OP_CA << FIR_OP1_SHIFT) | |
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(FIR_OP_PA << FIR_OP2_SHIFT) | |
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(FIR_OP_RBW << FIR_OP3_SHIFT)); |
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if (oob) |
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out_be32(&lbc->fcr, NAND_CMD_READOOB << FCR_CMD0_SHIFT); |
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else |
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out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); |
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} |
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} |
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/* cmdfunc send commands to the FCM */ |
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static void fsl_elbc_cmdfunc(struct nand_chip *chip, unsigned int command, |
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int column, int page_addr) |
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{ |
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struct mtd_info *mtd = nand_to_mtd(chip); |
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struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
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struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
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struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
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struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
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elbc_fcm_ctrl->use_mdr = 0; |
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/* clear the read buffer */ |
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elbc_fcm_ctrl->read_bytes = 0; |
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if (command != NAND_CMD_PAGEPROG) |
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elbc_fcm_ctrl->index = 0; |
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switch (command) { |
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/* READ0 and READ1 read the entire buffer to use hardware ECC. */ |
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case NAND_CMD_READ1: |
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column += 256; |
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fallthrough; |
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case NAND_CMD_READ0: |
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dev_dbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" |
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" 0x%x, column: 0x%x.\n", page_addr, column); |
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out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ |
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set_addr(mtd, 0, page_addr, 0); |
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elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
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elbc_fcm_ctrl->index += column; |
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fsl_elbc_do_read(chip, 0); |
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fsl_elbc_run_command(mtd); |
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return; |
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/* RNDOUT moves the pointer inside the page */ |
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case NAND_CMD_RNDOUT: |
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dev_dbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n", |
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column); |
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elbc_fcm_ctrl->index = column; |
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return; |
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/* READOOB reads only the OOB because no ECC is performed. */ |
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case NAND_CMD_READOOB: |
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dev_vdbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" |
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" 0x%x, column: 0x%x.\n", page_addr, column); |
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out_be32(&lbc->fbcr, mtd->oobsize - column); |
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set_addr(mtd, column, page_addr, 1); |
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elbc_fcm_ctrl->read_bytes = mtd->writesize + mtd->oobsize; |
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fsl_elbc_do_read(chip, 1); |
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fsl_elbc_run_command(mtd); |
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return; |
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case NAND_CMD_READID: |
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case NAND_CMD_PARAM: |
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dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD %x\n", command); |
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out_be32(&lbc->fir, (FIR_OP_CM0 << FIR_OP0_SHIFT) | |
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(FIR_OP_UA << FIR_OP1_SHIFT) | |
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(FIR_OP_RBW << FIR_OP2_SHIFT)); |
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out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); |
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/* |
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* although currently it's 8 bytes for READID, we always read |
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* the maximum 256 bytes(for PARAM) |
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*/ |
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out_be32(&lbc->fbcr, 256); |
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elbc_fcm_ctrl->read_bytes = 256; |
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elbc_fcm_ctrl->use_mdr = 1; |
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elbc_fcm_ctrl->mdr = column; |
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set_addr(mtd, 0, 0, 0); |
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fsl_elbc_run_command(mtd); |
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return; |
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/* ERASE1 stores the block and page address */ |
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case NAND_CMD_ERASE1: |
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dev_vdbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " |
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"page_addr: 0x%x.\n", page_addr); |
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set_addr(mtd, 0, page_addr, 0); |
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return; |
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/* ERASE2 uses the block and page address from ERASE1 */ |
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case NAND_CMD_ERASE2: |
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dev_vdbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); |
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out_be32(&lbc->fir, |
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(FIR_OP_CM0 << FIR_OP0_SHIFT) | |
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(FIR_OP_PA << FIR_OP1_SHIFT) | |
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(FIR_OP_CM2 << FIR_OP2_SHIFT) | |
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(FIR_OP_CW1 << FIR_OP3_SHIFT) | |
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(FIR_OP_RS << FIR_OP4_SHIFT)); |
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out_be32(&lbc->fcr, |
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(NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | |
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(NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
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(NAND_CMD_ERASE2 << FCR_CMD2_SHIFT)); |
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out_be32(&lbc->fbcr, 0); |
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elbc_fcm_ctrl->read_bytes = 0; |
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elbc_fcm_ctrl->use_mdr = 1; |
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fsl_elbc_run_command(mtd); |
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return; |
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/* SEQIN sets up the addr buffer and all registers except the length */ |
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case NAND_CMD_SEQIN: { |
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__be32 fcr; |
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dev_vdbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " |
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"page_addr: 0x%x, column: 0x%x.\n", |
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page_addr, column); |
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elbc_fcm_ctrl->column = column; |
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elbc_fcm_ctrl->use_mdr = 1; |
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if (column >= mtd->writesize) { |
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/* OOB area */ |
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column -= mtd->writesize; |
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elbc_fcm_ctrl->oob = 1; |
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} else { |
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WARN_ON(column != 0); |
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elbc_fcm_ctrl->oob = 0; |
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} |
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fcr = (NAND_CMD_STATUS << FCR_CMD1_SHIFT) | |
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(NAND_CMD_SEQIN << FCR_CMD2_SHIFT) | |
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(NAND_CMD_PAGEPROG << FCR_CMD3_SHIFT); |
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if (priv->page_size) { |
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out_be32(&lbc->fir, |
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(FIR_OP_CM2 << FIR_OP0_SHIFT) | |
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(FIR_OP_CA << FIR_OP1_SHIFT) | |
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(FIR_OP_PA << FIR_OP2_SHIFT) | |
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(FIR_OP_WB << FIR_OP3_SHIFT) | |
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(FIR_OP_CM3 << FIR_OP4_SHIFT) | |
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(FIR_OP_CW1 << FIR_OP5_SHIFT) | |
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(FIR_OP_RS << FIR_OP6_SHIFT)); |
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} else { |
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out_be32(&lbc->fir, |
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(FIR_OP_CM0 << FIR_OP0_SHIFT) | |
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(FIR_OP_CM2 << FIR_OP1_SHIFT) | |
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(FIR_OP_CA << FIR_OP2_SHIFT) | |
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(FIR_OP_PA << FIR_OP3_SHIFT) | |
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(FIR_OP_WB << FIR_OP4_SHIFT) | |
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(FIR_OP_CM3 << FIR_OP5_SHIFT) | |
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(FIR_OP_CW1 << FIR_OP6_SHIFT) | |
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(FIR_OP_RS << FIR_OP7_SHIFT)); |
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if (elbc_fcm_ctrl->oob) |
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/* OOB area --> READOOB */ |
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fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; |
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else |
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/* First 256 bytes --> READ0 */ |
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fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; |
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} |
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out_be32(&lbc->fcr, fcr); |
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set_addr(mtd, column, page_addr, elbc_fcm_ctrl->oob); |
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return; |
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} |
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/* PAGEPROG reuses all of the setup from SEQIN and adds the length */ |
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case NAND_CMD_PAGEPROG: { |
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dev_vdbg(priv->dev, |
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"fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " |
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"writing %d bytes.\n", elbc_fcm_ctrl->index); |
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|
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/* if the write did not start at 0 or is not a full page |
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* then set the exact length, otherwise use a full page |
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* write so the HW generates the ECC. |
|
*/ |
|
if (elbc_fcm_ctrl->oob || elbc_fcm_ctrl->column != 0 || |
|
elbc_fcm_ctrl->index != mtd->writesize + mtd->oobsize) |
|
out_be32(&lbc->fbcr, |
|
elbc_fcm_ctrl->index - elbc_fcm_ctrl->column); |
|
else |
|
out_be32(&lbc->fbcr, 0); |
|
|
|
fsl_elbc_run_command(mtd); |
|
return; |
|
} |
|
|
|
/* CMD_STATUS must read the status byte while CEB is active */ |
|
/* Note - it does not wait for the ready line */ |
|
case NAND_CMD_STATUS: |
|
out_be32(&lbc->fir, |
|
(FIR_OP_CM0 << FIR_OP0_SHIFT) | |
|
(FIR_OP_RBW << FIR_OP1_SHIFT)); |
|
out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); |
|
out_be32(&lbc->fbcr, 1); |
|
set_addr(mtd, 0, 0, 0); |
|
elbc_fcm_ctrl->read_bytes = 1; |
|
|
|
fsl_elbc_run_command(mtd); |
|
|
|
/* The chip always seems to report that it is |
|
* write-protected, even when it is not. |
|
*/ |
|
setbits8(elbc_fcm_ctrl->addr, NAND_STATUS_WP); |
|
return; |
|
|
|
/* RESET without waiting for the ready line */ |
|
case NAND_CMD_RESET: |
|
dev_dbg(priv->dev, "fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); |
|
out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); |
|
out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); |
|
fsl_elbc_run_command(mtd); |
|
return; |
|
|
|
default: |
|
dev_err(priv->dev, |
|
"fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", |
|
command); |
|
} |
|
} |
|
|
|
static void fsl_elbc_select_chip(struct nand_chip *chip, int cs) |
|
{ |
|
/* The hardware does not seem to support multiple |
|
* chips per bank. |
|
*/ |
|
} |
|
|
|
/* |
|
* Write buf to the FCM Controller Data Buffer |
|
*/ |
|
static void fsl_elbc_write_buf(struct nand_chip *chip, const u8 *buf, int len) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
|
unsigned int bufsize = mtd->writesize + mtd->oobsize; |
|
|
|
if (len <= 0) { |
|
dev_err(priv->dev, "write_buf of %d bytes", len); |
|
elbc_fcm_ctrl->status = 0; |
|
return; |
|
} |
|
|
|
if ((unsigned int)len > bufsize - elbc_fcm_ctrl->index) { |
|
dev_err(priv->dev, |
|
"write_buf beyond end of buffer " |
|
"(%d requested, %u available)\n", |
|
len, bufsize - elbc_fcm_ctrl->index); |
|
len = bufsize - elbc_fcm_ctrl->index; |
|
} |
|
|
|
memcpy_toio(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], buf, len); |
|
/* |
|
* This is workaround for the weird elbc hangs during nand write, |
|
* Scott Wood says: "...perhaps difference in how long it takes a |
|
* write to make it through the localbus compared to a write to IMMR |
|
* is causing problems, and sync isn't helping for some reason." |
|
* Reading back the last byte helps though. |
|
*/ |
|
in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index] + len - 1); |
|
|
|
elbc_fcm_ctrl->index += len; |
|
} |
|
|
|
/* |
|
* read a byte from either the FCM hardware buffer if it has any data left |
|
* otherwise issue a command to read a single byte. |
|
*/ |
|
static u8 fsl_elbc_read_byte(struct nand_chip *chip) |
|
{ |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
|
|
|
/* If there are still bytes in the FCM, then use the next byte. */ |
|
if (elbc_fcm_ctrl->index < elbc_fcm_ctrl->read_bytes) |
|
return in_8(&elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index++]); |
|
|
|
dev_err(priv->dev, "read_byte beyond end of buffer\n"); |
|
return ERR_BYTE; |
|
} |
|
|
|
/* |
|
* Read from the FCM Controller Data Buffer |
|
*/ |
|
static void fsl_elbc_read_buf(struct nand_chip *chip, u8 *buf, int len) |
|
{ |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
|
int avail; |
|
|
|
if (len < 0) |
|
return; |
|
|
|
avail = min((unsigned int)len, |
|
elbc_fcm_ctrl->read_bytes - elbc_fcm_ctrl->index); |
|
memcpy_fromio(buf, &elbc_fcm_ctrl->addr[elbc_fcm_ctrl->index], avail); |
|
elbc_fcm_ctrl->index += avail; |
|
|
|
if (len > avail) |
|
dev_err(priv->dev, |
|
"read_buf beyond end of buffer " |
|
"(%d requested, %d available)\n", |
|
len, avail); |
|
} |
|
|
|
/* This function is called after Program and Erase Operations to |
|
* check for success or failure. |
|
*/ |
|
static int fsl_elbc_wait(struct nand_chip *chip) |
|
{ |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
|
|
|
if (elbc_fcm_ctrl->status != LTESR_CC) |
|
return NAND_STATUS_FAIL; |
|
|
|
/* The chip always seems to report that it is |
|
* write-protected, even when it is not. |
|
*/ |
|
return (elbc_fcm_ctrl->mdr & 0xff) | NAND_STATUS_WP; |
|
} |
|
|
|
static int fsl_elbc_read_page(struct nand_chip *chip, uint8_t *buf, |
|
int oob_required, int page) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
|
|
|
nand_read_page_op(chip, page, 0, buf, mtd->writesize); |
|
if (oob_required) |
|
fsl_elbc_read_buf(chip, chip->oob_poi, mtd->oobsize); |
|
|
|
if (fsl_elbc_wait(chip) & NAND_STATUS_FAIL) |
|
mtd->ecc_stats.failed++; |
|
|
|
return elbc_fcm_ctrl->max_bitflips; |
|
} |
|
|
|
/* ECC will be calculated automatically, and errors will be detected in |
|
* waitfunc. |
|
*/ |
|
static int fsl_elbc_write_page(struct nand_chip *chip, const uint8_t *buf, |
|
int oob_required, int page) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
|
|
nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize); |
|
fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); |
|
|
|
return nand_prog_page_end_op(chip); |
|
} |
|
|
|
/* ECC will be calculated automatically, and errors will be detected in |
|
* waitfunc. |
|
*/ |
|
static int fsl_elbc_write_subpage(struct nand_chip *chip, uint32_t offset, |
|
uint32_t data_len, const uint8_t *buf, |
|
int oob_required, int page) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
|
|
nand_prog_page_begin_op(chip, page, 0, NULL, 0); |
|
fsl_elbc_write_buf(chip, buf, mtd->writesize); |
|
fsl_elbc_write_buf(chip, chip->oob_poi, mtd->oobsize); |
|
return nand_prog_page_end_op(chip); |
|
} |
|
|
|
static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv) |
|
{ |
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; |
|
struct nand_chip *chip = &priv->chip; |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
|
|
dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank); |
|
|
|
/* Fill in fsl_elbc_mtd structure */ |
|
mtd->dev.parent = priv->dev; |
|
nand_set_flash_node(chip, priv->dev->of_node); |
|
|
|
/* set timeout to maximum */ |
|
priv->fmr = 15 << FMR_CWTO_SHIFT; |
|
if (in_be32(&lbc->bank[priv->bank].or) & OR_FCM_PGS) |
|
priv->fmr |= FMR_ECCM; |
|
|
|
/* fill in nand_chip structure */ |
|
/* set up function call table */ |
|
chip->legacy.read_byte = fsl_elbc_read_byte; |
|
chip->legacy.write_buf = fsl_elbc_write_buf; |
|
chip->legacy.read_buf = fsl_elbc_read_buf; |
|
chip->legacy.select_chip = fsl_elbc_select_chip; |
|
chip->legacy.cmdfunc = fsl_elbc_cmdfunc; |
|
chip->legacy.waitfunc = fsl_elbc_wait; |
|
chip->legacy.set_features = nand_get_set_features_notsupp; |
|
chip->legacy.get_features = nand_get_set_features_notsupp; |
|
|
|
chip->bbt_td = &bbt_main_descr; |
|
chip->bbt_md = &bbt_mirror_descr; |
|
|
|
/* set up nand options */ |
|
chip->bbt_options = NAND_BBT_USE_FLASH; |
|
|
|
chip->controller = &elbc_fcm_ctrl->controller; |
|
nand_set_controller_data(chip, priv); |
|
|
|
return 0; |
|
} |
|
|
|
static int fsl_elbc_attach_chip(struct nand_chip *chip) |
|
{ |
|
struct mtd_info *mtd = nand_to_mtd(chip); |
|
struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); |
|
struct fsl_lbc_ctrl *ctrl = priv->ctrl; |
|
struct fsl_lbc_regs __iomem *lbc = ctrl->regs; |
|
unsigned int al; |
|
|
|
switch (chip->ecc.engine_type) { |
|
/* |
|
* if ECC was not chosen in DT, decide whether to use HW or SW ECC from |
|
* CS Base Register |
|
*/ |
|
case NAND_ECC_ENGINE_TYPE_NONE: |
|
/* If CS Base Register selects full hardware ECC then use it */ |
|
if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == |
|
BR_DECC_CHK_GEN) { |
|
chip->ecc.read_page = fsl_elbc_read_page; |
|
chip->ecc.write_page = fsl_elbc_write_page; |
|
chip->ecc.write_subpage = fsl_elbc_write_subpage; |
|
|
|
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; |
|
mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops); |
|
chip->ecc.size = 512; |
|
chip->ecc.bytes = 3; |
|
chip->ecc.strength = 1; |
|
} else { |
|
/* otherwise fall back to default software ECC */ |
|
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; |
|
chip->ecc.algo = NAND_ECC_ALGO_HAMMING; |
|
} |
|
break; |
|
|
|
/* if SW ECC was chosen in DT, we do not need to set anything here */ |
|
case NAND_ECC_ENGINE_TYPE_SOFT: |
|
break; |
|
|
|
/* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */ |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
/* calculate FMR Address Length field */ |
|
al = 0; |
|
if (chip->pagemask & 0xffff0000) |
|
al++; |
|
if (chip->pagemask & 0xff000000) |
|
al++; |
|
|
|
priv->fmr |= al << FMR_AL_SHIFT; |
|
|
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", |
|
nanddev_ntargets(&chip->base)); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", |
|
nanddev_target_size(&chip->base)); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", |
|
chip->pagemask); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->legacy.chip_delay = %d\n", |
|
chip->legacy.chip_delay); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", |
|
chip->badblockpos); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", |
|
chip->chip_shift); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", |
|
chip->page_shift); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", |
|
chip->phys_erase_shift); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.engine_type = %d\n", |
|
chip->ecc.engine_type); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", |
|
chip->ecc.steps); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", |
|
chip->ecc.bytes); |
|
dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", |
|
chip->ecc.total); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n", |
|
mtd->ooblayout); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", |
|
mtd->erasesize); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", |
|
mtd->writesize); |
|
dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", |
|
mtd->oobsize); |
|
|
|
/* adjust Option Register and ECC to match Flash page size */ |
|
if (mtd->writesize == 512) { |
|
priv->page_size = 0; |
|
clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
|
} else if (mtd->writesize == 2048) { |
|
priv->page_size = 1; |
|
setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS); |
|
} else { |
|
dev_err(priv->dev, |
|
"fsl_elbc_init: page size %d is not supported\n", |
|
mtd->writesize); |
|
return -ENOTSUPP; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct nand_controller_ops fsl_elbc_controller_ops = { |
|
.attach_chip = fsl_elbc_attach_chip, |
|
}; |
|
|
|
static int fsl_elbc_chip_remove(struct fsl_elbc_mtd *priv) |
|
{ |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; |
|
struct mtd_info *mtd = nand_to_mtd(&priv->chip); |
|
|
|
kfree(mtd->name); |
|
|
|
if (priv->vbase) |
|
iounmap(priv->vbase); |
|
|
|
elbc_fcm_ctrl->chips[priv->bank] = NULL; |
|
kfree(priv); |
|
return 0; |
|
} |
|
|
|
static DEFINE_MUTEX(fsl_elbc_nand_mutex); |
|
|
|
static int fsl_elbc_nand_probe(struct platform_device *pdev) |
|
{ |
|
struct fsl_lbc_regs __iomem *lbc; |
|
struct fsl_elbc_mtd *priv; |
|
struct resource res; |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl; |
|
static const char *part_probe_types[] |
|
= { "cmdlinepart", "RedBoot", "ofpart", NULL }; |
|
int ret; |
|
int bank; |
|
struct device *dev; |
|
struct device_node *node = pdev->dev.of_node; |
|
struct mtd_info *mtd; |
|
|
|
if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) |
|
return -ENODEV; |
|
lbc = fsl_lbc_ctrl_dev->regs; |
|
dev = fsl_lbc_ctrl_dev->dev; |
|
|
|
/* get, allocate and map the memory resource */ |
|
ret = of_address_to_resource(node, 0, &res); |
|
if (ret) { |
|
dev_err(dev, "failed to get resource\n"); |
|
return ret; |
|
} |
|
|
|
/* find which chip select it is connected to */ |
|
for (bank = 0; bank < MAX_BANKS; bank++) |
|
if ((in_be32(&lbc->bank[bank].br) & BR_V) && |
|
(in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && |
|
(in_be32(&lbc->bank[bank].br) & |
|
in_be32(&lbc->bank[bank].or) & BR_BA) |
|
== fsl_lbc_addr(res.start)) |
|
break; |
|
|
|
if (bank >= MAX_BANKS) { |
|
dev_err(dev, "address did not match any chip selects\n"); |
|
return -ENODEV; |
|
} |
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
mutex_lock(&fsl_elbc_nand_mutex); |
|
if (!fsl_lbc_ctrl_dev->nand) { |
|
elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL); |
|
if (!elbc_fcm_ctrl) { |
|
mutex_unlock(&fsl_elbc_nand_mutex); |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
elbc_fcm_ctrl->counter++; |
|
|
|
nand_controller_init(&elbc_fcm_ctrl->controller); |
|
fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl; |
|
} else { |
|
elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
|
} |
|
mutex_unlock(&fsl_elbc_nand_mutex); |
|
|
|
elbc_fcm_ctrl->chips[bank] = priv; |
|
priv->bank = bank; |
|
priv->ctrl = fsl_lbc_ctrl_dev; |
|
priv->dev = &pdev->dev; |
|
dev_set_drvdata(priv->dev, priv); |
|
|
|
priv->vbase = ioremap(res.start, resource_size(&res)); |
|
if (!priv->vbase) { |
|
dev_err(dev, "failed to map chip region\n"); |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
|
|
mtd = nand_to_mtd(&priv->chip); |
|
mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); |
|
if (!nand_to_mtd(&priv->chip)->name) { |
|
ret = -ENOMEM; |
|
goto err; |
|
} |
|
|
|
ret = fsl_elbc_chip_init(priv); |
|
if (ret) |
|
goto err; |
|
|
|
priv->chip.controller->ops = &fsl_elbc_controller_ops; |
|
ret = nand_scan(&priv->chip, 1); |
|
if (ret) |
|
goto err; |
|
|
|
/* First look for RedBoot table or partitions on the command |
|
* line, these take precedence over device tree information */ |
|
ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0); |
|
if (ret) |
|
goto cleanup_nand; |
|
|
|
pr_info("eLBC NAND device at 0x%llx, bank %d\n", |
|
(unsigned long long)res.start, priv->bank); |
|
|
|
return 0; |
|
|
|
cleanup_nand: |
|
nand_cleanup(&priv->chip); |
|
err: |
|
fsl_elbc_chip_remove(priv); |
|
|
|
return ret; |
|
} |
|
|
|
static int fsl_elbc_nand_remove(struct platform_device *pdev) |
|
{ |
|
struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand; |
|
struct fsl_elbc_mtd *priv = dev_get_drvdata(&pdev->dev); |
|
struct nand_chip *chip = &priv->chip; |
|
int ret; |
|
|
|
ret = mtd_device_unregister(nand_to_mtd(chip)); |
|
WARN_ON(ret); |
|
nand_cleanup(chip); |
|
|
|
fsl_elbc_chip_remove(priv); |
|
|
|
mutex_lock(&fsl_elbc_nand_mutex); |
|
elbc_fcm_ctrl->counter--; |
|
if (!elbc_fcm_ctrl->counter) { |
|
fsl_lbc_ctrl_dev->nand = NULL; |
|
kfree(elbc_fcm_ctrl); |
|
} |
|
mutex_unlock(&fsl_elbc_nand_mutex); |
|
|
|
return 0; |
|
|
|
} |
|
|
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static const struct of_device_id fsl_elbc_nand_match[] = { |
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{ .compatible = "fsl,elbc-fcm-nand", }, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, fsl_elbc_nand_match); |
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|
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static struct platform_driver fsl_elbc_nand_driver = { |
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.driver = { |
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.name = "fsl,elbc-fcm-nand", |
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.of_match_table = fsl_elbc_nand_match, |
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}, |
|
.probe = fsl_elbc_nand_probe, |
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.remove = fsl_elbc_nand_remove, |
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}; |
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|
|
module_platform_driver(fsl_elbc_nand_driver); |
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|
|
MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Freescale"); |
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MODULE_DESCRIPTION("Freescale Enhanced Local Bus Controller MTD NAND driver");
|
|
|