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443 lines
11 KiB
443 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2006 Jonathan McDowell <[email protected]> |
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* |
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* Derived from drivers/mtd/nand/toto.c (removed in v2.6.28) |
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* Copyright (c) 2003 Texas Instruments |
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* Copyright (c) 2002 Thomas Gleixner <[email protected]> |
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* |
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* Converted to platform driver by Janusz Krzysztofik <[email protected]> |
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* Partially stolen from plat_nand.c |
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* |
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* Overview: |
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* This is a device driver for the NAND flash device found on the |
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* Amstrad E3 (Delta). |
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*/ |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/nand-gpio.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/sizes.h> |
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/* |
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* MTD structure for E3 (Delta) |
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*/ |
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struct gpio_nand { |
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struct nand_controller base; |
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struct nand_chip nand_chip; |
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struct gpio_desc *gpiod_rdy; |
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struct gpio_desc *gpiod_nce; |
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struct gpio_desc *gpiod_nre; |
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struct gpio_desc *gpiod_nwp; |
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struct gpio_desc *gpiod_nwe; |
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struct gpio_desc *gpiod_ale; |
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struct gpio_desc *gpiod_cle; |
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struct gpio_descs *data_gpiods; |
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bool data_in; |
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unsigned int tRP; |
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unsigned int tWP; |
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u8 (*io_read)(struct gpio_nand *this); |
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void (*io_write)(struct gpio_nand *this, u8 byte); |
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}; |
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static void gpio_nand_write_commit(struct gpio_nand *priv) |
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{ |
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gpiod_set_value(priv->gpiod_nwe, 1); |
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ndelay(priv->tWP); |
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gpiod_set_value(priv->gpiod_nwe, 0); |
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} |
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static void gpio_nand_io_write(struct gpio_nand *priv, u8 byte) |
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{ |
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struct gpio_descs *data_gpiods = priv->data_gpiods; |
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DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, }; |
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gpiod_set_raw_array_value(data_gpiods->ndescs, data_gpiods->desc, |
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data_gpiods->info, values); |
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gpio_nand_write_commit(priv); |
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} |
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static void gpio_nand_dir_output(struct gpio_nand *priv, u8 byte) |
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{ |
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struct gpio_descs *data_gpiods = priv->data_gpiods; |
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DECLARE_BITMAP(values, BITS_PER_TYPE(byte)) = { byte, }; |
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int i; |
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for (i = 0; i < data_gpiods->ndescs; i++) |
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gpiod_direction_output_raw(data_gpiods->desc[i], |
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test_bit(i, values)); |
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gpio_nand_write_commit(priv); |
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priv->data_in = false; |
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} |
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static u8 gpio_nand_io_read(struct gpio_nand *priv) |
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{ |
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u8 res; |
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struct gpio_descs *data_gpiods = priv->data_gpiods; |
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DECLARE_BITMAP(values, BITS_PER_TYPE(res)) = { 0, }; |
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gpiod_set_value(priv->gpiod_nre, 1); |
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ndelay(priv->tRP); |
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gpiod_get_raw_array_value(data_gpiods->ndescs, data_gpiods->desc, |
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data_gpiods->info, values); |
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gpiod_set_value(priv->gpiod_nre, 0); |
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res = values[0]; |
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return res; |
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} |
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static void gpio_nand_dir_input(struct gpio_nand *priv) |
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{ |
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struct gpio_descs *data_gpiods = priv->data_gpiods; |
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int i; |
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for (i = 0; i < data_gpiods->ndescs; i++) |
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gpiod_direction_input(data_gpiods->desc[i]); |
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priv->data_in = true; |
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} |
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static void gpio_nand_write_buf(struct gpio_nand *priv, const u8 *buf, int len) |
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{ |
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int i = 0; |
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if (len > 0 && priv->data_in) |
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gpio_nand_dir_output(priv, buf[i++]); |
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while (i < len) |
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priv->io_write(priv, buf[i++]); |
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} |
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static void gpio_nand_read_buf(struct gpio_nand *priv, u8 *buf, int len) |
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{ |
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int i; |
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if (priv->data_gpiods && !priv->data_in) |
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gpio_nand_dir_input(priv); |
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for (i = 0; i < len; i++) |
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buf[i] = priv->io_read(priv); |
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} |
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static void gpio_nand_ctrl_cs(struct gpio_nand *priv, bool assert) |
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{ |
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gpiod_set_value(priv->gpiod_nce, assert); |
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} |
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static int gpio_nand_exec_op(struct nand_chip *this, |
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const struct nand_operation *op, bool check_only) |
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{ |
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struct gpio_nand *priv = nand_get_controller_data(this); |
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const struct nand_op_instr *instr; |
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int ret = 0; |
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if (check_only) |
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return 0; |
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gpio_nand_ctrl_cs(priv, 1); |
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for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) { |
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switch (instr->type) { |
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case NAND_OP_CMD_INSTR: |
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gpiod_set_value(priv->gpiod_cle, 1); |
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gpio_nand_write_buf(priv, &instr->ctx.cmd.opcode, 1); |
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gpiod_set_value(priv->gpiod_cle, 0); |
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break; |
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case NAND_OP_ADDR_INSTR: |
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gpiod_set_value(priv->gpiod_ale, 1); |
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gpio_nand_write_buf(priv, instr->ctx.addr.addrs, |
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instr->ctx.addr.naddrs); |
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gpiod_set_value(priv->gpiod_ale, 0); |
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break; |
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case NAND_OP_DATA_IN_INSTR: |
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gpio_nand_read_buf(priv, instr->ctx.data.buf.in, |
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instr->ctx.data.len); |
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break; |
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case NAND_OP_DATA_OUT_INSTR: |
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gpio_nand_write_buf(priv, instr->ctx.data.buf.out, |
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instr->ctx.data.len); |
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break; |
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case NAND_OP_WAITRDY_INSTR: |
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ret = priv->gpiod_rdy ? |
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nand_gpio_waitrdy(this, priv->gpiod_rdy, |
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instr->ctx.waitrdy.timeout_ms) : |
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nand_soft_waitrdy(this, |
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instr->ctx.waitrdy.timeout_ms); |
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break; |
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} |
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if (ret) |
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break; |
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} |
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gpio_nand_ctrl_cs(priv, 0); |
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return ret; |
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} |
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static int gpio_nand_setup_interface(struct nand_chip *this, int csline, |
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const struct nand_interface_config *cf) |
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{ |
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struct gpio_nand *priv = nand_get_controller_data(this); |
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const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf); |
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struct device *dev = &nand_to_mtd(this)->dev; |
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if (IS_ERR(sdr)) |
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return PTR_ERR(sdr); |
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if (csline == NAND_DATA_IFACE_CHECK_ONLY) |
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return 0; |
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if (priv->gpiod_nre) { |
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priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000); |
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dev_dbg(dev, "using %u ns read pulse width\n", priv->tRP); |
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} |
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priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000); |
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dev_dbg(dev, "using %u ns write pulse width\n", priv->tWP); |
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return 0; |
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} |
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static int gpio_nand_attach_chip(struct nand_chip *chip) |
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{ |
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chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; |
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if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) |
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chip->ecc.algo = NAND_ECC_ALGO_HAMMING; |
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return 0; |
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} |
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static const struct nand_controller_ops gpio_nand_ops = { |
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.exec_op = gpio_nand_exec_op, |
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.attach_chip = gpio_nand_attach_chip, |
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.setup_interface = gpio_nand_setup_interface, |
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}; |
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/* |
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* Main initialization routine |
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*/ |
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static int gpio_nand_probe(struct platform_device *pdev) |
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{ |
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struct gpio_nand_platdata *pdata = dev_get_platdata(&pdev->dev); |
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const struct mtd_partition *partitions = NULL; |
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int num_partitions = 0; |
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struct gpio_nand *priv; |
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struct nand_chip *this; |
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struct mtd_info *mtd; |
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int (*probe)(struct platform_device *pdev, struct gpio_nand *priv); |
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int err = 0; |
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if (pdata) { |
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partitions = pdata->parts; |
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num_partitions = pdata->num_parts; |
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} |
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/* Allocate memory for MTD device structure and private data */ |
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priv = devm_kzalloc(&pdev->dev, sizeof(struct gpio_nand), |
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GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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this = &priv->nand_chip; |
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mtd = nand_to_mtd(this); |
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mtd->dev.parent = &pdev->dev; |
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nand_set_controller_data(this, priv); |
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nand_set_flash_node(this, pdev->dev.of_node); |
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priv->gpiod_rdy = devm_gpiod_get_optional(&pdev->dev, "rdy", GPIOD_IN); |
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if (IS_ERR(priv->gpiod_rdy)) { |
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err = PTR_ERR(priv->gpiod_rdy); |
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dev_warn(&pdev->dev, "RDY GPIO request failed (%d)\n", err); |
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return err; |
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} |
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platform_set_drvdata(pdev, priv); |
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/* Set chip enabled but write protected */ |
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priv->gpiod_nwp = devm_gpiod_get_optional(&pdev->dev, "nwp", |
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GPIOD_OUT_HIGH); |
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if (IS_ERR(priv->gpiod_nwp)) { |
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err = PTR_ERR(priv->gpiod_nwp); |
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dev_err(&pdev->dev, "NWP GPIO request failed (%d)\n", err); |
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return err; |
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} |
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priv->gpiod_nce = devm_gpiod_get_optional(&pdev->dev, "nce", |
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GPIOD_OUT_LOW); |
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if (IS_ERR(priv->gpiod_nce)) { |
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err = PTR_ERR(priv->gpiod_nce); |
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dev_err(&pdev->dev, "NCE GPIO request failed (%d)\n", err); |
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return err; |
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} |
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priv->gpiod_nre = devm_gpiod_get_optional(&pdev->dev, "nre", |
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GPIOD_OUT_LOW); |
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if (IS_ERR(priv->gpiod_nre)) { |
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err = PTR_ERR(priv->gpiod_nre); |
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dev_err(&pdev->dev, "NRE GPIO request failed (%d)\n", err); |
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return err; |
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} |
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priv->gpiod_nwe = devm_gpiod_get_optional(&pdev->dev, "nwe", |
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GPIOD_OUT_LOW); |
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if (IS_ERR(priv->gpiod_nwe)) { |
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err = PTR_ERR(priv->gpiod_nwe); |
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dev_err(&pdev->dev, "NWE GPIO request failed (%d)\n", err); |
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return err; |
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} |
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priv->gpiod_ale = devm_gpiod_get(&pdev->dev, "ale", GPIOD_OUT_LOW); |
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if (IS_ERR(priv->gpiod_ale)) { |
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err = PTR_ERR(priv->gpiod_ale); |
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dev_err(&pdev->dev, "ALE GPIO request failed (%d)\n", err); |
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return err; |
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} |
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priv->gpiod_cle = devm_gpiod_get(&pdev->dev, "cle", GPIOD_OUT_LOW); |
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if (IS_ERR(priv->gpiod_cle)) { |
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err = PTR_ERR(priv->gpiod_cle); |
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dev_err(&pdev->dev, "CLE GPIO request failed (%d)\n", err); |
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return err; |
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} |
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/* Request array of data pins, initialize them as input */ |
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priv->data_gpiods = devm_gpiod_get_array_optional(&pdev->dev, "data", |
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GPIOD_IN); |
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if (IS_ERR(priv->data_gpiods)) { |
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err = PTR_ERR(priv->data_gpiods); |
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dev_err(&pdev->dev, "data GPIO request failed: %d\n", err); |
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return err; |
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} |
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if (priv->data_gpiods) { |
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if (!priv->gpiod_nwe) { |
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dev_err(&pdev->dev, |
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"mandatory NWE pin not provided by platform\n"); |
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return -ENODEV; |
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} |
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priv->io_read = gpio_nand_io_read; |
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priv->io_write = gpio_nand_io_write; |
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priv->data_in = true; |
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} |
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if (pdev->id_entry) |
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probe = (void *) pdev->id_entry->driver_data; |
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else |
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probe = of_device_get_match_data(&pdev->dev); |
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if (probe) |
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err = probe(pdev, priv); |
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if (err) |
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return err; |
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if (!priv->io_read || !priv->io_write) { |
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dev_err(&pdev->dev, "incomplete device configuration\n"); |
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return -ENODEV; |
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} |
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/* Initialize the NAND controller object embedded in gpio_nand. */ |
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priv->base.ops = &gpio_nand_ops; |
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nand_controller_init(&priv->base); |
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this->controller = &priv->base; |
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/* |
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* FIXME: We should release write protection only after nand_scan() to |
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* be on the safe side but we can't do that until we have a generic way |
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* to assert/deassert WP from the core. Even if the core shouldn't |
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* write things in the nand_scan() path, it should have control on this |
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* pin just in case we ever need to disable write protection during |
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* chip detection/initialization. |
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*/ |
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/* Release write protection */ |
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gpiod_set_value(priv->gpiod_nwp, 0); |
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/* Scan to find existence of the device */ |
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err = nand_scan(this, 1); |
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if (err) |
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return err; |
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/* Register the partitions */ |
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err = mtd_device_register(mtd, partitions, num_partitions); |
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if (err) |
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goto err_nand_cleanup; |
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return 0; |
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err_nand_cleanup: |
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nand_cleanup(this); |
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return err; |
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} |
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/* |
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* Clean up routine |
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*/ |
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static int gpio_nand_remove(struct platform_device *pdev) |
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{ |
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struct gpio_nand *priv = platform_get_drvdata(pdev); |
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struct mtd_info *mtd = nand_to_mtd(&priv->nand_chip); |
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int ret; |
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/* Apply write protection */ |
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gpiod_set_value(priv->gpiod_nwp, 1); |
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/* Unregister device */ |
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ret = mtd_device_unregister(mtd); |
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WARN_ON(ret); |
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nand_cleanup(mtd_to_nand(mtd)); |
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return 0; |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id gpio_nand_of_id_table[] = { |
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{ |
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/* sentinel */ |
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}, |
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}; |
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MODULE_DEVICE_TABLE(of, gpio_nand_of_id_table); |
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#endif |
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static const struct platform_device_id gpio_nand_plat_id_table[] = { |
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{ |
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.name = "ams-delta-nand", |
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}, { |
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/* sentinel */ |
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}, |
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}; |
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MODULE_DEVICE_TABLE(platform, gpio_nand_plat_id_table); |
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static struct platform_driver gpio_nand_driver = { |
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.probe = gpio_nand_probe, |
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.remove = gpio_nand_remove, |
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.id_table = gpio_nand_plat_id_table, |
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.driver = { |
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.name = "ams-delta-nand", |
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.of_match_table = of_match_ptr(gpio_nand_of_id_table), |
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}, |
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}; |
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module_platform_driver(gpio_nand_driver); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_AUTHOR("Jonathan McDowell <[email protected]>"); |
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MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
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