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682 lines
18 KiB
682 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* MTD driver for the 28F160F3 Flash Memory (non-CFI) on LART. |
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* |
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* Author: Abraham vd Merwe <[email protected]> |
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* |
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* Copyright (c) 2001, 2d3D, Inc. |
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* |
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* References: |
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* |
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* [1] 3 Volt Fast Boot Block Flash Memory" Intel Datasheet |
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* - Order Number: 290644-005 |
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* - January 2000 |
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* |
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* [2] MTD internal API documentation |
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* - http://www.linux-mtd.infradead.org/ |
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* |
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* Limitations: |
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* |
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* Even though this driver is written for 3 Volt Fast Boot |
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* Block Flash Memory, it is rather specific to LART. With |
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* Minor modifications, notably the without data/address line |
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* mangling and different bus settings, etc. it should be |
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* trivial to adapt to other platforms. |
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* |
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* If somebody would sponsor me a different board, I'll |
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* adapt the driver (: |
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*/ |
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/* debugging */ |
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//#define LART_DEBUG |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#ifndef CONFIG_SA1100_LART |
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#error This is for LART architecture only |
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#endif |
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static char module_name[] = "lart"; |
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/* |
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* These values is specific to 28Fxxxx3 flash memory. |
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* See section 2.3.1 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet |
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*/ |
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#define FLASH_BLOCKSIZE_PARAM (4096 * BUSWIDTH) |
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#define FLASH_NUMBLOCKS_16m_PARAM 8 |
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#define FLASH_NUMBLOCKS_8m_PARAM 8 |
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/* |
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* These values is specific to 28Fxxxx3 flash memory. |
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* See section 2.3.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet |
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*/ |
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#define FLASH_BLOCKSIZE_MAIN (32768 * BUSWIDTH) |
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#define FLASH_NUMBLOCKS_16m_MAIN 31 |
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#define FLASH_NUMBLOCKS_8m_MAIN 15 |
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/* |
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* These values are specific to LART |
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*/ |
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/* general */ |
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#define BUSWIDTH 4 /* don't change this - a lot of the code _will_ break if you change this */ |
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#define FLASH_OFFSET 0xe8000000 /* see linux/arch/arm/mach-sa1100/lart.c */ |
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/* blob */ |
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#define NUM_BLOB_BLOCKS FLASH_NUMBLOCKS_16m_PARAM |
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#define PART_BLOB_START 0x00000000 |
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#define PART_BLOB_LEN (NUM_BLOB_BLOCKS * FLASH_BLOCKSIZE_PARAM) |
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/* kernel */ |
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#define NUM_KERNEL_BLOCKS 7 |
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#define PART_KERNEL_START (PART_BLOB_START + PART_BLOB_LEN) |
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#define PART_KERNEL_LEN (NUM_KERNEL_BLOCKS * FLASH_BLOCKSIZE_MAIN) |
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/* initial ramdisk */ |
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#define NUM_INITRD_BLOCKS 24 |
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#define PART_INITRD_START (PART_KERNEL_START + PART_KERNEL_LEN) |
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#define PART_INITRD_LEN (NUM_INITRD_BLOCKS * FLASH_BLOCKSIZE_MAIN) |
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/* |
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* See section 4.0 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet |
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*/ |
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#define READ_ARRAY 0x00FF00FF /* Read Array/Reset */ |
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#define READ_ID_CODES 0x00900090 /* Read Identifier Codes */ |
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#define ERASE_SETUP 0x00200020 /* Block Erase */ |
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#define ERASE_CONFIRM 0x00D000D0 /* Block Erase and Program Resume */ |
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#define PGM_SETUP 0x00400040 /* Program */ |
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#define STATUS_READ 0x00700070 /* Read Status Register */ |
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#define STATUS_CLEAR 0x00500050 /* Clear Status Register */ |
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#define STATUS_BUSY 0x00800080 /* Write State Machine Status (WSMS) */ |
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#define STATUS_ERASE_ERR 0x00200020 /* Erase Status (ES) */ |
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#define STATUS_PGM_ERR 0x00100010 /* Program Status (PS) */ |
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/* |
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* See section 4.2 in "3 Volt Fast Boot Block Flash Memory" Intel Datasheet |
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*/ |
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#define FLASH_MANUFACTURER 0x00890089 |
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#define FLASH_DEVICE_8mbit_TOP 0x88f188f1 |
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#define FLASH_DEVICE_8mbit_BOTTOM 0x88f288f2 |
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#define FLASH_DEVICE_16mbit_TOP 0x88f388f3 |
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#define FLASH_DEVICE_16mbit_BOTTOM 0x88f488f4 |
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/***************************************************************************************************/ |
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/* |
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* The data line mapping on LART is as follows: |
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* |
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* U2 CPU | U3 CPU |
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* ------------------- |
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* 0 20 | 0 12 |
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* 1 22 | 1 14 |
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* 2 19 | 2 11 |
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* 3 17 | 3 9 |
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* 4 24 | 4 0 |
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* 5 26 | 5 2 |
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* 6 31 | 6 7 |
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* 7 29 | 7 5 |
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* 8 21 | 8 13 |
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* 9 23 | 9 15 |
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* 10 18 | 10 10 |
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* 11 16 | 11 8 |
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* 12 25 | 12 1 |
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* 13 27 | 13 3 |
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* 14 30 | 14 6 |
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* 15 28 | 15 4 |
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*/ |
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/* Mangle data (x) */ |
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#define DATA_TO_FLASH(x) \ |
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( \ |
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(((x) & 0x08009000) >> 11) + \ |
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(((x) & 0x00002000) >> 10) + \ |
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(((x) & 0x04004000) >> 8) + \ |
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(((x) & 0x00000010) >> 4) + \ |
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(((x) & 0x91000820) >> 3) + \ |
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(((x) & 0x22080080) >> 2) + \ |
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((x) & 0x40000400) + \ |
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(((x) & 0x00040040) << 1) + \ |
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(((x) & 0x00110000) << 4) + \ |
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(((x) & 0x00220100) << 5) + \ |
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(((x) & 0x00800208) << 6) + \ |
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(((x) & 0x00400004) << 9) + \ |
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(((x) & 0x00000001) << 12) + \ |
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(((x) & 0x00000002) << 13) \ |
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) |
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/* Unmangle data (x) */ |
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#define FLASH_TO_DATA(x) \ |
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( \ |
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(((x) & 0x00010012) << 11) + \ |
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(((x) & 0x00000008) << 10) + \ |
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(((x) & 0x00040040) << 8) + \ |
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(((x) & 0x00000001) << 4) + \ |
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(((x) & 0x12200104) << 3) + \ |
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(((x) & 0x08820020) << 2) + \ |
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((x) & 0x40000400) + \ |
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(((x) & 0x00080080) >> 1) + \ |
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(((x) & 0x01100000) >> 4) + \ |
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(((x) & 0x04402000) >> 5) + \ |
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(((x) & 0x20008200) >> 6) + \ |
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(((x) & 0x80000800) >> 9) + \ |
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(((x) & 0x00001000) >> 12) + \ |
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(((x) & 0x00004000) >> 13) \ |
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) |
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/* |
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* The address line mapping on LART is as follows: |
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* |
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* U3 CPU | U2 CPU |
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* ------------------- |
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* 0 2 | 0 2 |
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* 1 3 | 1 3 |
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* 2 9 | 2 9 |
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* 3 13 | 3 8 |
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* 4 8 | 4 7 |
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* 5 12 | 5 6 |
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* 6 11 | 6 5 |
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* 7 10 | 7 4 |
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* 8 4 | 8 10 |
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* 9 5 | 9 11 |
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* 10 6 | 10 12 |
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* 11 7 | 11 13 |
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* |
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* BOOT BLOCK BOUNDARY |
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* |
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* 12 15 | 12 15 |
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* 13 14 | 13 14 |
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* 14 16 | 14 16 |
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* |
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* MAIN BLOCK BOUNDARY |
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* |
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* 15 17 | 15 18 |
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* 16 18 | 16 17 |
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* 17 20 | 17 20 |
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* 18 19 | 18 19 |
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* 19 21 | 19 21 |
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* |
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* As we can see from above, the addresses aren't mangled across |
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* block boundaries, so we don't need to worry about address |
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* translations except for sending/reading commands during |
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* initialization |
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*/ |
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/* Mangle address (x) on chip U2 */ |
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#define ADDR_TO_FLASH_U2(x) \ |
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( \ |
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(((x) & 0x00000f00) >> 4) + \ |
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(((x) & 0x00042000) << 1) + \ |
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(((x) & 0x0009c003) << 2) + \ |
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(((x) & 0x00021080) << 3) + \ |
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(((x) & 0x00000010) << 4) + \ |
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(((x) & 0x00000040) << 5) + \ |
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(((x) & 0x00000024) << 7) + \ |
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(((x) & 0x00000008) << 10) \ |
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) |
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/* Unmangle address (x) on chip U2 */ |
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#define FLASH_U2_TO_ADDR(x) \ |
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( \ |
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(((x) << 4) & 0x00000f00) + \ |
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(((x) >> 1) & 0x00042000) + \ |
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(((x) >> 2) & 0x0009c003) + \ |
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(((x) >> 3) & 0x00021080) + \ |
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(((x) >> 4) & 0x00000010) + \ |
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(((x) >> 5) & 0x00000040) + \ |
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(((x) >> 7) & 0x00000024) + \ |
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(((x) >> 10) & 0x00000008) \ |
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) |
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/* Mangle address (x) on chip U3 */ |
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#define ADDR_TO_FLASH_U3(x) \ |
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( \ |
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(((x) & 0x00000080) >> 3) + \ |
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(((x) & 0x00000040) >> 1) + \ |
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(((x) & 0x00052020) << 1) + \ |
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(((x) & 0x00084f03) << 2) + \ |
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(((x) & 0x00029010) << 3) + \ |
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(((x) & 0x00000008) << 5) + \ |
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(((x) & 0x00000004) << 7) \ |
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) |
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/* Unmangle address (x) on chip U3 */ |
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#define FLASH_U3_TO_ADDR(x) \ |
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( \ |
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(((x) << 3) & 0x00000080) + \ |
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(((x) << 1) & 0x00000040) + \ |
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(((x) >> 1) & 0x00052020) + \ |
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(((x) >> 2) & 0x00084f03) + \ |
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(((x) >> 3) & 0x00029010) + \ |
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(((x) >> 5) & 0x00000008) + \ |
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(((x) >> 7) & 0x00000004) \ |
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) |
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/***************************************************************************************************/ |
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static __u8 read8 (__u32 offset) |
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{ |
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volatile __u8 *data = (__u8 *) (FLASH_OFFSET + offset); |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.2x\n", __func__, offset, *data); |
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#endif |
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return (*data); |
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} |
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static __u32 read32 (__u32 offset) |
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{ |
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volatile __u32 *data = (__u32 *) (FLASH_OFFSET + offset); |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(): 0x%.8x -> 0x%.8x\n", __func__, offset, *data); |
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#endif |
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return (*data); |
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} |
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static void write32 (__u32 x,__u32 offset) |
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{ |
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volatile __u32 *data = (__u32 *) (FLASH_OFFSET + offset); |
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*data = x; |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, *data); |
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#endif |
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} |
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/***************************************************************************************************/ |
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/* |
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* Probe for 16mbit flash memory on a LART board without doing |
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* too much damage. Since we need to write 1 dword to memory, |
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* we're f**cked if this happens to be DRAM since we can't |
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* restore the memory (otherwise we might exit Read Array mode). |
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* |
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* Returns 1 if we found 16mbit flash memory on LART, 0 otherwise. |
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*/ |
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static int flash_probe (void) |
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{ |
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__u32 manufacturer,devtype; |
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/* setup "Read Identifier Codes" mode */ |
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write32 (DATA_TO_FLASH (READ_ID_CODES),0x00000000); |
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/* probe U2. U2/U3 returns the same data since the first 3 |
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* address lines is mangled in the same way */ |
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manufacturer = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000000))); |
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devtype = FLASH_TO_DATA (read32 (ADDR_TO_FLASH_U2 (0x00000001))); |
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/* put the flash back into command mode */ |
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write32 (DATA_TO_FLASH (READ_ARRAY),0x00000000); |
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return (manufacturer == FLASH_MANUFACTURER && (devtype == FLASH_DEVICE_16mbit_TOP || devtype == FLASH_DEVICE_16mbit_BOTTOM)); |
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} |
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/* |
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* Erase one block of flash memory at offset ``offset'' which is any |
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* address within the block which should be erased. |
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* |
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* Returns 1 if successful, 0 otherwise. |
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*/ |
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static inline int erase_block (__u32 offset) |
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{ |
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__u32 status; |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(): 0x%.8x\n", __func__, offset); |
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#endif |
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/* erase and confirm */ |
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write32 (DATA_TO_FLASH (ERASE_SETUP),offset); |
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write32 (DATA_TO_FLASH (ERASE_CONFIRM),offset); |
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/* wait for block erase to finish */ |
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do |
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{ |
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write32 (DATA_TO_FLASH (STATUS_READ),offset); |
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status = FLASH_TO_DATA (read32 (offset)); |
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} |
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while ((~status & STATUS_BUSY) != 0); |
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/* put the flash back into command mode */ |
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write32 (DATA_TO_FLASH (READ_ARRAY),offset); |
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/* was the erase successful? */ |
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if ((status & STATUS_ERASE_ERR)) |
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{ |
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printk (KERN_WARNING "%s: erase error at address 0x%.8x.\n",module_name,offset); |
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return (0); |
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} |
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return (1); |
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} |
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static int flash_erase (struct mtd_info *mtd,struct erase_info *instr) |
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{ |
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__u32 addr,len; |
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int i,first; |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n", __func__, instr->addr, instr->len); |
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#endif |
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/* |
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* check that both start and end of the requested erase are |
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* aligned with the erasesize at the appropriate addresses. |
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* |
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* skip all erase regions which are ended before the start of |
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* the requested erase. Actually, to save on the calculations, |
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* we skip to the first erase region which starts after the |
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* start of the requested erase, and then go back one. |
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*/ |
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for (i = 0; i < mtd->numeraseregions && instr->addr >= mtd->eraseregions[i].offset; i++) ; |
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i--; |
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/* |
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* ok, now i is pointing at the erase region in which this |
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* erase request starts. Check the start of the requested |
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* erase range is aligned with the erase size which is in |
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* effect here. |
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*/ |
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if (i < 0 || (instr->addr & (mtd->eraseregions[i].erasesize - 1))) |
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return -EINVAL; |
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/* Remember the erase region we start on */ |
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first = i; |
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/* |
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* next, check that the end of the requested erase is aligned |
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* with the erase region at that address. |
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* |
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* as before, drop back one to point at the region in which |
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* the address actually falls |
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*/ |
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for (; i < mtd->numeraseregions && instr->addr + instr->len >= mtd->eraseregions[i].offset; i++) ; |
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i--; |
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/* is the end aligned on a block boundary? */ |
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if (i < 0 || ((instr->addr + instr->len) & (mtd->eraseregions[i].erasesize - 1))) |
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return -EINVAL; |
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addr = instr->addr; |
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len = instr->len; |
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i = first; |
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/* now erase those blocks */ |
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while (len) |
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{ |
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if (!erase_block (addr)) |
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return (-EIO); |
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addr += mtd->eraseregions[i].erasesize; |
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len -= mtd->eraseregions[i].erasesize; |
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if (addr == mtd->eraseregions[i].offset + (mtd->eraseregions[i].erasesize * mtd->eraseregions[i].numblocks)) i++; |
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} |
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return (0); |
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} |
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static int flash_read (struct mtd_info *mtd,loff_t from,size_t len,size_t *retlen,u_char *buf) |
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{ |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n", __func__, (__u32)from, len); |
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#endif |
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/* we always read len bytes */ |
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*retlen = len; |
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/* first, we read bytes until we reach a dword boundary */ |
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if (from & (BUSWIDTH - 1)) |
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{ |
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int gap = BUSWIDTH - (from & (BUSWIDTH - 1)); |
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while (len && gap--) { |
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*buf++ = read8 (from++); |
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len--; |
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} |
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} |
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/* now we read dwords until we reach a non-dword boundary */ |
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while (len >= BUSWIDTH) |
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{ |
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*((__u32 *) buf) = read32 (from); |
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buf += BUSWIDTH; |
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from += BUSWIDTH; |
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len -= BUSWIDTH; |
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} |
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/* top up the last unaligned bytes */ |
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if (len & (BUSWIDTH - 1)) |
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while (len--) *buf++ = read8 (from++); |
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return (0); |
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} |
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/* |
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* Write one dword ``x'' to flash memory at offset ``offset''. ``offset'' |
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* must be 32 bits, i.e. it must be on a dword boundary. |
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* |
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* Returns 1 if successful, 0 otherwise. |
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*/ |
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static inline int write_dword (__u32 offset,__u32 x) |
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{ |
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__u32 status; |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(): 0x%.8x <- 0x%.8x\n", __func__, offset, x); |
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#endif |
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/* setup writing */ |
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write32 (DATA_TO_FLASH (PGM_SETUP),offset); |
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/* write the data */ |
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write32 (x,offset); |
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/* wait for the write to finish */ |
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do |
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{ |
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write32 (DATA_TO_FLASH (STATUS_READ),offset); |
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status = FLASH_TO_DATA (read32 (offset)); |
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} |
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while ((~status & STATUS_BUSY) != 0); |
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/* put the flash back into command mode */ |
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write32 (DATA_TO_FLASH (READ_ARRAY),offset); |
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/* was the write successful? */ |
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if ((status & STATUS_PGM_ERR) || read32 (offset) != x) |
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{ |
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printk (KERN_WARNING "%s: write error at address 0x%.8x.\n",module_name,offset); |
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return (0); |
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} |
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return (1); |
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} |
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static int flash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf) |
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{ |
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__u8 tmp[4]; |
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int i,n; |
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#ifdef LART_DEBUG |
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printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n", __func__, (__u32)to, len); |
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#endif |
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/* sanity checks */ |
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if (!len) return (0); |
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/* first, we write a 0xFF.... padded byte until we reach a dword boundary */ |
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if (to & (BUSWIDTH - 1)) |
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{ |
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__u32 aligned = to & ~(BUSWIDTH - 1); |
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int gap = to - aligned; |
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i = n = 0; |
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while (gap--) tmp[i++] = 0xFF; |
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while (len && i < BUSWIDTH) { |
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tmp[i++] = buf[n++]; |
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len--; |
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} |
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while (i < BUSWIDTH) tmp[i++] = 0xFF; |
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if (!write_dword (aligned,*((__u32 *) tmp))) return (-EIO); |
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to += n; |
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buf += n; |
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*retlen += n; |
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} |
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/* now we write dwords until we reach a non-dword boundary */ |
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while (len >= BUSWIDTH) |
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{ |
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if (!write_dword (to,*((__u32 *) buf))) return (-EIO); |
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to += BUSWIDTH; |
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buf += BUSWIDTH; |
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*retlen += BUSWIDTH; |
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len -= BUSWIDTH; |
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} |
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/* top up the last unaligned bytes, padded with 0xFF.... */ |
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if (len & (BUSWIDTH - 1)) |
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{ |
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i = n = 0; |
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while (len--) tmp[i++] = buf[n++]; |
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while (i < BUSWIDTH) tmp[i++] = 0xFF; |
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if (!write_dword (to,*((__u32 *) tmp))) return (-EIO); |
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*retlen += n; |
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} |
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return (0); |
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} |
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/***************************************************************************************************/ |
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static struct mtd_info mtd; |
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static struct mtd_erase_region_info erase_regions[] = { |
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/* parameter blocks */ |
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{ |
|
.offset = 0x00000000, |
|
.erasesize = FLASH_BLOCKSIZE_PARAM, |
|
.numblocks = FLASH_NUMBLOCKS_16m_PARAM, |
|
}, |
|
/* main blocks */ |
|
{ |
|
.offset = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM, |
|
.erasesize = FLASH_BLOCKSIZE_MAIN, |
|
.numblocks = FLASH_NUMBLOCKS_16m_MAIN, |
|
} |
|
}; |
|
|
|
static const struct mtd_partition lart_partitions[] = { |
|
/* blob */ |
|
{ |
|
.name = "blob", |
|
.offset = PART_BLOB_START, |
|
.size = PART_BLOB_LEN, |
|
}, |
|
/* kernel */ |
|
{ |
|
.name = "kernel", |
|
.offset = PART_KERNEL_START, /* MTDPART_OFS_APPEND */ |
|
.size = PART_KERNEL_LEN, |
|
}, |
|
/* initial ramdisk / file system */ |
|
{ |
|
.name = "file system", |
|
.offset = PART_INITRD_START, /* MTDPART_OFS_APPEND */ |
|
.size = PART_INITRD_LEN, /* MTDPART_SIZ_FULL */ |
|
} |
|
}; |
|
#define NUM_PARTITIONS ARRAY_SIZE(lart_partitions) |
|
|
|
static int __init lart_flash_init (void) |
|
{ |
|
int result; |
|
memset (&mtd,0,sizeof (mtd)); |
|
printk ("MTD driver for LART. Written by Abraham vd Merwe <[email protected]>\n"); |
|
printk ("%s: Probing for 28F160x3 flash on LART...\n",module_name); |
|
if (!flash_probe ()) |
|
{ |
|
printk (KERN_WARNING "%s: Found no LART compatible flash device\n",module_name); |
|
return (-ENXIO); |
|
} |
|
printk ("%s: This looks like a LART board to me.\n",module_name); |
|
mtd.name = module_name; |
|
mtd.type = MTD_NORFLASH; |
|
mtd.writesize = 1; |
|
mtd.writebufsize = 4; |
|
mtd.flags = MTD_CAP_NORFLASH; |
|
mtd.size = FLASH_BLOCKSIZE_PARAM * FLASH_NUMBLOCKS_16m_PARAM + FLASH_BLOCKSIZE_MAIN * FLASH_NUMBLOCKS_16m_MAIN; |
|
mtd.erasesize = FLASH_BLOCKSIZE_MAIN; |
|
mtd.numeraseregions = ARRAY_SIZE(erase_regions); |
|
mtd.eraseregions = erase_regions; |
|
mtd._erase = flash_erase; |
|
mtd._read = flash_read; |
|
mtd._write = flash_write; |
|
mtd.owner = THIS_MODULE; |
|
|
|
#ifdef LART_DEBUG |
|
printk (KERN_DEBUG |
|
"mtd.name = %s\n" |
|
"mtd.size = 0x%.8x (%uM)\n" |
|
"mtd.erasesize = 0x%.8x (%uK)\n" |
|
"mtd.numeraseregions = %d\n", |
|
mtd.name, |
|
mtd.size,mtd.size / (1024*1024), |
|
mtd.erasesize,mtd.erasesize / 1024, |
|
mtd.numeraseregions); |
|
|
|
if (mtd.numeraseregions) |
|
for (result = 0; result < mtd.numeraseregions; result++) |
|
printk (KERN_DEBUG |
|
"\n\n" |
|
"mtd.eraseregions[%d].offset = 0x%.8x\n" |
|
"mtd.eraseregions[%d].erasesize = 0x%.8x (%uK)\n" |
|
"mtd.eraseregions[%d].numblocks = %d\n", |
|
result,mtd.eraseregions[result].offset, |
|
result,mtd.eraseregions[result].erasesize,mtd.eraseregions[result].erasesize / 1024, |
|
result,mtd.eraseregions[result].numblocks); |
|
|
|
printk ("\npartitions = %d\n", ARRAY_SIZE(lart_partitions)); |
|
|
|
for (result = 0; result < ARRAY_SIZE(lart_partitions); result++) |
|
printk (KERN_DEBUG |
|
"\n\n" |
|
"lart_partitions[%d].name = %s\n" |
|
"lart_partitions[%d].offset = 0x%.8x\n" |
|
"lart_partitions[%d].size = 0x%.8x (%uK)\n", |
|
result,lart_partitions[result].name, |
|
result,lart_partitions[result].offset, |
|
result,lart_partitions[result].size,lart_partitions[result].size / 1024); |
|
#endif |
|
|
|
result = mtd_device_register(&mtd, lart_partitions, |
|
ARRAY_SIZE(lart_partitions)); |
|
|
|
return (result); |
|
} |
|
|
|
static void __exit lart_flash_exit (void) |
|
{ |
|
mtd_device_unregister(&mtd); |
|
} |
|
|
|
module_init (lart_flash_init); |
|
module_exit (lart_flash_exit); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Abraham vd Merwe <[email protected]>"); |
|
MODULE_DESCRIPTION("MTD driver for Intel 28F160F3 on LART board");
|
|
|