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484 lines
11 KiB
484 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* GS1662 device registration. |
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* |
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* Copyright (C) 2015-2016 Nexvision |
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* Author: Charles-Antoine Couret <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/spi/spi.h> |
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#include <linux/platform_device.h> |
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#include <linux/ctype.h> |
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#include <linux/err.h> |
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#include <linux/device.h> |
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#include <linux/module.h> |
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#include <linux/videodev2.h> |
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#include <media/v4l2-common.h> |
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#include <media/v4l2-ctrls.h> |
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#include <media/v4l2-device.h> |
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#include <media/v4l2-subdev.h> |
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#include <media/v4l2-dv-timings.h> |
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#include <linux/v4l2-dv-timings.h> |
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#define REG_STATUS 0x04 |
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#define REG_FORCE_FMT 0x06 |
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#define REG_LINES_PER_FRAME 0x12 |
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#define REG_WORDS_PER_LINE 0x13 |
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#define REG_WORDS_PER_ACT_LINE 0x14 |
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#define REG_ACT_LINES_PER_FRAME 0x15 |
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#define MASK_H_LOCK 0x001 |
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#define MASK_V_LOCK 0x002 |
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#define MASK_STD_LOCK 0x004 |
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#define MASK_FORCE_STD 0x020 |
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#define MASK_STD_STATUS 0x3E0 |
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#define GS_WIDTH_MIN 720 |
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#define GS_WIDTH_MAX 2048 |
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#define GS_HEIGHT_MIN 487 |
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#define GS_HEIGHT_MAX 1080 |
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#define GS_PIXELCLOCK_MIN 10519200 |
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#define GS_PIXELCLOCK_MAX 74250000 |
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struct gs { |
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struct spi_device *pdev; |
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struct v4l2_subdev sd; |
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struct v4l2_dv_timings current_timings; |
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int enabled; |
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}; |
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struct gs_reg_fmt { |
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u16 reg_value; |
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struct v4l2_dv_timings format; |
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}; |
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struct gs_reg_fmt_custom { |
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u16 reg_value; |
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__u32 width; |
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__u32 height; |
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__u64 pixelclock; |
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__u32 interlaced; |
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}; |
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static const struct spi_device_id gs_id[] = { |
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{ "gs1662", 0 }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(spi, gs_id); |
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static const struct v4l2_dv_timings fmt_cap[] = { |
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V4L2_DV_BT_SDI_720X487I60, |
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V4L2_DV_BT_CEA_720X576P50, |
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V4L2_DV_BT_CEA_1280X720P24, |
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V4L2_DV_BT_CEA_1280X720P25, |
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V4L2_DV_BT_CEA_1280X720P30, |
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V4L2_DV_BT_CEA_1280X720P50, |
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V4L2_DV_BT_CEA_1280X720P60, |
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V4L2_DV_BT_CEA_1920X1080P24, |
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V4L2_DV_BT_CEA_1920X1080P25, |
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V4L2_DV_BT_CEA_1920X1080P30, |
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V4L2_DV_BT_CEA_1920X1080I50, |
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V4L2_DV_BT_CEA_1920X1080I60, |
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}; |
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static const struct gs_reg_fmt reg_fmt[] = { |
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{ 0x00, V4L2_DV_BT_CEA_1280X720P60 }, |
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{ 0x01, V4L2_DV_BT_CEA_1280X720P60 }, |
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{ 0x02, V4L2_DV_BT_CEA_1280X720P30 }, |
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{ 0x03, V4L2_DV_BT_CEA_1280X720P30 }, |
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{ 0x04, V4L2_DV_BT_CEA_1280X720P50 }, |
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{ 0x05, V4L2_DV_BT_CEA_1280X720P50 }, |
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{ 0x06, V4L2_DV_BT_CEA_1280X720P25 }, |
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{ 0x07, V4L2_DV_BT_CEA_1280X720P25 }, |
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{ 0x08, V4L2_DV_BT_CEA_1280X720P24 }, |
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{ 0x09, V4L2_DV_BT_CEA_1280X720P24 }, |
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{ 0x0A, V4L2_DV_BT_CEA_1920X1080I60 }, |
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{ 0x0B, V4L2_DV_BT_CEA_1920X1080P30 }, |
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/* Default value: keep this field before 0xC */ |
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{ 0x14, V4L2_DV_BT_CEA_1920X1080I50 }, |
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{ 0x0C, V4L2_DV_BT_CEA_1920X1080I50 }, |
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{ 0x0D, V4L2_DV_BT_CEA_1920X1080P25 }, |
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{ 0x0E, V4L2_DV_BT_CEA_1920X1080P25 }, |
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{ 0x10, V4L2_DV_BT_CEA_1920X1080P24 }, |
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{ 0x12, V4L2_DV_BT_CEA_1920X1080P24 }, |
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{ 0x16, V4L2_DV_BT_SDI_720X487I60 }, |
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{ 0x19, V4L2_DV_BT_SDI_720X487I60 }, |
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{ 0x18, V4L2_DV_BT_CEA_720X576P50 }, |
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{ 0x1A, V4L2_DV_BT_CEA_720X576P50 }, |
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/* Implement following timings before enable it. |
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* Because of we don't have access to these theoretical timings yet. |
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* Workaround: use functions to get and set registers for these formats. |
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*/ |
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#if 0 |
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{ 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ |
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{ 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */ |
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{ 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ |
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{ 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */ |
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{ 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ |
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{ 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ |
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{ 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */ |
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#endif |
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}; |
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static const struct v4l2_dv_timings_cap gs_timings_cap = { |
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.type = V4L2_DV_BT_656_1120, |
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/* keep this initialization for compatibility with GCC < 4.4.6 */ |
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.reserved = { 0 }, |
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V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN, |
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GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN, |
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GS_PIXELCLOCK_MAX, |
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V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, |
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V4L2_DV_BT_CAP_PROGRESSIVE |
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| V4L2_DV_BT_CAP_INTERLACED) |
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}; |
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static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value) |
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{ |
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int ret; |
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u16 buf_addr = (0x8000 | (0x0FFF & addr)); |
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u16 buf_value = 0; |
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struct spi_message msg; |
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struct spi_transfer tx[] = { |
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{ |
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.tx_buf = &buf_addr, |
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.len = 2, |
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.delay = { |
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.value = 1, |
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.unit = SPI_DELAY_UNIT_USECS |
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}, |
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}, { |
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.rx_buf = &buf_value, |
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.len = 2, |
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.delay = { |
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.value = 1, |
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.unit = SPI_DELAY_UNIT_USECS |
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}, |
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}, |
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}; |
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spi_message_init(&msg); |
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spi_message_add_tail(&tx[0], &msg); |
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spi_message_add_tail(&tx[1], &msg); |
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ret = spi_sync(spi, &msg); |
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*value = buf_value; |
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return ret; |
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} |
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static int gs_write_register(struct spi_device *spi, u16 addr, u16 value) |
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{ |
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int ret; |
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u16 buf_addr = addr; |
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u16 buf_value = value; |
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struct spi_message msg; |
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struct spi_transfer tx[] = { |
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{ |
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.tx_buf = &buf_addr, |
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.len = 2, |
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.delay = { |
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.value = 1, |
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.unit = SPI_DELAY_UNIT_USECS |
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}, |
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}, { |
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.tx_buf = &buf_value, |
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.len = 2, |
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.delay = { |
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.value = 1, |
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.unit = SPI_DELAY_UNIT_USECS |
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}, |
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}, |
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}; |
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spi_message_init(&msg); |
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spi_message_add_tail(&tx[0], &msg); |
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spi_message_add_tail(&tx[1], &msg); |
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ret = spi_sync(spi, &msg); |
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return ret; |
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} |
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#ifdef CONFIG_VIDEO_ADV_DEBUG |
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static int gs_g_register(struct v4l2_subdev *sd, |
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struct v4l2_dbg_register *reg) |
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{ |
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struct spi_device *spi = v4l2_get_subdevdata(sd); |
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u16 val; |
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int ret; |
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ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); |
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reg->val = val; |
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reg->size = 2; |
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return ret; |
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} |
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static int gs_s_register(struct v4l2_subdev *sd, |
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const struct v4l2_dbg_register *reg) |
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{ |
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struct spi_device *spi = v4l2_get_subdevdata(sd); |
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return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); |
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} |
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#endif |
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static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) |
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{ |
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int std = (status & MASK_STD_STATUS) >> 5; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { |
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if (reg_fmt[i].reg_value == std) { |
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*timings = reg_fmt[i].format; |
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return 0; |
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} |
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} |
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return -ERANGE; |
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} |
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static u16 get_register_timings(struct v4l2_dv_timings *timings) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { |
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if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0, |
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false)) |
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return reg_fmt[i].reg_value | MASK_FORCE_STD; |
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} |
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return 0x0; |
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} |
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static inline struct gs *to_gs(struct v4l2_subdev *sd) |
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{ |
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return container_of(sd, struct gs, sd); |
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} |
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static int gs_s_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings *timings) |
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{ |
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struct gs *gs = to_gs(sd); |
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int reg_value; |
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reg_value = get_register_timings(timings); |
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if (reg_value == 0x0) |
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return -EINVAL; |
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gs->current_timings = *timings; |
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return 0; |
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} |
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static int gs_g_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings *timings) |
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{ |
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struct gs *gs = to_gs(sd); |
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*timings = gs->current_timings; |
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return 0; |
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} |
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static int gs_query_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings *timings) |
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{ |
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struct gs *gs = to_gs(sd); |
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struct v4l2_dv_timings fmt; |
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u16 reg_value, i; |
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int ret; |
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if (gs->enabled) |
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return -EBUSY; |
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/* |
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* Check if the component detect a line, a frame or something else |
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* which looks like a video signal activity. |
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*/ |
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for (i = 0; i < 4; i++) { |
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gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value); |
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if (reg_value) |
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break; |
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} |
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/* If no register reports a video signal */ |
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if (i >= 4) |
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return -ENOLINK; |
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gs_read_register(gs->pdev, REG_STATUS, ®_value); |
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if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK)) |
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return -ENOLCK; |
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if (!(reg_value & MASK_STD_LOCK)) |
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return -ERANGE; |
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ret = gs_status_format(reg_value, &fmt); |
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if (ret < 0) |
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return ret; |
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*timings = fmt; |
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return 0; |
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} |
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static int gs_enum_dv_timings(struct v4l2_subdev *sd, |
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struct v4l2_enum_dv_timings *timings) |
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{ |
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if (timings->index >= ARRAY_SIZE(fmt_cap)) |
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return -EINVAL; |
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if (timings->pad != 0) |
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return -EINVAL; |
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timings->timings = fmt_cap[timings->index]; |
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return 0; |
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} |
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static int gs_s_stream(struct v4l2_subdev *sd, int enable) |
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{ |
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struct gs *gs = to_gs(sd); |
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int reg_value; |
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if (gs->enabled == enable) |
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return 0; |
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gs->enabled = enable; |
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if (enable) { |
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/* To force the specific format */ |
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reg_value = get_register_timings(&gs->current_timings); |
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return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value); |
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} |
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/* To renable auto-detection mode */ |
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return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0); |
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} |
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static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status) |
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{ |
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struct gs *gs = to_gs(sd); |
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u16 reg_value, i; |
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int ret; |
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/* |
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* Check if the component detect a line, a frame or something else |
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* which looks like a video signal activity. |
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*/ |
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for (i = 0; i < 4; i++) { |
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ret = gs_read_register(gs->pdev, |
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REG_LINES_PER_FRAME + i, ®_value); |
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if (reg_value) |
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break; |
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if (ret) { |
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*status = V4L2_IN_ST_NO_POWER; |
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return ret; |
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} |
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} |
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/* If no register reports a video signal */ |
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if (i >= 4) |
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*status |= V4L2_IN_ST_NO_SIGNAL; |
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ret = gs_read_register(gs->pdev, REG_STATUS, ®_value); |
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if (!(reg_value & MASK_H_LOCK)) |
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*status |= V4L2_IN_ST_NO_H_LOCK; |
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if (!(reg_value & MASK_V_LOCK)) |
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*status |= V4L2_IN_ST_NO_V_LOCK; |
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if (!(reg_value & MASK_STD_LOCK)) |
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*status |= V4L2_IN_ST_NO_STD_LOCK; |
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return ret; |
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} |
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static int gs_dv_timings_cap(struct v4l2_subdev *sd, |
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struct v4l2_dv_timings_cap *cap) |
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{ |
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if (cap->pad != 0) |
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return -EINVAL; |
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*cap = gs_timings_cap; |
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return 0; |
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} |
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/* V4L2 core operation handlers */ |
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static const struct v4l2_subdev_core_ops gs_core_ops = { |
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#ifdef CONFIG_VIDEO_ADV_DEBUG |
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.g_register = gs_g_register, |
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.s_register = gs_s_register, |
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#endif |
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}; |
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static const struct v4l2_subdev_video_ops gs_video_ops = { |
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.s_dv_timings = gs_s_dv_timings, |
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.g_dv_timings = gs_g_dv_timings, |
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.s_stream = gs_s_stream, |
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.g_input_status = gs_g_input_status, |
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.query_dv_timings = gs_query_dv_timings, |
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}; |
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static const struct v4l2_subdev_pad_ops gs_pad_ops = { |
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.enum_dv_timings = gs_enum_dv_timings, |
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.dv_timings_cap = gs_dv_timings_cap, |
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}; |
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/* V4L2 top level operation handlers */ |
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static const struct v4l2_subdev_ops gs_ops = { |
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.core = &gs_core_ops, |
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.video = &gs_video_ops, |
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.pad = &gs_pad_ops, |
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}; |
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static int gs_probe(struct spi_device *spi) |
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{ |
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int ret; |
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struct gs *gs; |
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struct v4l2_subdev *sd; |
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gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL); |
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if (!gs) |
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return -ENOMEM; |
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gs->pdev = spi; |
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sd = &gs->sd; |
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spi->mode = SPI_MODE_0; |
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spi->irq = -1; |
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spi->max_speed_hz = 10000000; |
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spi->bits_per_word = 16; |
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ret = spi_setup(spi); |
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v4l2_spi_subdev_init(sd, spi, &gs_ops); |
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gs->current_timings = reg_fmt[0].format; |
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gs->enabled = 0; |
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/* Set H_CONFIG to SMPTE timings */ |
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gs_write_register(spi, 0x0, 0x300); |
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return ret; |
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} |
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static int gs_remove(struct spi_device *spi) |
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{ |
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struct v4l2_subdev *sd = spi_get_drvdata(spi); |
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v4l2_device_unregister_subdev(sd); |
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return 0; |
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} |
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static struct spi_driver gs_driver = { |
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.driver = { |
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.name = "gs1662", |
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}, |
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.probe = gs_probe, |
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.remove = gs_remove, |
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.id_table = gs_id, |
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}; |
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module_spi_driver(gs_driver); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Charles-Antoine Couret <[email protected]>"); |
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MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver");
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