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455 lines
12 KiB
455 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for Mediatek IR Receiver Controller |
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* |
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* Copyright (C) 2017 Sean Wang <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/reset.h> |
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#include <media/rc-core.h> |
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#define MTK_IR_DEV KBUILD_MODNAME |
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/* Register to enable PWM and IR */ |
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#define MTK_CONFIG_HIGH_REG 0x0c |
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/* Bit to enable IR pulse width detection */ |
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#define MTK_PWM_EN BIT(13) |
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/* |
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* Register to setting ok count whose unit based on hardware sampling period |
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* indicating IR receiving completion and then making IRQ fires |
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*/ |
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#define MTK_OK_COUNT(x) (((x) & GENMASK(23, 16)) << 16) |
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/* Bit to enable IR hardware function */ |
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#define MTK_IR_EN BIT(0) |
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/* Bit to restart IR receiving */ |
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#define MTK_IRCLR BIT(0) |
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/* Fields containing pulse width data */ |
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#define MTK_WIDTH_MASK (GENMASK(7, 0)) |
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/* IR threshold */ |
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#define MTK_IRTHD 0x14 |
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#define MTK_DG_CNT_MASK (GENMASK(12, 8)) |
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#define MTK_DG_CNT(x) ((x) << 8) |
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/* Bit to enable interrupt */ |
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#define MTK_IRINT_EN BIT(0) |
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/* Bit to clear interrupt status */ |
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#define MTK_IRINT_CLR BIT(0) |
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/* Maximum count of samples */ |
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#define MTK_MAX_SAMPLES 0xff |
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/* Indicate the end of IR message */ |
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#define MTK_IR_END(v, p) ((v) == MTK_MAX_SAMPLES && (p) == 0) |
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/* Number of registers to record the pulse width */ |
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#define MTK_CHKDATA_SZ 17 |
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/* Sample period in us */ |
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#define MTK_IR_SAMPLE 46 |
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enum mtk_fields { |
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/* Register to setting software sampling period */ |
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MTK_CHK_PERIOD, |
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/* Register to setting hardware sampling period */ |
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MTK_HW_PERIOD, |
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}; |
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enum mtk_regs { |
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/* Register to clear state of state machine */ |
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MTK_IRCLR_REG, |
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/* Register containing pulse width data */ |
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MTK_CHKDATA_REG, |
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/* Register to enable IR interrupt */ |
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MTK_IRINT_EN_REG, |
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/* Register to ack IR interrupt */ |
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MTK_IRINT_CLR_REG |
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}; |
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static const u32 mt7623_regs[] = { |
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[MTK_IRCLR_REG] = 0x20, |
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[MTK_CHKDATA_REG] = 0x88, |
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[MTK_IRINT_EN_REG] = 0xcc, |
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[MTK_IRINT_CLR_REG] = 0xd0, |
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}; |
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static const u32 mt7622_regs[] = { |
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[MTK_IRCLR_REG] = 0x18, |
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[MTK_CHKDATA_REG] = 0x30, |
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[MTK_IRINT_EN_REG] = 0x1c, |
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[MTK_IRINT_CLR_REG] = 0x20, |
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}; |
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struct mtk_field_type { |
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u32 reg; |
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u8 offset; |
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u32 mask; |
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}; |
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/* |
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* struct mtk_ir_data - This is the structure holding all differences among |
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various hardwares |
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* @regs: The pointer to the array holding registers offset |
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* @fields: The pointer to the array holding fields location |
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* @div: The internal divisor for the based reference clock |
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* @ok_count: The count indicating the completion of IR data |
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* receiving when count is reached |
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* @hw_period: The value indicating the hardware sampling period |
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*/ |
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struct mtk_ir_data { |
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const u32 *regs; |
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const struct mtk_field_type *fields; |
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u8 div; |
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u8 ok_count; |
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u32 hw_period; |
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}; |
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static const struct mtk_field_type mt7623_fields[] = { |
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[MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)}, |
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[MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)}, |
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}; |
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static const struct mtk_field_type mt7622_fields[] = { |
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[MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)}, |
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[MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)}, |
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}; |
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/* |
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* struct mtk_ir - This is the main datasructure for holding the state |
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* of the driver |
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* @dev: The device pointer |
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* @rc: The rc instrance |
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* @base: The mapped register i/o base |
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* @irq: The IRQ that we are using |
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* @clk: The clock that IR internal is using |
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* @bus: The clock that software decoder is using |
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* @data: Holding specific data for vaious platform |
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*/ |
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struct mtk_ir { |
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struct device *dev; |
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struct rc_dev *rc; |
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void __iomem *base; |
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int irq; |
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struct clk *clk; |
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struct clk *bus; |
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const struct mtk_ir_data *data; |
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}; |
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static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i) |
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{ |
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return ir->data->regs[MTK_CHKDATA_REG] + 4 * i; |
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} |
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static inline u32 mtk_chk_period(struct mtk_ir *ir) |
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{ |
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u32 val; |
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/* |
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* Period for software decoder used in the |
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* unit of raw software sampling |
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*/ |
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val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus), |
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USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE); |
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dev_dbg(ir->dev, "@pwm clk = \t%lu\n", |
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clk_get_rate(ir->bus) / ir->data->div); |
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dev_dbg(ir->dev, "@chkperiod = %08x\n", val); |
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return val; |
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} |
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static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg) |
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{ |
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u32 tmp; |
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tmp = __raw_readl(ir->base + reg); |
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tmp = (tmp & ~mask) | val; |
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__raw_writel(tmp, ir->base + reg); |
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} |
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static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg) |
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{ |
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__raw_writel(val, ir->base + reg); |
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} |
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static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg) |
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{ |
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return __raw_readl(ir->base + reg); |
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} |
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static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask) |
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{ |
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u32 val; |
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val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); |
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mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]); |
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} |
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static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask) |
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{ |
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u32 val; |
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val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]); |
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mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]); |
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} |
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static irqreturn_t mtk_ir_irq(int irqno, void *dev_id) |
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{ |
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struct mtk_ir *ir = dev_id; |
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u8 wid = 0; |
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u32 i, j, val; |
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struct ir_raw_event rawir = {}; |
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/* |
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* Reset decoder state machine explicitly is required |
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* because 1) the longest duration for space MTK IR hardware |
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* could record is not safely long. e.g 12ms if rx resolution |
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* is 46us by default. There is still the risk to satisfying |
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* every decoder to reset themselves through long enough |
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* trailing spaces and 2) the IRQ handler guarantees that |
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* start of IR message is always contained in and starting |
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* from register mtk_chkdata_reg(ir, i). |
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*/ |
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ir_raw_event_reset(ir->rc); |
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/* First message must be pulse */ |
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rawir.pulse = false; |
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/* Handle all pulse and space IR controller captures */ |
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for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) { |
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val = mtk_r32(ir, mtk_chkdata_reg(ir, i)); |
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dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val); |
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for (j = 0 ; j < 4 ; j++) { |
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wid = (val & (MTK_WIDTH_MASK << j * 8)) >> j * 8; |
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rawir.pulse = !rawir.pulse; |
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rawir.duration = wid * (MTK_IR_SAMPLE + 1); |
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ir_raw_event_store_with_filter(ir->rc, &rawir); |
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} |
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} |
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/* |
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* The maximum number of edges the IR controller can |
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* hold is MTK_CHKDATA_SZ * 4. So if received IR messages |
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* is over the limit, the last incomplete IR message would |
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* be appended trailing space and still would be sent into |
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* ir-rc-raw to decode. That helps it is possible that it |
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* has enough information to decode a scancode even if the |
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* trailing end of the message is missing. |
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*/ |
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if (!MTK_IR_END(wid, rawir.pulse)) { |
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rawir.pulse = false; |
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rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); |
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ir_raw_event_store_with_filter(ir->rc, &rawir); |
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} |
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ir_raw_event_handle(ir->rc); |
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/* |
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* Restart controller for the next receive that would |
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* clear up all CHKDATA registers |
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*/ |
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mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]); |
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/* Clear interrupt status */ |
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mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, |
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ir->data->regs[MTK_IRINT_CLR_REG]); |
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return IRQ_HANDLED; |
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} |
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static const struct mtk_ir_data mt7623_data = { |
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.regs = mt7623_regs, |
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.fields = mt7623_fields, |
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.ok_count = 0xf, |
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.hw_period = 0xff, |
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.div = 4, |
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}; |
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static const struct mtk_ir_data mt7622_data = { |
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.regs = mt7622_regs, |
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.fields = mt7622_fields, |
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.ok_count = 0xf, |
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.hw_period = 0xffff, |
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.div = 32, |
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}; |
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static const struct of_device_id mtk_ir_match[] = { |
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{ .compatible = "mediatek,mt7623-cir", .data = &mt7623_data}, |
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{ .compatible = "mediatek,mt7622-cir", .data = &mt7622_data}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, mtk_ir_match); |
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static int mtk_ir_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct device_node *dn = dev->of_node; |
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struct resource *res; |
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struct mtk_ir *ir; |
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u32 val; |
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int ret = 0; |
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const char *map_name; |
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ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL); |
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if (!ir) |
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return -ENOMEM; |
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ir->dev = dev; |
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ir->data = of_device_get_match_data(dev); |
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ir->clk = devm_clk_get(dev, "clk"); |
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if (IS_ERR(ir->clk)) { |
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dev_err(dev, "failed to get a ir clock.\n"); |
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return PTR_ERR(ir->clk); |
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} |
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ir->bus = devm_clk_get(dev, "bus"); |
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if (IS_ERR(ir->bus)) { |
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/* |
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* For compatibility with older device trees try unnamed |
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* ir->bus uses the same clock as ir->clock. |
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*/ |
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ir->bus = ir->clk; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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ir->base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(ir->base)) |
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return PTR_ERR(ir->base); |
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ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW); |
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if (!ir->rc) { |
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dev_err(dev, "failed to allocate device\n"); |
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return -ENOMEM; |
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} |
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ir->rc->priv = ir; |
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ir->rc->device_name = MTK_IR_DEV; |
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ir->rc->input_phys = MTK_IR_DEV "/input0"; |
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ir->rc->input_id.bustype = BUS_HOST; |
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ir->rc->input_id.vendor = 0x0001; |
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ir->rc->input_id.product = 0x0001; |
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ir->rc->input_id.version = 0x0001; |
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map_name = of_get_property(dn, "linux,rc-map-name", NULL); |
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ir->rc->map_name = map_name ?: RC_MAP_EMPTY; |
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ir->rc->dev.parent = dev; |
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ir->rc->driver_name = MTK_IR_DEV; |
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ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
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ir->rc->rx_resolution = MTK_IR_SAMPLE; |
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ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1); |
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ret = devm_rc_register_device(dev, ir->rc); |
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if (ret) { |
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dev_err(dev, "failed to register rc device\n"); |
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return ret; |
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} |
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platform_set_drvdata(pdev, ir); |
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ir->irq = platform_get_irq(pdev, 0); |
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if (ir->irq < 0) |
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return -ENODEV; |
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if (clk_prepare_enable(ir->clk)) { |
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dev_err(dev, "try to enable ir_clk failed\n"); |
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return -EINVAL; |
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} |
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if (clk_prepare_enable(ir->bus)) { |
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dev_err(dev, "try to enable ir_clk failed\n"); |
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ret = -EINVAL; |
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goto exit_clkdisable_clk; |
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} |
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/* |
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* Enable interrupt after proper hardware |
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* setup and IRQ handler registration |
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*/ |
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mtk_irq_disable(ir, MTK_IRINT_EN); |
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ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir); |
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if (ret) { |
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dev_err(dev, "failed request irq\n"); |
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goto exit_clkdisable_bus; |
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} |
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/* |
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* Setup software sample period as the reference of software decoder |
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*/ |
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val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) & |
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ir->data->fields[MTK_CHK_PERIOD].mask; |
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mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask, |
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ir->data->fields[MTK_CHK_PERIOD].reg); |
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/* |
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* Setup hardware sampling period used to setup the proper timeout for |
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* indicating end of IR receiving completion |
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*/ |
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val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) & |
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ir->data->fields[MTK_HW_PERIOD].mask; |
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mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask, |
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ir->data->fields[MTK_HW_PERIOD].reg); |
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/* Set de-glitch counter */ |
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mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD); |
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/* Enable IR and PWM */ |
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val = mtk_r32(ir, MTK_CONFIG_HIGH_REG); |
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val |= MTK_OK_COUNT(ir->data->ok_count) | MTK_PWM_EN | MTK_IR_EN; |
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mtk_w32(ir, val, MTK_CONFIG_HIGH_REG); |
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mtk_irq_enable(ir, MTK_IRINT_EN); |
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dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n", |
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MTK_IR_SAMPLE); |
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return 0; |
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exit_clkdisable_bus: |
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clk_disable_unprepare(ir->bus); |
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exit_clkdisable_clk: |
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clk_disable_unprepare(ir->clk); |
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return ret; |
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} |
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static int mtk_ir_remove(struct platform_device *pdev) |
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{ |
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struct mtk_ir *ir = platform_get_drvdata(pdev); |
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/* |
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* Avoid contention between remove handler and |
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* IRQ handler so that disabling IR interrupt and |
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* waiting for pending IRQ handler to complete |
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*/ |
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mtk_irq_disable(ir, MTK_IRINT_EN); |
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synchronize_irq(ir->irq); |
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clk_disable_unprepare(ir->bus); |
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clk_disable_unprepare(ir->clk); |
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return 0; |
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} |
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static struct platform_driver mtk_ir_driver = { |
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.probe = mtk_ir_probe, |
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.remove = mtk_ir_remove, |
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.driver = { |
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.name = MTK_IR_DEV, |
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.of_match_table = mtk_ir_match, |
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}, |
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}; |
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module_platform_driver(mtk_ir_driver); |
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MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver"); |
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MODULE_AUTHOR("Sean Wang <[email protected]>"); |
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MODULE_LICENSE("GPL");
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