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408 lines
9.7 KiB
408 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014 Linaro Ltd. |
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* Copyright (c) 2014 Hisilicon Limited. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_device.h> |
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#include <linux/regmap.h> |
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#include <media/rc-core.h> |
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#define IR_ENABLE 0x00 |
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#define IR_CONFIG 0x04 |
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#define CNT_LEADS 0x08 |
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#define CNT_LEADE 0x0c |
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#define CNT_SLEADE 0x10 |
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#define CNT0_B 0x14 |
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#define CNT1_B 0x18 |
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#define IR_BUSY 0x1c |
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#define IR_DATAH 0x20 |
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#define IR_DATAL 0x24 |
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#define IR_INTM 0x28 |
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#define IR_INTS 0x2c |
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#define IR_INTC 0x30 |
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#define IR_START 0x34 |
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/* interrupt mask */ |
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#define INTMS_SYMBRCV (BIT(24) | BIT(8)) |
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#define INTMS_TIMEOUT (BIT(25) | BIT(9)) |
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#define INTMS_OVERFLOW (BIT(26) | BIT(10)) |
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#define INT_CLR_OVERFLOW BIT(18) |
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#define INT_CLR_TIMEOUT BIT(17) |
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#define INT_CLR_RCV BIT(16) |
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#define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17)) |
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#define IR_CLK_ENABLE BIT(4) |
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#define IR_CLK_RESET BIT(5) |
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/* IR_ENABLE register bits */ |
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#define IR_ENABLE_EN BIT(0) |
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#define IR_ENABLE_EN_EXTRA BIT(8) |
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#define IR_CFG_WIDTH_MASK 0xffff |
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#define IR_CFG_WIDTH_SHIFT 16 |
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#define IR_CFG_FORMAT_MASK 0x3 |
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#define IR_CFG_FORMAT_SHIFT 14 |
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#define IR_CFG_INT_LEVEL_MASK 0x3f |
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#define IR_CFG_INT_LEVEL_SHIFT 8 |
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/* only support raw mode */ |
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#define IR_CFG_MODE_RAW BIT(7) |
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#define IR_CFG_FREQ_MASK 0x7f |
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#define IR_CFG_FREQ_SHIFT 0 |
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#define IR_CFG_INT_THRESHOLD 1 |
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/* symbol start from low to high, symbol stream end at high*/ |
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#define IR_CFG_SYMBOL_FMT 0 |
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#define IR_CFG_SYMBOL_MAXWIDTH 0x3e80 |
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#define IR_HIX5HD2_NAME "hix5hd2-ir" |
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/* Need to set extra bit for enabling IR */ |
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#define HIX5HD2_FLAG_EXTRA_ENABLE BIT(0) |
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struct hix5hd2_soc_data { |
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u32 clk_reg; |
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u32 flags; |
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}; |
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static const struct hix5hd2_soc_data hix5hd2_data = { |
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.clk_reg = 0x48, |
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}; |
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static const struct hix5hd2_soc_data hi3796cv300_data = { |
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.clk_reg = 0x60, |
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.flags = HIX5HD2_FLAG_EXTRA_ENABLE, |
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}; |
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struct hix5hd2_ir_priv { |
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int irq; |
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void __iomem *base; |
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struct device *dev; |
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struct rc_dev *rdev; |
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struct regmap *regmap; |
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struct clk *clock; |
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unsigned long rate; |
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const struct hix5hd2_soc_data *socdata; |
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}; |
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static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on) |
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{ |
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u32 clk_reg = dev->socdata->clk_reg; |
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u32 val; |
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int ret = 0; |
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if (dev->regmap) { |
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regmap_read(dev->regmap, clk_reg, &val); |
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if (on) { |
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val &= ~IR_CLK_RESET; |
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val |= IR_CLK_ENABLE; |
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} else { |
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val &= ~IR_CLK_ENABLE; |
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val |= IR_CLK_RESET; |
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} |
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regmap_write(dev->regmap, clk_reg, val); |
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} else { |
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if (on) |
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ret = clk_prepare_enable(dev->clock); |
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else |
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clk_disable_unprepare(dev->clock); |
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} |
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return ret; |
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} |
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static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv) |
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{ |
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u32 val = IR_ENABLE_EN; |
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if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE) |
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val |= IR_ENABLE_EN_EXTRA; |
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writel_relaxed(val, priv->base + IR_ENABLE); |
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} |
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static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv) |
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{ |
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int timeout = 10000; |
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u32 val, rate; |
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hix5hd2_ir_enable(priv); |
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while (readl_relaxed(priv->base + IR_BUSY)) { |
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if (timeout--) { |
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udelay(1); |
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} else { |
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dev_err(priv->dev, "IR_BUSY timeout\n"); |
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return -ETIMEDOUT; |
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} |
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} |
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/* Now only support raw mode, with symbol start from low to high */ |
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rate = DIV_ROUND_CLOSEST(priv->rate, 1000000); |
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val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT; |
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val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT; |
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val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK |
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<< IR_CFG_INT_LEVEL_SHIFT; |
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val |= IR_CFG_MODE_RAW; |
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val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT; |
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writel_relaxed(val, priv->base + IR_CONFIG); |
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writel_relaxed(0x00, priv->base + IR_INTM); |
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/* write arbitrary value to start */ |
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writel_relaxed(0x01, priv->base + IR_START); |
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return 0; |
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} |
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static int hix5hd2_ir_open(struct rc_dev *rdev) |
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{ |
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struct hix5hd2_ir_priv *priv = rdev->priv; |
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int ret; |
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ret = hix5hd2_ir_clk_enable(priv, true); |
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if (ret) |
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return ret; |
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ret = hix5hd2_ir_config(priv); |
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if (ret) { |
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hix5hd2_ir_clk_enable(priv, false); |
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return ret; |
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} |
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return 0; |
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} |
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static void hix5hd2_ir_close(struct rc_dev *rdev) |
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{ |
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struct hix5hd2_ir_priv *priv = rdev->priv; |
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hix5hd2_ir_clk_enable(priv, false); |
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} |
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static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data) |
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{ |
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u32 symb_num, symb_val, symb_time; |
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u32 data_l, data_h; |
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u32 irq_sr, i; |
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struct hix5hd2_ir_priv *priv = data; |
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irq_sr = readl_relaxed(priv->base + IR_INTS); |
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if (irq_sr & INTMS_OVERFLOW) { |
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/* |
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* we must read IR_DATAL first, then we can clean up |
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* IR_INTS availably since logic would not clear |
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* fifo when overflow, drv do the job |
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*/ |
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ir_raw_event_reset(priv->rdev); |
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symb_num = readl_relaxed(priv->base + IR_DATAH); |
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for (i = 0; i < symb_num; i++) |
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readl_relaxed(priv->base + IR_DATAL); |
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writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC); |
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dev_info(priv->dev, "overflow, level=%d\n", |
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IR_CFG_INT_THRESHOLD); |
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} |
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if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) { |
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struct ir_raw_event ev = {}; |
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symb_num = readl_relaxed(priv->base + IR_DATAH); |
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for (i = 0; i < symb_num; i++) { |
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symb_val = readl_relaxed(priv->base + IR_DATAL); |
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data_l = ((symb_val & 0xffff) * 10); |
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data_h = ((symb_val >> 16) & 0xffff) * 10; |
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symb_time = (data_l + data_h) / 10; |
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ev.duration = data_l; |
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ev.pulse = true; |
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ir_raw_event_store(priv->rdev, &ev); |
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if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) { |
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ev.duration = data_h; |
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ev.pulse = false; |
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ir_raw_event_store(priv->rdev, &ev); |
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} else { |
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ir_raw_event_set_idle(priv->rdev, true); |
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} |
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} |
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if (irq_sr & INTMS_SYMBRCV) |
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writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC); |
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if (irq_sr & INTMS_TIMEOUT) |
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writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC); |
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} |
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/* Empty software fifo */ |
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ir_raw_event_handle(priv->rdev); |
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return IRQ_HANDLED; |
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} |
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static const struct of_device_id hix5hd2_ir_table[] = { |
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{ .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, }, |
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{ .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, hix5hd2_ir_table); |
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static int hix5hd2_ir_probe(struct platform_device *pdev) |
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{ |
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struct rc_dev *rdev; |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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struct hix5hd2_ir_priv *priv; |
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struct device_node *node = pdev->dev.of_node; |
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const struct of_device_id *of_id; |
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const char *map_name; |
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int ret; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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of_id = of_match_device(hix5hd2_ir_table, dev); |
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if (!of_id) { |
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dev_err(dev, "Unable to initialize IR data\n"); |
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return -ENODEV; |
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} |
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priv->socdata = of_id->data; |
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priv->regmap = syscon_regmap_lookup_by_phandle(node, |
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"hisilicon,power-syscon"); |
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if (IS_ERR(priv->regmap)) { |
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dev_info(dev, "no power-reg\n"); |
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priv->regmap = NULL; |
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} |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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priv->base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(priv->base)) |
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return PTR_ERR(priv->base); |
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priv->irq = platform_get_irq(pdev, 0); |
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if (priv->irq < 0) |
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return priv->irq; |
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rdev = rc_allocate_device(RC_DRIVER_IR_RAW); |
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if (!rdev) |
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return -ENOMEM; |
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priv->clock = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clock)) { |
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dev_err(dev, "clock not found\n"); |
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ret = PTR_ERR(priv->clock); |
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goto err; |
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} |
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ret = clk_prepare_enable(priv->clock); |
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if (ret) |
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goto err; |
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priv->rate = clk_get_rate(priv->clock); |
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rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
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rdev->priv = priv; |
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rdev->open = hix5hd2_ir_open; |
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rdev->close = hix5hd2_ir_close; |
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rdev->driver_name = IR_HIX5HD2_NAME; |
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map_name = of_get_property(node, "linux,rc-map-name", NULL); |
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rdev->map_name = map_name ?: RC_MAP_EMPTY; |
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rdev->device_name = IR_HIX5HD2_NAME; |
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rdev->input_phys = IR_HIX5HD2_NAME "/input0"; |
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rdev->input_id.bustype = BUS_HOST; |
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rdev->input_id.vendor = 0x0001; |
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rdev->input_id.product = 0x0001; |
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rdev->input_id.version = 0x0100; |
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rdev->rx_resolution = 10; |
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rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10; |
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ret = rc_register_device(rdev); |
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if (ret < 0) |
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goto clkerr; |
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if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt, |
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0, pdev->name, priv) < 0) { |
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dev_err(dev, "IRQ %d register failed\n", priv->irq); |
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ret = -EINVAL; |
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goto regerr; |
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} |
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priv->rdev = rdev; |
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priv->dev = dev; |
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platform_set_drvdata(pdev, priv); |
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return ret; |
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regerr: |
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rc_unregister_device(rdev); |
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rdev = NULL; |
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clkerr: |
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clk_disable_unprepare(priv->clock); |
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err: |
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rc_free_device(rdev); |
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dev_err(dev, "Unable to register device (%d)\n", ret); |
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return ret; |
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} |
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static int hix5hd2_ir_remove(struct platform_device *pdev) |
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{ |
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struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev); |
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clk_disable_unprepare(priv->clock); |
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rc_unregister_device(priv->rdev); |
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return 0; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int hix5hd2_ir_suspend(struct device *dev) |
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{ |
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struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); |
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clk_disable_unprepare(priv->clock); |
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hix5hd2_ir_clk_enable(priv, false); |
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return 0; |
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} |
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static int hix5hd2_ir_resume(struct device *dev) |
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{ |
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struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev); |
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int ret; |
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ret = hix5hd2_ir_clk_enable(priv, true); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(priv->clock); |
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if (ret) { |
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hix5hd2_ir_clk_enable(priv, false); |
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return ret; |
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} |
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hix5hd2_ir_enable(priv); |
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writel_relaxed(0x00, priv->base + IR_INTM); |
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writel_relaxed(0xff, priv->base + IR_INTC); |
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writel_relaxed(0x01, priv->base + IR_START); |
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return 0; |
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} |
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#endif |
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static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend, |
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hix5hd2_ir_resume); |
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static struct platform_driver hix5hd2_ir_driver = { |
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.driver = { |
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.name = IR_HIX5HD2_NAME, |
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.of_match_table = hix5hd2_ir_table, |
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.pm = &hix5hd2_ir_pm_ops, |
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}, |
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.probe = hix5hd2_ir_probe, |
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.remove = hix5hd2_ir_remove, |
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}; |
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module_platform_driver(hix5hd2_ir_driver); |
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MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms"); |
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MODULE_AUTHOR("Guoxiong Yan <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:hix5hd2-ir");
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