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668 lines
17 KiB
668 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR |
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* |
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* Copyright (C) 2011 Jarod Wilson <[email protected]> |
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* |
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* Special thanks to Fintek for providing hardware and spec sheets. |
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* This driver is based upon the nuvoton, ite and ene drivers for |
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* similar hardware. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pnp.h> |
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#include <linux/io.h> |
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#include <linux/interrupt.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <media/rc-core.h> |
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#include "fintek-cir.h" |
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/* write val to config reg */ |
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static inline void fintek_cr_write(struct fintek_dev *fintek, u8 val, u8 reg) |
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{ |
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fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", |
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__func__, reg, val, fintek->cr_ip, fintek->cr_dp); |
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outb(reg, fintek->cr_ip); |
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outb(val, fintek->cr_dp); |
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} |
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/* read val from config reg */ |
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static inline u8 fintek_cr_read(struct fintek_dev *fintek, u8 reg) |
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{ |
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u8 val; |
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outb(reg, fintek->cr_ip); |
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val = inb(fintek->cr_dp); |
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fit_dbg("%s: reg 0x%02x, val 0x%02x (ip/dp: %02x/%02x)", |
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__func__, reg, val, fintek->cr_ip, fintek->cr_dp); |
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return val; |
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} |
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/* update config register bit without changing other bits */ |
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static inline void fintek_set_reg_bit(struct fintek_dev *fintek, u8 val, u8 reg) |
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{ |
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u8 tmp = fintek_cr_read(fintek, reg) | val; |
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fintek_cr_write(fintek, tmp, reg); |
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} |
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/* enter config mode */ |
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static inline void fintek_config_mode_enable(struct fintek_dev *fintek) |
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{ |
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/* Enabling Config Mode explicitly requires writing 2x */ |
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outb(CONFIG_REG_ENABLE, fintek->cr_ip); |
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outb(CONFIG_REG_ENABLE, fintek->cr_ip); |
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} |
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/* exit config mode */ |
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static inline void fintek_config_mode_disable(struct fintek_dev *fintek) |
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{ |
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outb(CONFIG_REG_DISABLE, fintek->cr_ip); |
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} |
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/* |
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* When you want to address a specific logical device, write its logical |
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* device number to GCR_LOGICAL_DEV_NO |
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*/ |
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static inline void fintek_select_logical_dev(struct fintek_dev *fintek, u8 ldev) |
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{ |
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fintek_cr_write(fintek, ldev, GCR_LOGICAL_DEV_NO); |
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} |
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/* write val to cir config register */ |
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static inline void fintek_cir_reg_write(struct fintek_dev *fintek, u8 val, u8 offset) |
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{ |
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outb(val, fintek->cir_addr + offset); |
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} |
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/* read val from cir config register */ |
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static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset) |
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{ |
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return inb(fintek->cir_addr + offset); |
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} |
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/* dump current cir register contents */ |
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static void cir_dump_regs(struct fintek_dev *fintek) |
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{ |
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fintek_config_mode_enable(fintek); |
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fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
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pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME); |
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pr_info(" * CR CIR BASE ADDR: 0x%x\n", |
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(fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) | |
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fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO)); |
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pr_info(" * CR CIR IRQ NUM: 0x%x\n", |
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fintek_cr_read(fintek, CIR_CR_IRQ_SEL)); |
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fintek_config_mode_disable(fintek); |
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pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME); |
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pr_info(" * STATUS: 0x%x\n", |
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fintek_cir_reg_read(fintek, CIR_STATUS)); |
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pr_info(" * CONTROL: 0x%x\n", |
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fintek_cir_reg_read(fintek, CIR_CONTROL)); |
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pr_info(" * RX_DATA: 0x%x\n", |
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fintek_cir_reg_read(fintek, CIR_RX_DATA)); |
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pr_info(" * TX_CONTROL: 0x%x\n", |
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fintek_cir_reg_read(fintek, CIR_TX_CONTROL)); |
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pr_info(" * TX_DATA: 0x%x\n", |
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fintek_cir_reg_read(fintek, CIR_TX_DATA)); |
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} |
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/* detect hardware features */ |
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static int fintek_hw_detect(struct fintek_dev *fintek) |
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{ |
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unsigned long flags; |
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u8 chip_major, chip_minor; |
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u8 vendor_major, vendor_minor; |
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u8 portsel, ir_class; |
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u16 vendor, chip; |
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fintek_config_mode_enable(fintek); |
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/* Check if we're using config port 0x4e or 0x2e */ |
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portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); |
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if (portsel == 0xff) { |
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fit_pr(KERN_INFO, "first portsel read was bunk, trying alt"); |
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fintek_config_mode_disable(fintek); |
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fintek->cr_ip = CR_INDEX_PORT2; |
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fintek->cr_dp = CR_DATA_PORT2; |
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fintek_config_mode_enable(fintek); |
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portsel = fintek_cr_read(fintek, GCR_CONFIG_PORT_SEL); |
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} |
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fit_dbg("portsel reg: 0x%02x", portsel); |
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ir_class = fintek_cir_reg_read(fintek, CIR_CR_CLASS); |
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fit_dbg("ir_class reg: 0x%02x", ir_class); |
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switch (ir_class) { |
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case CLASS_RX_2TX: |
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case CLASS_RX_1TX: |
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fintek->hw_tx_capable = true; |
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break; |
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case CLASS_RX_ONLY: |
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default: |
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fintek->hw_tx_capable = false; |
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break; |
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} |
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chip_major = fintek_cr_read(fintek, GCR_CHIP_ID_HI); |
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chip_minor = fintek_cr_read(fintek, GCR_CHIP_ID_LO); |
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chip = chip_major << 8 | chip_minor; |
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vendor_major = fintek_cr_read(fintek, GCR_VENDOR_ID_HI); |
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vendor_minor = fintek_cr_read(fintek, GCR_VENDOR_ID_LO); |
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vendor = vendor_major << 8 | vendor_minor; |
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if (vendor != VENDOR_ID_FINTEK) |
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fit_pr(KERN_WARNING, "Unknown vendor ID: 0x%04x", vendor); |
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else |
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fit_dbg("Read Fintek vendor ID from chip"); |
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fintek_config_mode_disable(fintek); |
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spin_lock_irqsave(&fintek->fintek_lock, flags); |
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fintek->chip_major = chip_major; |
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fintek->chip_minor = chip_minor; |
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fintek->chip_vendor = vendor; |
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/* |
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* Newer reviews of this chipset uses port 8 instead of 5 |
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*/ |
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if ((chip != 0x0408) && (chip != 0x0804)) |
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fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV2; |
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else |
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fintek->logical_dev_cir = LOGICAL_DEV_CIR_REV1; |
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spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
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return 0; |
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} |
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static void fintek_cir_ldev_init(struct fintek_dev *fintek) |
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{ |
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/* Select CIR logical device and enable */ |
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fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
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fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); |
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/* Write allocated CIR address and IRQ information to hardware */ |
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fintek_cr_write(fintek, fintek->cir_addr >> 8, CIR_CR_BASE_ADDR_HI); |
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fintek_cr_write(fintek, fintek->cir_addr & 0xff, CIR_CR_BASE_ADDR_LO); |
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fintek_cr_write(fintek, fintek->cir_irq, CIR_CR_IRQ_SEL); |
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fit_dbg("CIR initialized, base io address: 0x%lx, irq: %d (len: %d)", |
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fintek->cir_addr, fintek->cir_irq, fintek->cir_port_len); |
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} |
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/* enable CIR interrupts */ |
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static void fintek_enable_cir_irq(struct fintek_dev *fintek) |
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{ |
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fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); |
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} |
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static void fintek_cir_regs_init(struct fintek_dev *fintek) |
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{ |
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/* clear any and all stray interrupts */ |
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fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); |
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/* and finally, enable interrupts */ |
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fintek_enable_cir_irq(fintek); |
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} |
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static void fintek_enable_wake(struct fintek_dev *fintek) |
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{ |
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fintek_config_mode_enable(fintek); |
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fintek_select_logical_dev(fintek, LOGICAL_DEV_ACPI); |
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/* Allow CIR PME's to wake system */ |
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fintek_set_reg_bit(fintek, ACPI_WAKE_EN_CIR_BIT, LDEV_ACPI_WAKE_EN_REG); |
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/* Enable CIR PME's */ |
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fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_EN_REG); |
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/* Clear CIR PME status register */ |
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fintek_set_reg_bit(fintek, ACPI_PME_CIR_BIT, LDEV_ACPI_PME_CLR_REG); |
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/* Save state */ |
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fintek_set_reg_bit(fintek, ACPI_STATE_CIR_BIT, LDEV_ACPI_STATE_REG); |
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fintek_config_mode_disable(fintek); |
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} |
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static int fintek_cmdsize(u8 cmd, u8 subcmd) |
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{ |
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int datasize = 0; |
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switch (cmd) { |
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case BUF_COMMAND_NULL: |
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if (subcmd == BUF_HW_CMD_HEADER) |
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datasize = 1; |
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break; |
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case BUF_HW_CMD_HEADER: |
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if (subcmd == BUF_CMD_G_REVISION) |
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datasize = 2; |
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break; |
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case BUF_COMMAND_HEADER: |
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switch (subcmd) { |
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case BUF_CMD_S_CARRIER: |
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case BUF_CMD_S_TIMEOUT: |
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case BUF_RSP_PULSE_COUNT: |
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datasize = 2; |
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break; |
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case BUF_CMD_SIG_END: |
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case BUF_CMD_S_TXMASK: |
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case BUF_CMD_S_RXSENSOR: |
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datasize = 1; |
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break; |
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} |
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} |
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return datasize; |
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} |
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/* process ir data stored in driver buffer */ |
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static void fintek_process_rx_ir_data(struct fintek_dev *fintek) |
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{ |
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struct ir_raw_event rawir = {}; |
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u8 sample; |
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bool event = false; |
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int i; |
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for (i = 0; i < fintek->pkts; i++) { |
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sample = fintek->buf[i]; |
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switch (fintek->parser_state) { |
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case CMD_HEADER: |
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fintek->cmd = sample; |
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if ((fintek->cmd == BUF_COMMAND_HEADER) || |
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((fintek->cmd & BUF_COMMAND_MASK) != |
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BUF_PULSE_BIT)) { |
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fintek->parser_state = SUBCMD; |
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continue; |
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} |
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fintek->rem = (fintek->cmd & BUF_LEN_MASK); |
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fit_dbg("%s: rem: 0x%02x", __func__, fintek->rem); |
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if (fintek->rem) |
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fintek->parser_state = PARSE_IRDATA; |
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else |
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ir_raw_event_reset(fintek->rdev); |
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break; |
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case SUBCMD: |
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fintek->rem = fintek_cmdsize(fintek->cmd, sample); |
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fintek->parser_state = CMD_DATA; |
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break; |
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case CMD_DATA: |
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fintek->rem--; |
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break; |
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case PARSE_IRDATA: |
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fintek->rem--; |
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rawir.pulse = ((sample & BUF_PULSE_BIT) != 0); |
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rawir.duration = (sample & BUF_SAMPLE_MASK) |
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* CIR_SAMPLE_PERIOD; |
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fit_dbg("Storing %s with duration %d", |
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rawir.pulse ? "pulse" : "space", |
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rawir.duration); |
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if (ir_raw_event_store_with_filter(fintek->rdev, |
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&rawir)) |
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event = true; |
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break; |
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} |
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if ((fintek->parser_state != CMD_HEADER) && !fintek->rem) |
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fintek->parser_state = CMD_HEADER; |
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} |
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fintek->pkts = 0; |
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if (event) { |
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fit_dbg("Calling ir_raw_event_handle"); |
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ir_raw_event_handle(fintek->rdev); |
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} |
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} |
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/* copy data from hardware rx register into driver buffer */ |
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static void fintek_get_rx_ir_data(struct fintek_dev *fintek, u8 rx_irqs) |
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{ |
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unsigned long flags; |
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u8 sample, status; |
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spin_lock_irqsave(&fintek->fintek_lock, flags); |
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/* |
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* We must read data from CIR_RX_DATA until the hardware IR buffer |
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* is empty and clears the RX_TIMEOUT and/or RX_RECEIVE flags in |
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* the CIR_STATUS register |
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*/ |
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do { |
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sample = fintek_cir_reg_read(fintek, CIR_RX_DATA); |
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fit_dbg("%s: sample: 0x%02x", __func__, sample); |
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fintek->buf[fintek->pkts] = sample; |
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fintek->pkts++; |
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status = fintek_cir_reg_read(fintek, CIR_STATUS); |
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if (!(status & CIR_STATUS_IRQ_EN)) |
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break; |
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} while (status & rx_irqs); |
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fintek_process_rx_ir_data(fintek); |
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spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
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} |
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static void fintek_cir_log_irqs(u8 status) |
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{ |
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fit_pr(KERN_INFO, "IRQ 0x%02x:%s%s%s%s%s", status, |
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status & CIR_STATUS_IRQ_EN ? " IRQEN" : "", |
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status & CIR_STATUS_TX_FINISH ? " TXF" : "", |
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status & CIR_STATUS_TX_UNDERRUN ? " TXU" : "", |
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status & CIR_STATUS_RX_TIMEOUT ? " RXTO" : "", |
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status & CIR_STATUS_RX_RECEIVE ? " RXOK" : ""); |
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} |
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/* interrupt service routine for incoming and outgoing CIR data */ |
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static irqreturn_t fintek_cir_isr(int irq, void *data) |
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{ |
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struct fintek_dev *fintek = data; |
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u8 status, rx_irqs; |
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fit_dbg_verbose("%s firing", __func__); |
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fintek_config_mode_enable(fintek); |
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fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
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fintek_config_mode_disable(fintek); |
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/* |
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* Get IR Status register contents. Write 1 to ack/clear |
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* |
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* bit: reg name - description |
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* 3: TX_FINISH - TX is finished |
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* 2: TX_UNDERRUN - TX underrun |
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* 1: RX_TIMEOUT - RX data timeout |
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* 0: RX_RECEIVE - RX data received |
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*/ |
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status = fintek_cir_reg_read(fintek, CIR_STATUS); |
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if (!(status & CIR_STATUS_IRQ_MASK) || status == 0xff) { |
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fit_dbg_verbose("%s exiting, IRSTS 0x%02x", __func__, status); |
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fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); |
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return IRQ_RETVAL(IRQ_NONE); |
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} |
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if (debug) |
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fintek_cir_log_irqs(status); |
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rx_irqs = status & (CIR_STATUS_RX_RECEIVE | CIR_STATUS_RX_TIMEOUT); |
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if (rx_irqs) |
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fintek_get_rx_ir_data(fintek, rx_irqs); |
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/* ack/clear all irq flags we've got */ |
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fintek_cir_reg_write(fintek, status, CIR_STATUS); |
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fit_dbg_verbose("%s done", __func__); |
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return IRQ_RETVAL(IRQ_HANDLED); |
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} |
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static void fintek_enable_cir(struct fintek_dev *fintek) |
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{ |
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/* set IRQ enabled */ |
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fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_EN, CIR_STATUS); |
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fintek_config_mode_enable(fintek); |
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/* enable the CIR logical device */ |
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fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
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fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); |
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fintek_config_mode_disable(fintek); |
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/* clear all pending interrupts */ |
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fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); |
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/* enable interrupts */ |
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fintek_enable_cir_irq(fintek); |
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} |
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static void fintek_disable_cir(struct fintek_dev *fintek) |
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{ |
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fintek_config_mode_enable(fintek); |
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/* disable the CIR logical device */ |
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fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
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fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); |
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fintek_config_mode_disable(fintek); |
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} |
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static int fintek_open(struct rc_dev *dev) |
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{ |
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struct fintek_dev *fintek = dev->priv; |
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unsigned long flags; |
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spin_lock_irqsave(&fintek->fintek_lock, flags); |
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fintek_enable_cir(fintek); |
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spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
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return 0; |
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} |
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static void fintek_close(struct rc_dev *dev) |
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{ |
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struct fintek_dev *fintek = dev->priv; |
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unsigned long flags; |
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spin_lock_irqsave(&fintek->fintek_lock, flags); |
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fintek_disable_cir(fintek); |
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spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
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} |
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/* Allocate memory, probe hardware, and initialize everything */ |
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static int fintek_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id) |
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{ |
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struct fintek_dev *fintek; |
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struct rc_dev *rdev; |
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int ret = -ENOMEM; |
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fintek = kzalloc(sizeof(struct fintek_dev), GFP_KERNEL); |
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if (!fintek) |
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return ret; |
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/* input device for IR remote (and tx) */ |
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rdev = rc_allocate_device(RC_DRIVER_IR_RAW); |
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if (!rdev) |
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goto exit_free_dev_rdev; |
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ret = -ENODEV; |
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/* validate pnp resources */ |
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if (!pnp_port_valid(pdev, 0)) { |
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dev_err(&pdev->dev, "IR PNP Port not valid!\n"); |
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goto exit_free_dev_rdev; |
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} |
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if (!pnp_irq_valid(pdev, 0)) { |
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dev_err(&pdev->dev, "IR PNP IRQ not valid!\n"); |
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goto exit_free_dev_rdev; |
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} |
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fintek->cir_addr = pnp_port_start(pdev, 0); |
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fintek->cir_irq = pnp_irq(pdev, 0); |
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fintek->cir_port_len = pnp_port_len(pdev, 0); |
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fintek->cr_ip = CR_INDEX_PORT; |
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fintek->cr_dp = CR_DATA_PORT; |
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spin_lock_init(&fintek->fintek_lock); |
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pnp_set_drvdata(pdev, fintek); |
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fintek->pdev = pdev; |
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ret = fintek_hw_detect(fintek); |
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if (ret) |
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goto exit_free_dev_rdev; |
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/* Initialize CIR & CIR Wake Logical Devices */ |
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fintek_config_mode_enable(fintek); |
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fintek_cir_ldev_init(fintek); |
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fintek_config_mode_disable(fintek); |
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|
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/* Initialize CIR & CIR Wake Config Registers */ |
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fintek_cir_regs_init(fintek); |
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|
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/* Set up the rc device */ |
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rdev->priv = fintek; |
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rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; |
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rdev->open = fintek_open; |
|
rdev->close = fintek_close; |
|
rdev->device_name = FINTEK_DESCRIPTION; |
|
rdev->input_phys = "fintek/cir0"; |
|
rdev->input_id.bustype = BUS_HOST; |
|
rdev->input_id.vendor = VENDOR_ID_FINTEK; |
|
rdev->input_id.product = fintek->chip_major; |
|
rdev->input_id.version = fintek->chip_minor; |
|
rdev->dev.parent = &pdev->dev; |
|
rdev->driver_name = FINTEK_DRIVER_NAME; |
|
rdev->map_name = RC_MAP_RC6_MCE; |
|
rdev->timeout = 1000; |
|
/* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ |
|
rdev->rx_resolution = CIR_SAMPLE_PERIOD; |
|
|
|
fintek->rdev = rdev; |
|
|
|
ret = -EBUSY; |
|
/* now claim resources */ |
|
if (!request_region(fintek->cir_addr, |
|
fintek->cir_port_len, FINTEK_DRIVER_NAME)) |
|
goto exit_free_dev_rdev; |
|
|
|
if (request_irq(fintek->cir_irq, fintek_cir_isr, IRQF_SHARED, |
|
FINTEK_DRIVER_NAME, (void *)fintek)) |
|
goto exit_free_cir_addr; |
|
|
|
ret = rc_register_device(rdev); |
|
if (ret) |
|
goto exit_free_irq; |
|
|
|
device_init_wakeup(&pdev->dev, true); |
|
|
|
fit_pr(KERN_NOTICE, "driver has been successfully loaded\n"); |
|
if (debug) |
|
cir_dump_regs(fintek); |
|
|
|
return 0; |
|
|
|
exit_free_irq: |
|
free_irq(fintek->cir_irq, fintek); |
|
exit_free_cir_addr: |
|
release_region(fintek->cir_addr, fintek->cir_port_len); |
|
exit_free_dev_rdev: |
|
rc_free_device(rdev); |
|
kfree(fintek); |
|
|
|
return ret; |
|
} |
|
|
|
static void fintek_remove(struct pnp_dev *pdev) |
|
{ |
|
struct fintek_dev *fintek = pnp_get_drvdata(pdev); |
|
unsigned long flags; |
|
|
|
spin_lock_irqsave(&fintek->fintek_lock, flags); |
|
/* disable CIR */ |
|
fintek_disable_cir(fintek); |
|
fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); |
|
/* enable CIR Wake (for IR power-on) */ |
|
fintek_enable_wake(fintek); |
|
spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
|
|
|
/* free resources */ |
|
free_irq(fintek->cir_irq, fintek); |
|
release_region(fintek->cir_addr, fintek->cir_port_len); |
|
|
|
rc_unregister_device(fintek->rdev); |
|
|
|
kfree(fintek); |
|
} |
|
|
|
static int fintek_suspend(struct pnp_dev *pdev, pm_message_t state) |
|
{ |
|
struct fintek_dev *fintek = pnp_get_drvdata(pdev); |
|
unsigned long flags; |
|
|
|
fit_dbg("%s called", __func__); |
|
|
|
spin_lock_irqsave(&fintek->fintek_lock, flags); |
|
|
|
/* disable all CIR interrupts */ |
|
fintek_cir_reg_write(fintek, CIR_STATUS_IRQ_MASK, CIR_STATUS); |
|
|
|
spin_unlock_irqrestore(&fintek->fintek_lock, flags); |
|
|
|
fintek_config_mode_enable(fintek); |
|
|
|
/* disable cir logical dev */ |
|
fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
|
fintek_cr_write(fintek, LOGICAL_DEV_DISABLE, CIR_CR_DEV_EN); |
|
|
|
fintek_config_mode_disable(fintek); |
|
|
|
/* make sure wake is enabled */ |
|
fintek_enable_wake(fintek); |
|
|
|
return 0; |
|
} |
|
|
|
static int fintek_resume(struct pnp_dev *pdev) |
|
{ |
|
struct fintek_dev *fintek = pnp_get_drvdata(pdev); |
|
|
|
fit_dbg("%s called", __func__); |
|
|
|
/* open interrupt */ |
|
fintek_enable_cir_irq(fintek); |
|
|
|
/* Enable CIR logical device */ |
|
fintek_config_mode_enable(fintek); |
|
fintek_select_logical_dev(fintek, fintek->logical_dev_cir); |
|
fintek_cr_write(fintek, LOGICAL_DEV_ENABLE, CIR_CR_DEV_EN); |
|
|
|
fintek_config_mode_disable(fintek); |
|
|
|
fintek_cir_regs_init(fintek); |
|
|
|
return 0; |
|
} |
|
|
|
static void fintek_shutdown(struct pnp_dev *pdev) |
|
{ |
|
struct fintek_dev *fintek = pnp_get_drvdata(pdev); |
|
fintek_enable_wake(fintek); |
|
} |
|
|
|
static const struct pnp_device_id fintek_ids[] = { |
|
{ "FIT0002", 0 }, /* CIR */ |
|
{ "", 0 }, |
|
}; |
|
|
|
static struct pnp_driver fintek_driver = { |
|
.name = FINTEK_DRIVER_NAME, |
|
.id_table = fintek_ids, |
|
.flags = PNP_DRIVER_RES_DO_NOT_CHANGE, |
|
.probe = fintek_probe, |
|
.remove = fintek_remove, |
|
.suspend = fintek_suspend, |
|
.resume = fintek_resume, |
|
.shutdown = fintek_shutdown, |
|
}; |
|
|
|
module_param(debug, int, S_IRUGO | S_IWUSR); |
|
MODULE_PARM_DESC(debug, "Enable debugging output"); |
|
|
|
MODULE_DEVICE_TABLE(pnp, fintek_ids); |
|
MODULE_DESCRIPTION(FINTEK_DESCRIPTION " driver"); |
|
|
|
MODULE_AUTHOR("Jarod Wilson <[email protected]>"); |
|
MODULE_LICENSE("GPL"); |
|
|
|
module_pnp_driver(fintek_driver);
|
|
|