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293 lines
7.0 KiB
293 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/mailbox_controller.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/mailbox/qcom-ipcc.h> |
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#define IPCC_MBOX_MAX_CHAN 48 |
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/* IPCC Register offsets */ |
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#define IPCC_REG_SEND_ID 0x0c |
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#define IPCC_REG_RECV_ID 0x10 |
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#define IPCC_REG_RECV_SIGNAL_ENABLE 0x14 |
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#define IPCC_REG_RECV_SIGNAL_DISABLE 0x18 |
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#define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c |
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#define IPCC_REG_CLIENT_CLEAR 0x38 |
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#define IPCC_SIGNAL_ID_MASK GENMASK(15, 0) |
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#define IPCC_CLIENT_ID_MASK GENMASK(31, 16) |
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#define IPCC_NO_PENDING_IRQ GENMASK(31, 0) |
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/** |
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* struct qcom_ipcc_chan_info - Per-mailbox-channel info |
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* @client_id: The client-id to which the interrupt has to be triggered |
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* @signal_id: The signal-id to which the interrupt has to be triggered |
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*/ |
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struct qcom_ipcc_chan_info { |
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u16 client_id; |
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u16 signal_id; |
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}; |
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/** |
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* struct qcom_ipcc - Holder for the mailbox driver |
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* @dev: Device associated with this instance |
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* @base: Base address of the IPCC frame associated to APSS |
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* @irq_domain: The irq_domain associated with this instance |
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* @chan: The mailbox channels array |
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* @mchan: The per-mailbox channel info array |
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* @mbox: The mailbox controller |
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* @irq: Summary irq |
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*/ |
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struct qcom_ipcc { |
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struct device *dev; |
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void __iomem *base; |
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struct irq_domain *irq_domain; |
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struct mbox_chan chan[IPCC_MBOX_MAX_CHAN]; |
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struct qcom_ipcc_chan_info mchan[IPCC_MBOX_MAX_CHAN]; |
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struct mbox_controller mbox; |
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int irq; |
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}; |
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static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox) |
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{ |
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return container_of(mbox, struct qcom_ipcc, mbox); |
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} |
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static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id) |
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{ |
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return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) | |
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FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id); |
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} |
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static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data) |
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{ |
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struct qcom_ipcc *ipcc = data; |
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u32 hwirq; |
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int virq; |
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for (;;) { |
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hwirq = readl(ipcc->base + IPCC_REG_RECV_ID); |
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if (hwirq == IPCC_NO_PENDING_IRQ) |
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break; |
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virq = irq_find_mapping(ipcc->irq_domain, hwirq); |
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writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR); |
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generic_handle_irq(virq); |
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} |
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return IRQ_HANDLED; |
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} |
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static void qcom_ipcc_mask_irq(struct irq_data *irqd) |
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{ |
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struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); |
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irq_hw_number_t hwirq = irqd_to_hwirq(irqd); |
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writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE); |
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} |
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static void qcom_ipcc_unmask_irq(struct irq_data *irqd) |
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{ |
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struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd); |
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irq_hw_number_t hwirq = irqd_to_hwirq(irqd); |
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writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE); |
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} |
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static struct irq_chip qcom_ipcc_irq_chip = { |
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.name = "ipcc", |
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.irq_mask = qcom_ipcc_mask_irq, |
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.irq_unmask = qcom_ipcc_unmask_irq, |
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.flags = IRQCHIP_SKIP_SET_WAKE, |
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}; |
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static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hw) |
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{ |
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struct qcom_ipcc *ipcc = d->host_data; |
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irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq); |
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irq_set_chip_data(irq, ipcc); |
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irq_set_noprobe(irq); |
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return 0; |
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} |
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static int qcom_ipcc_domain_xlate(struct irq_domain *d, |
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struct device_node *node, const u32 *intspec, |
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unsigned int intsize, |
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unsigned long *out_hwirq, |
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unsigned int *out_type) |
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{ |
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if (intsize != 3) |
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return -EINVAL; |
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*out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]); |
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*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; |
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return 0; |
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} |
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static const struct irq_domain_ops qcom_ipcc_irq_ops = { |
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.map = qcom_ipcc_domain_map, |
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.xlate = qcom_ipcc_domain_xlate, |
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}; |
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static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data) |
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{ |
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struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox); |
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struct qcom_ipcc_chan_info *mchan = chan->con_priv; |
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u32 hwirq; |
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hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id); |
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writel(hwirq, ipcc->base + IPCC_REG_SEND_ID); |
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return 0; |
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} |
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static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan) |
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{ |
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chan->con_priv = NULL; |
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} |
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static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox, |
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const struct of_phandle_args *ph) |
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{ |
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struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox); |
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struct qcom_ipcc_chan_info *mchan; |
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struct mbox_chan *chan; |
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unsigned int i; |
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if (ph->args_count != 2) |
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return ERR_PTR(-EINVAL); |
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for (i = 0; i < IPCC_MBOX_MAX_CHAN; i++) { |
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chan = &ipcc->chan[i]; |
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if (!chan->con_priv) { |
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mchan = &ipcc->mchan[i]; |
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mchan->client_id = ph->args[0]; |
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mchan->signal_id = ph->args[1]; |
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chan->con_priv = mchan; |
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break; |
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} |
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chan = NULL; |
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} |
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return chan ?: ERR_PTR(-EBUSY); |
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} |
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static const struct mbox_chan_ops ipcc_mbox_chan_ops = { |
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.send_data = qcom_ipcc_mbox_send_data, |
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.shutdown = qcom_ipcc_mbox_shutdown, |
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}; |
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static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc) |
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{ |
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struct mbox_controller *mbox; |
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struct device *dev = ipcc->dev; |
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mbox = &ipcc->mbox; |
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mbox->dev = dev; |
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mbox->num_chans = IPCC_MBOX_MAX_CHAN; |
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mbox->chans = ipcc->chan; |
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mbox->ops = &ipcc_mbox_chan_ops; |
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mbox->of_xlate = qcom_ipcc_mbox_xlate; |
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mbox->txdone_irq = false; |
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mbox->txdone_poll = false; |
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return devm_mbox_controller_register(dev, mbox); |
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} |
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static int qcom_ipcc_probe(struct platform_device *pdev) |
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{ |
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struct qcom_ipcc *ipcc; |
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int ret; |
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ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL); |
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if (!ipcc) |
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return -ENOMEM; |
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ipcc->dev = &pdev->dev; |
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ipcc->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(ipcc->base)) |
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return PTR_ERR(ipcc->base); |
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ipcc->irq = platform_get_irq(pdev, 0); |
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if (ipcc->irq < 0) |
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return ipcc->irq; |
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ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node, |
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&qcom_ipcc_irq_ops, ipcc); |
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if (!ipcc->irq_domain) |
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return -ENOMEM; |
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ret = qcom_ipcc_setup_mbox(ipcc); |
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if (ret) |
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goto err_mbox; |
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ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn, |
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IRQF_TRIGGER_HIGH, "ipcc", ipcc); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret); |
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goto err_mbox; |
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} |
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enable_irq_wake(ipcc->irq); |
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platform_set_drvdata(pdev, ipcc); |
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return 0; |
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err_mbox: |
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irq_domain_remove(ipcc->irq_domain); |
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return ret; |
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} |
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static int qcom_ipcc_remove(struct platform_device *pdev) |
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{ |
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struct qcom_ipcc *ipcc = platform_get_drvdata(pdev); |
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disable_irq_wake(ipcc->irq); |
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irq_domain_remove(ipcc->irq_domain); |
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return 0; |
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} |
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static const struct of_device_id qcom_ipcc_of_match[] = { |
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{ .compatible = "qcom,ipcc"}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match); |
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static struct platform_driver qcom_ipcc_driver = { |
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.probe = qcom_ipcc_probe, |
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.remove = qcom_ipcc_remove, |
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.driver = { |
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.name = "qcom-ipcc", |
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.of_match_table = qcom_ipcc_of_match, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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static int __init qcom_ipcc_init(void) |
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{ |
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return platform_driver_register(&qcom_ipcc_driver); |
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} |
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arch_initcall(qcom_ipcc_init); |
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MODULE_AUTHOR("Venkata Narendra Kumar Gutta <[email protected]>"); |
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MODULE_AUTHOR("Manivannan Sadhasivam <[email protected]>"); |
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MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver"); |
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MODULE_LICENSE("GPL v2");
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