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551 lines
15 KiB
551 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/mach-mmp/irq.c |
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* |
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* Generic IRQ handling, GPIO IRQ demultiplexing, etc. |
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* Copyright (C) 2008 - 2012 Marvell Technology Group Ltd. |
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* |
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* Author: Bin Yang <[email protected]> |
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* Haojian Zhuang <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/io.h> |
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#include <linux/ioport.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <asm/exception.h> |
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#include <asm/hardirq.h> |
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#define MAX_ICU_NR 16 |
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#define PJ1_INT_SEL 0x10c |
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#define PJ4_INT_SEL 0x104 |
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/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ |
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#define SEL_INT_PENDING (1 << 6) |
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#define SEL_INT_NUM_MASK 0x3f |
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#define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5) |
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#define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6) |
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struct icu_chip_data { |
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int nr_irqs; |
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unsigned int virq_base; |
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unsigned int cascade_irq; |
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void __iomem *reg_status; |
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void __iomem *reg_mask; |
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unsigned int conf_enable; |
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unsigned int conf_disable; |
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unsigned int conf_mask; |
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unsigned int conf2_mask; |
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unsigned int clr_mfp_irq_base; |
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unsigned int clr_mfp_hwirq; |
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struct irq_domain *domain; |
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}; |
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struct mmp_intc_conf { |
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unsigned int conf_enable; |
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unsigned int conf_disable; |
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unsigned int conf_mask; |
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unsigned int conf2_mask; |
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}; |
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static void __iomem *mmp_icu_base; |
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static void __iomem *mmp_icu2_base; |
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static struct icu_chip_data icu_data[MAX_ICU_NR]; |
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static int max_icu_nr; |
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extern void mmp2_clear_pmic_int(void); |
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static void icu_mask_ack_irq(struct irq_data *d) |
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{ |
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struct irq_domain *domain = d->domain; |
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struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
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int hwirq; |
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u32 r; |
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hwirq = d->irq - data->virq_base; |
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if (data == &icu_data[0]) { |
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r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
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r &= ~data->conf_mask; |
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r |= data->conf_disable; |
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writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
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} else { |
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#ifdef CONFIG_CPU_MMP2 |
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if ((data->virq_base == data->clr_mfp_irq_base) |
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&& (hwirq == data->clr_mfp_hwirq)) |
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mmp2_clear_pmic_int(); |
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#endif |
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r = readl_relaxed(data->reg_mask) | (1 << hwirq); |
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writel_relaxed(r, data->reg_mask); |
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} |
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} |
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static void icu_mask_irq(struct irq_data *d) |
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{ |
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struct irq_domain *domain = d->domain; |
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struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
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int hwirq; |
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u32 r; |
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hwirq = d->irq - data->virq_base; |
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if (data == &icu_data[0]) { |
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r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
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r &= ~data->conf_mask; |
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r |= data->conf_disable; |
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writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
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if (data->conf2_mask) { |
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/* |
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* ICU1 (above) only controls PJ4 MP1; if using SMP, |
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* we need to also mask the MP2 and MM cores via ICU2. |
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*/ |
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r = readl_relaxed(mmp_icu2_base + (hwirq << 2)); |
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r &= ~data->conf2_mask; |
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writel_relaxed(r, mmp_icu2_base + (hwirq << 2)); |
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} |
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} else { |
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r = readl_relaxed(data->reg_mask) | (1 << hwirq); |
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writel_relaxed(r, data->reg_mask); |
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} |
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} |
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static void icu_unmask_irq(struct irq_data *d) |
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{ |
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struct irq_domain *domain = d->domain; |
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struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; |
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int hwirq; |
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u32 r; |
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hwirq = d->irq - data->virq_base; |
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if (data == &icu_data[0]) { |
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r = readl_relaxed(mmp_icu_base + (hwirq << 2)); |
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r &= ~data->conf_mask; |
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r |= data->conf_enable; |
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writel_relaxed(r, mmp_icu_base + (hwirq << 2)); |
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} else { |
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r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); |
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writel_relaxed(r, data->reg_mask); |
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} |
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} |
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struct irq_chip icu_irq_chip = { |
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.name = "icu_irq", |
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.irq_mask = icu_mask_irq, |
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.irq_mask_ack = icu_mask_ack_irq, |
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.irq_unmask = icu_unmask_irq, |
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}; |
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static void icu_mux_irq_demux(struct irq_desc *desc) |
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{ |
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unsigned int irq = irq_desc_get_irq(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct irq_domain *domain; |
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struct icu_chip_data *data; |
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int i; |
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unsigned long mask, status, n; |
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chained_irq_enter(chip, desc); |
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for (i = 1; i < max_icu_nr; i++) { |
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if (irq == icu_data[i].cascade_irq) { |
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domain = icu_data[i].domain; |
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data = (struct icu_chip_data *)domain->host_data; |
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break; |
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} |
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} |
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if (i >= max_icu_nr) { |
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pr_err("Spurious irq %d in MMP INTC\n", irq); |
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goto out; |
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} |
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mask = readl_relaxed(data->reg_mask); |
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while (1) { |
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status = readl_relaxed(data->reg_status) & ~mask; |
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if (status == 0) |
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break; |
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for_each_set_bit(n, &status, BITS_PER_LONG) { |
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generic_handle_irq(icu_data[i].virq_base + n); |
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} |
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} |
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out: |
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chained_irq_exit(chip, desc); |
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} |
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static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hw) |
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{ |
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irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); |
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return 0; |
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} |
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static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node, |
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const u32 *intspec, unsigned int intsize, |
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unsigned long *out_hwirq, |
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unsigned int *out_type) |
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{ |
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*out_hwirq = intspec[0]; |
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return 0; |
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} |
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static const struct irq_domain_ops mmp_irq_domain_ops = { |
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.map = mmp_irq_domain_map, |
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.xlate = mmp_irq_domain_xlate, |
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}; |
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static const struct mmp_intc_conf mmp_conf = { |
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.conf_enable = 0x51, |
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.conf_disable = 0x0, |
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.conf_mask = 0x7f, |
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}; |
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static const struct mmp_intc_conf mmp2_conf = { |
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.conf_enable = 0x20, |
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.conf_disable = 0x0, |
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.conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ | |
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MMP2_ICU_INT_ROUTE_PJ4_FIQ, |
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}; |
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static struct mmp_intc_conf mmp3_conf = { |
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.conf_enable = 0x20, |
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.conf_disable = 0x0, |
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.conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ | |
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MMP2_ICU_INT_ROUTE_PJ4_FIQ, |
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.conf2_mask = 0xf0, |
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}; |
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static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs) |
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{ |
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int hwirq; |
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hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); |
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if (!(hwirq & SEL_INT_PENDING)) |
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return; |
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hwirq &= SEL_INT_NUM_MASK; |
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handle_domain_irq(icu_data[0].domain, hwirq, regs); |
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} |
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static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs) |
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{ |
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int hwirq; |
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hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); |
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if (!(hwirq & SEL_INT_PENDING)) |
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return; |
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hwirq &= SEL_INT_NUM_MASK; |
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handle_domain_irq(icu_data[0].domain, hwirq, regs); |
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} |
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/* MMP (ARMv5) */ |
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void __init icu_init_irq(void) |
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{ |
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int irq; |
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max_icu_nr = 1; |
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mmp_icu_base = ioremap(0xd4282000, 0x1000); |
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icu_data[0].conf_enable = mmp_conf.conf_enable; |
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icu_data[0].conf_disable = mmp_conf.conf_disable; |
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icu_data[0].conf_mask = mmp_conf.conf_mask; |
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icu_data[0].nr_irqs = 64; |
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icu_data[0].virq_base = 0; |
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icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, |
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&irq_domain_simple_ops, |
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&icu_data[0]); |
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for (irq = 0; irq < 64; irq++) { |
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icu_mask_irq(irq_get_irq_data(irq)); |
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irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); |
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} |
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irq_set_default_host(icu_data[0].domain); |
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set_handle_irq(mmp_handle_irq); |
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} |
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/* MMP2 (ARMv7) */ |
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void __init mmp2_init_icu(void) |
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{ |
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int irq, end; |
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max_icu_nr = 8; |
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mmp_icu_base = ioremap(0xd4282000, 0x1000); |
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icu_data[0].conf_enable = mmp2_conf.conf_enable; |
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icu_data[0].conf_disable = mmp2_conf.conf_disable; |
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icu_data[0].conf_mask = mmp2_conf.conf_mask; |
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icu_data[0].nr_irqs = 64; |
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icu_data[0].virq_base = 0; |
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icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, |
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&irq_domain_simple_ops, |
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&icu_data[0]); |
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icu_data[1].reg_status = mmp_icu_base + 0x150; |
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icu_data[1].reg_mask = mmp_icu_base + 0x168; |
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icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base + |
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icu_data[0].nr_irqs; |
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icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */ |
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icu_data[1].nr_irqs = 2; |
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icu_data[1].cascade_irq = 4; |
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icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs; |
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icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, |
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icu_data[1].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[1]); |
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icu_data[2].reg_status = mmp_icu_base + 0x154; |
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icu_data[2].reg_mask = mmp_icu_base + 0x16c; |
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icu_data[2].nr_irqs = 2; |
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icu_data[2].cascade_irq = 5; |
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icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs; |
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icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, |
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icu_data[2].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[2]); |
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icu_data[3].reg_status = mmp_icu_base + 0x180; |
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icu_data[3].reg_mask = mmp_icu_base + 0x17c; |
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icu_data[3].nr_irqs = 3; |
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icu_data[3].cascade_irq = 9; |
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icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs; |
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icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, |
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icu_data[3].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[3]); |
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icu_data[4].reg_status = mmp_icu_base + 0x158; |
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icu_data[4].reg_mask = mmp_icu_base + 0x170; |
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icu_data[4].nr_irqs = 5; |
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icu_data[4].cascade_irq = 17; |
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icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs; |
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icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, |
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icu_data[4].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[4]); |
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icu_data[5].reg_status = mmp_icu_base + 0x15c; |
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icu_data[5].reg_mask = mmp_icu_base + 0x174; |
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icu_data[5].nr_irqs = 15; |
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icu_data[5].cascade_irq = 35; |
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icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs; |
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icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, |
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icu_data[5].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[5]); |
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icu_data[6].reg_status = mmp_icu_base + 0x160; |
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icu_data[6].reg_mask = mmp_icu_base + 0x178; |
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icu_data[6].nr_irqs = 2; |
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icu_data[6].cascade_irq = 51; |
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icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs; |
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icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, |
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icu_data[6].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[6]); |
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icu_data[7].reg_status = mmp_icu_base + 0x188; |
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icu_data[7].reg_mask = mmp_icu_base + 0x184; |
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icu_data[7].nr_irqs = 2; |
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icu_data[7].cascade_irq = 55; |
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icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs; |
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icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, |
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icu_data[7].virq_base, 0, |
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&irq_domain_simple_ops, |
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&icu_data[7]); |
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end = icu_data[7].virq_base + icu_data[7].nr_irqs; |
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for (irq = 0; irq < end; irq++) { |
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icu_mask_irq(irq_get_irq_data(irq)); |
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if (irq == icu_data[1].cascade_irq || |
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irq == icu_data[2].cascade_irq || |
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irq == icu_data[3].cascade_irq || |
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irq == icu_data[4].cascade_irq || |
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irq == icu_data[5].cascade_irq || |
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irq == icu_data[6].cascade_irq || |
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irq == icu_data[7].cascade_irq) { |
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irq_set_chip(irq, &icu_irq_chip); |
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irq_set_chained_handler(irq, icu_mux_irq_demux); |
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} else { |
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irq_set_chip_and_handler(irq, &icu_irq_chip, |
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handle_level_irq); |
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} |
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} |
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irq_set_default_host(icu_data[0].domain); |
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set_handle_irq(mmp2_handle_irq); |
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} |
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#ifdef CONFIG_OF |
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static int __init mmp_init_bases(struct device_node *node) |
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{ |
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int ret, nr_irqs, irq, i = 0; |
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ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); |
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if (ret) { |
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pr_err("Not found mrvl,intc-nr-irqs property\n"); |
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return ret; |
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} |
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mmp_icu_base = of_iomap(node, 0); |
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if (!mmp_icu_base) { |
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pr_err("Failed to get interrupt controller register\n"); |
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return -ENOMEM; |
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} |
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icu_data[0].virq_base = 0; |
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icu_data[0].domain = irq_domain_add_linear(node, nr_irqs, |
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&mmp_irq_domain_ops, |
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&icu_data[0]); |
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for (irq = 0; irq < nr_irqs; irq++) { |
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ret = irq_create_mapping(icu_data[0].domain, irq); |
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if (!ret) { |
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pr_err("Failed to mapping hwirq\n"); |
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goto err; |
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} |
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if (!irq) |
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icu_data[0].virq_base = ret; |
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} |
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icu_data[0].nr_irqs = nr_irqs; |
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return 0; |
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err: |
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if (icu_data[0].virq_base) { |
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for (i = 0; i < irq; i++) |
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irq_dispose_mapping(icu_data[0].virq_base + i); |
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} |
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irq_domain_remove(icu_data[0].domain); |
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iounmap(mmp_icu_base); |
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return -EINVAL; |
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} |
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static int __init mmp_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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int ret; |
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ret = mmp_init_bases(node); |
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if (ret < 0) |
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return ret; |
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icu_data[0].conf_enable = mmp_conf.conf_enable; |
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icu_data[0].conf_disable = mmp_conf.conf_disable; |
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icu_data[0].conf_mask = mmp_conf.conf_mask; |
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set_handle_irq(mmp_handle_irq); |
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max_icu_nr = 1; |
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return 0; |
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} |
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IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init); |
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static int __init mmp2_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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int ret; |
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ret = mmp_init_bases(node); |
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if (ret < 0) |
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return ret; |
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icu_data[0].conf_enable = mmp2_conf.conf_enable; |
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icu_data[0].conf_disable = mmp2_conf.conf_disable; |
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icu_data[0].conf_mask = mmp2_conf.conf_mask; |
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set_handle_irq(mmp2_handle_irq); |
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max_icu_nr = 1; |
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return 0; |
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} |
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IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init); |
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static int __init mmp3_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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int ret; |
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mmp_icu2_base = of_iomap(node, 1); |
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if (!mmp_icu2_base) { |
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pr_err("Failed to get interrupt controller register #2\n"); |
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return -ENODEV; |
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} |
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ret = mmp_init_bases(node); |
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if (ret < 0) { |
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iounmap(mmp_icu2_base); |
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return ret; |
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} |
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icu_data[0].conf_enable = mmp3_conf.conf_enable; |
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icu_data[0].conf_disable = mmp3_conf.conf_disable; |
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icu_data[0].conf_mask = mmp3_conf.conf_mask; |
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icu_data[0].conf2_mask = mmp3_conf.conf2_mask; |
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if (!parent) { |
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/* This is the main interrupt controller. */ |
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set_handle_irq(mmp2_handle_irq); |
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} |
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max_icu_nr = 1; |
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return 0; |
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} |
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IRQCHIP_DECLARE(mmp3_intc, "marvell,mmp3-intc", mmp3_of_init); |
|
|
|
static int __init mmp2_mux_of_init(struct device_node *node, |
|
struct device_node *parent) |
|
{ |
|
int i, ret, irq, j = 0; |
|
u32 nr_irqs, mfp_irq; |
|
u32 reg[4]; |
|
|
|
if (!parent) |
|
return -ENODEV; |
|
|
|
i = max_icu_nr; |
|
ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", |
|
&nr_irqs); |
|
if (ret) { |
|
pr_err("Not found mrvl,intc-nr-irqs property\n"); |
|
return -EINVAL; |
|
} |
|
|
|
/* |
|
* For historical reasons, the "regs" property of the |
|
* mrvl,mmp2-mux-intc is not a regular "regs" property containing |
|
* addresses on the parent bus, but offsets from the intc's base. |
|
* That is why we can't use of_address_to_resource() here. |
|
*/ |
|
ret = of_property_read_variable_u32_array(node, "reg", reg, |
|
ARRAY_SIZE(reg), |
|
ARRAY_SIZE(reg)); |
|
if (ret < 0) { |
|
pr_err("Not found reg property\n"); |
|
return -EINVAL; |
|
} |
|
icu_data[i].reg_status = mmp_icu_base + reg[0]; |
|
icu_data[i].reg_mask = mmp_icu_base + reg[2]; |
|
icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); |
|
if (!icu_data[i].cascade_irq) |
|
return -EINVAL; |
|
|
|
icu_data[i].virq_base = 0; |
|
icu_data[i].domain = irq_domain_add_linear(node, nr_irqs, |
|
&mmp_irq_domain_ops, |
|
&icu_data[i]); |
|
for (irq = 0; irq < nr_irqs; irq++) { |
|
ret = irq_create_mapping(icu_data[i].domain, irq); |
|
if (!ret) { |
|
pr_err("Failed to mapping hwirq\n"); |
|
goto err; |
|
} |
|
if (!irq) |
|
icu_data[i].virq_base = ret; |
|
} |
|
icu_data[i].nr_irqs = nr_irqs; |
|
if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", |
|
&mfp_irq)) { |
|
icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base; |
|
icu_data[i].clr_mfp_hwirq = mfp_irq; |
|
} |
|
irq_set_chained_handler(icu_data[i].cascade_irq, |
|
icu_mux_irq_demux); |
|
max_icu_nr++; |
|
return 0; |
|
err: |
|
if (icu_data[i].virq_base) { |
|
for (j = 0; j < irq; j++) |
|
irq_dispose_mapping(icu_data[i].virq_base + j); |
|
} |
|
irq_domain_remove(icu_data[i].domain); |
|
return -EINVAL; |
|
} |
|
IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init); |
|
#endif
|
|
|