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361 lines
9.8 KiB
361 lines
9.8 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Code to handle x86 style IRQs plus some generic interrupt stuff. |
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* |
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* Copyright (C) 1992 Linus Torvalds |
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* Copyright (C) 1994 - 2000 Ralf Baechle |
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*/ |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/of_irq.h> |
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#include <linux/spinlock.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/irq.h> |
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#include <asm/i8259.h> |
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#include <asm/io.h> |
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/* |
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* This is the 'legacy' 8259A Programmable Interrupt Controller, |
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* present in the majority of PC/AT boxes. |
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* plus some generic x86 specific things if generic specifics makes |
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* any sense at all. |
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* this file should become arch/i386/kernel/irq.c when the old irq.c |
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* moves to arch independent land |
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*/ |
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static int i8259A_auto_eoi = -1; |
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DEFINE_RAW_SPINLOCK(i8259A_lock); |
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static void disable_8259A_irq(struct irq_data *d); |
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static void enable_8259A_irq(struct irq_data *d); |
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static void mask_and_ack_8259A(struct irq_data *d); |
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static void init_8259A(int auto_eoi); |
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static int (*i8259_poll)(void) = i8259_irq; |
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static struct irq_chip i8259A_chip = { |
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.name = "XT-PIC", |
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.irq_mask = disable_8259A_irq, |
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.irq_disable = disable_8259A_irq, |
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.irq_unmask = enable_8259A_irq, |
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.irq_mask_ack = mask_and_ack_8259A, |
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}; |
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/* |
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* 8259A PIC functions to handle ISA devices: |
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*/ |
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void i8259_set_poll(int (*poll)(void)) |
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{ |
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i8259_poll = poll; |
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} |
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/* |
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* This contains the irq mask for both 8259A irq controllers, |
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*/ |
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static unsigned int cached_irq_mask = 0xffff; |
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#define cached_master_mask (cached_irq_mask) |
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#define cached_slave_mask (cached_irq_mask >> 8) |
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static void disable_8259A_irq(struct irq_data *d) |
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{ |
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unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; |
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unsigned long flags; |
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mask = 1 << irq; |
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raw_spin_lock_irqsave(&i8259A_lock, flags); |
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cached_irq_mask |= mask; |
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if (irq & 8) |
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outb(cached_slave_mask, PIC_SLAVE_IMR); |
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else |
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outb(cached_master_mask, PIC_MASTER_IMR); |
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raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
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} |
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static void enable_8259A_irq(struct irq_data *d) |
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{ |
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unsigned int mask, irq = d->irq - I8259A_IRQ_BASE; |
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unsigned long flags; |
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mask = ~(1 << irq); |
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raw_spin_lock_irqsave(&i8259A_lock, flags); |
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cached_irq_mask &= mask; |
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if (irq & 8) |
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outb(cached_slave_mask, PIC_SLAVE_IMR); |
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else |
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outb(cached_master_mask, PIC_MASTER_IMR); |
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raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
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} |
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void make_8259A_irq(unsigned int irq) |
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{ |
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disable_irq_nosync(irq); |
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irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq); |
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enable_irq(irq); |
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} |
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/* |
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* This function assumes to be called rarely. Switching between |
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* 8259A registers is slow. |
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* This has to be protected by the irq controller spinlock |
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* before being called. |
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*/ |
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static inline int i8259A_irq_real(unsigned int irq) |
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{ |
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int value; |
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int irqmask = 1 << irq; |
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if (irq < 8) { |
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outb(0x0B, PIC_MASTER_CMD); /* ISR register */ |
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value = inb(PIC_MASTER_CMD) & irqmask; |
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outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */ |
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return value; |
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} |
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outb(0x0B, PIC_SLAVE_CMD); /* ISR register */ |
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value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); |
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outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */ |
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return value; |
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} |
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/* |
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* Careful! The 8259A is a fragile beast, it pretty |
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* much _has_ to be done exactly like this (mask it |
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* first, _then_ send the EOI, and the order of EOI |
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* to the two 8259s is important! |
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*/ |
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static void mask_and_ack_8259A(struct irq_data *d) |
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{ |
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unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; |
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unsigned long flags; |
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irqmask = 1 << irq; |
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raw_spin_lock_irqsave(&i8259A_lock, flags); |
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/* |
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* Lightweight spurious IRQ detection. We do not want |
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* to overdo spurious IRQ handling - it's usually a sign |
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* of hardware problems, so we only do the checks we can |
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* do without slowing down good hardware unnecessarily. |
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* |
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* Note that IRQ7 and IRQ15 (the two spurious IRQs |
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* usually resulting from the 8259A-1|2 PICs) occur |
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* even if the IRQ is masked in the 8259A. Thus we |
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* can check spurious 8259A IRQs without doing the |
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* quite slow i8259A_irq_real() call for every IRQ. |
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* This does not cover 100% of spurious interrupts, |
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* but should be enough to warn the user that there |
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* is something bad going on ... |
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*/ |
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if (cached_irq_mask & irqmask) |
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goto spurious_8259A_irq; |
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cached_irq_mask |= irqmask; |
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handle_real_irq: |
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if (irq & 8) { |
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inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ |
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outb(cached_slave_mask, PIC_SLAVE_IMR); |
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outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ |
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outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ |
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} else { |
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inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ |
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outb(cached_master_mask, PIC_MASTER_IMR); |
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outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */ |
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} |
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raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
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return; |
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spurious_8259A_irq: |
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/* |
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* this is the slow path - should happen rarely. |
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*/ |
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if (i8259A_irq_real(irq)) |
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/* |
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* oops, the IRQ _is_ in service according to the |
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* 8259A - not spurious, go handle it. |
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*/ |
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goto handle_real_irq; |
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{ |
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static int spurious_irq_mask; |
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/* |
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* At this point we can be sure the IRQ is spurious, |
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* lets ACK and report it. [once per IRQ] |
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*/ |
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if (!(spurious_irq_mask & irqmask)) { |
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printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq); |
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spurious_irq_mask |= irqmask; |
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} |
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atomic_inc(&irq_err_count); |
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/* |
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* Theoretically we do not have to handle this IRQ, |
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* but in Linux this does not cause problems and is |
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* simpler for us. |
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*/ |
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goto handle_real_irq; |
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} |
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} |
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static void i8259A_resume(void) |
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{ |
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if (i8259A_auto_eoi >= 0) |
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init_8259A(i8259A_auto_eoi); |
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} |
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static void i8259A_shutdown(void) |
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{ |
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/* Put the i8259A into a quiescent state that |
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* the kernel initialization code can get it |
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* out of. |
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*/ |
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if (i8259A_auto_eoi >= 0) { |
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ |
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ |
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} |
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} |
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static struct syscore_ops i8259_syscore_ops = { |
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.resume = i8259A_resume, |
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.shutdown = i8259A_shutdown, |
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}; |
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static void init_8259A(int auto_eoi) |
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{ |
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unsigned long flags; |
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i8259A_auto_eoi = auto_eoi; |
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raw_spin_lock_irqsave(&i8259A_lock, flags); |
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */ |
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */ |
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/* |
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* outb_p - this has to work on a wide range of PC hardware. |
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*/ |
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outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */ |
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outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */ |
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outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */ |
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if (auto_eoi) /* master does Auto EOI */ |
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outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR); |
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else /* master expects normal EOI */ |
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outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR); |
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outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */ |
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outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */ |
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outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */ |
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outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */ |
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if (auto_eoi) |
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/* |
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* In AEOI mode we just have to mask the interrupt |
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* when acking. |
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*/ |
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i8259A_chip.irq_mask_ack = disable_8259A_irq; |
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else |
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i8259A_chip.irq_mask_ack = mask_and_ack_8259A; |
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udelay(100); /* wait for 8259A to initialize */ |
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outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */ |
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outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */ |
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raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
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} |
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static struct resource pic1_io_resource = { |
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.name = "pic1", |
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.start = PIC_MASTER_CMD, |
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.end = PIC_MASTER_IMR, |
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.flags = IORESOURCE_IO | IORESOURCE_BUSY |
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}; |
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static struct resource pic2_io_resource = { |
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.name = "pic2", |
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.start = PIC_SLAVE_CMD, |
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.end = PIC_SLAVE_IMR, |
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.flags = IORESOURCE_IO | IORESOURCE_BUSY |
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}; |
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static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq, |
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irq_hw_number_t hw) |
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{ |
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irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq); |
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irq_set_probe(virq); |
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return 0; |
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} |
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static const struct irq_domain_ops i8259A_ops = { |
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.map = i8259A_irq_domain_map, |
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.xlate = irq_domain_xlate_onecell, |
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}; |
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/* |
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* On systems with i8259-style interrupt controllers we assume for |
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* driver compatibility reasons interrupts 0 - 15 to be the i8259 |
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* interrupts even if the hardware uses a different interrupt numbering. |
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*/ |
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struct irq_domain * __init __init_i8259_irqs(struct device_node *node) |
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{ |
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/* |
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* PIC_CASCADE_IR is cascade interrupt to second interrupt controller |
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*/ |
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int irq = I8259A_IRQ_BASE + PIC_CASCADE_IR; |
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struct irq_domain *domain; |
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insert_resource(&ioport_resource, &pic1_io_resource); |
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insert_resource(&ioport_resource, &pic2_io_resource); |
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init_8259A(0); |
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domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0, |
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&i8259A_ops, NULL); |
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if (!domain) |
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panic("Failed to add i8259 IRQ domain"); |
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if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade", NULL)) |
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pr_err("Failed to register cascade interrupt\n"); |
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register_syscore_ops(&i8259_syscore_ops); |
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return domain; |
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} |
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void __init init_i8259_irqs(void) |
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{ |
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__init_i8259_irqs(NULL); |
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} |
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static void i8259_irq_dispatch(struct irq_desc *desc) |
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{ |
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struct irq_domain *domain = irq_desc_get_handler_data(desc); |
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int hwirq = i8259_poll(); |
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if (hwirq < 0) |
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return; |
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generic_handle_domain_irq(domain, hwirq); |
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} |
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int __init i8259_of_init(struct device_node *node, struct device_node *parent) |
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{ |
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struct irq_domain *domain; |
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unsigned int parent_irq; |
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domain = __init_i8259_irqs(node); |
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parent_irq = irq_of_parse_and_map(node, 0); |
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if (!parent_irq) { |
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pr_err("Failed to map i8259 parent IRQ\n"); |
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irq_domain_remove(domain); |
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return -ENODEV; |
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} |
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irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch, |
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domain); |
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return 0; |
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} |
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IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);
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