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218 lines
5.8 KiB
218 lines
5.8 KiB
/* |
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* Synopsys DW APB ICTL irqchip driver. |
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* |
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* Sebastian Hesselbarth <[email protected]> |
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* |
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* based on GPL'ed 2.6 kernel sources |
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* (c) Marvell International Ltd. |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/interrupt.h> |
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#define APB_INT_ENABLE_L 0x00 |
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#define APB_INT_ENABLE_H 0x04 |
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#define APB_INT_MASK_L 0x08 |
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#define APB_INT_MASK_H 0x0c |
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#define APB_INT_FINALSTATUS_L 0x30 |
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#define APB_INT_FINALSTATUS_H 0x34 |
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#define APB_INT_BASE_OFFSET 0x04 |
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/* irq domain of the primary interrupt controller. */ |
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static struct irq_domain *dw_apb_ictl_irq_domain; |
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static void __irq_entry dw_apb_ictl_handle_irq(struct pt_regs *regs) |
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{ |
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struct irq_domain *d = dw_apb_ictl_irq_domain; |
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int n; |
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for (n = 0; n < d->revmap_size; n += 32) { |
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); |
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u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); |
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while (stat) { |
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u32 hwirq = ffs(stat) - 1; |
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handle_domain_irq(d, hwirq, regs); |
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stat &= ~BIT(hwirq); |
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} |
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} |
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} |
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static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc) |
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{ |
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struct irq_domain *d = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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int n; |
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chained_irq_enter(chip, desc); |
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for (n = 0; n < d->revmap_size; n += 32) { |
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, n); |
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u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L); |
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while (stat) { |
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u32 hwirq = ffs(stat) - 1; |
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generic_handle_domain_irq(d, gc->irq_base + hwirq); |
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stat &= ~BIT(hwirq); |
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} |
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} |
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chained_irq_exit(chip, desc); |
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} |
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static int dw_apb_ictl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *arg) |
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{ |
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int i, ret; |
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irq_hw_number_t hwirq; |
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unsigned int type = IRQ_TYPE_NONE; |
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struct irq_fwspec *fwspec = arg; |
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ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); |
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if (ret) |
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return ret; |
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for (i = 0; i < nr_irqs; i++) |
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irq_map_generic_chip(domain, virq + i, hwirq + i); |
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return 0; |
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} |
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static const struct irq_domain_ops dw_apb_ictl_irq_domain_ops = { |
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.translate = irq_domain_translate_onecell, |
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.alloc = dw_apb_ictl_irq_domain_alloc, |
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.free = irq_domain_free_irqs_top, |
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}; |
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#ifdef CONFIG_PM |
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static void dw_apb_ictl_resume(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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irq_gc_lock(gc); |
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writel_relaxed(~0, gc->reg_base + ct->regs.enable); |
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writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask); |
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irq_gc_unlock(gc); |
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} |
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#else |
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#define dw_apb_ictl_resume NULL |
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#endif /* CONFIG_PM */ |
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static int __init dw_apb_ictl_init(struct device_node *np, |
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struct device_node *parent) |
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{ |
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const struct irq_domain_ops *domain_ops; |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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struct resource r; |
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struct irq_domain *domain; |
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struct irq_chip_generic *gc; |
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void __iomem *iobase; |
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int ret, nrirqs, parent_irq, i; |
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u32 reg; |
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if (!parent) { |
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/* Used as the primary interrupt controller */ |
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parent_irq = 0; |
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domain_ops = &dw_apb_ictl_irq_domain_ops; |
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} else { |
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/* Map the parent interrupt for the chained handler */ |
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parent_irq = irq_of_parse_and_map(np, 0); |
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if (parent_irq <= 0) { |
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pr_err("%pOF: unable to parse irq\n", np); |
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return -EINVAL; |
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} |
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domain_ops = &irq_generic_chip_ops; |
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} |
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ret = of_address_to_resource(np, 0, &r); |
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if (ret) { |
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pr_err("%pOF: unable to get resource\n", np); |
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return ret; |
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} |
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if (!request_mem_region(r.start, resource_size(&r), np->full_name)) { |
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pr_err("%pOF: unable to request mem region\n", np); |
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return -ENOMEM; |
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} |
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iobase = ioremap(r.start, resource_size(&r)); |
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if (!iobase) { |
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pr_err("%pOF: unable to map resource\n", np); |
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ret = -ENOMEM; |
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goto err_release; |
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} |
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/* |
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* DW IP can be configured to allow 2-64 irqs. We can determine |
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* the number of irqs supported by writing into enable register |
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* and look for bits not set, as corresponding flip-flops will |
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* have been removed by synthesis tool. |
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*/ |
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/* mask and enable all interrupts */ |
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writel_relaxed(~0, iobase + APB_INT_MASK_L); |
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writel_relaxed(~0, iobase + APB_INT_MASK_H); |
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writel_relaxed(~0, iobase + APB_INT_ENABLE_L); |
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writel_relaxed(~0, iobase + APB_INT_ENABLE_H); |
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reg = readl_relaxed(iobase + APB_INT_ENABLE_H); |
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if (reg) |
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nrirqs = 32 + fls(reg); |
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else |
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nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); |
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domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL); |
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if (!domain) { |
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pr_err("%pOF: unable to add irq domain\n", np); |
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ret = -ENOMEM; |
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goto err_unmap; |
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} |
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ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name, |
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handle_level_irq, clr, 0, |
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IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_err("%pOF: unable to alloc irq domain gc\n", np); |
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goto err_unmap; |
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} |
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for (i = 0; i < DIV_ROUND_UP(nrirqs, 32); i++) { |
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gc = irq_get_domain_generic_chip(domain, i * 32); |
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gc->reg_base = iobase + i * APB_INT_BASE_OFFSET; |
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gc->chip_types[0].regs.mask = APB_INT_MASK_L; |
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gc->chip_types[0].regs.enable = APB_INT_ENABLE_L; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; |
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gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume; |
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} |
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if (parent_irq) { |
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irq_set_chained_handler_and_data(parent_irq, |
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dw_apb_ictl_handle_irq_cascaded, domain); |
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} else { |
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dw_apb_ictl_irq_domain = domain; |
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set_handle_irq(dw_apb_ictl_handle_irq); |
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} |
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return 0; |
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err_unmap: |
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iounmap(iobase); |
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err_release: |
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release_mem_region(r.start, resource_size(&r)); |
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return ret; |
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} |
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IRQCHIP_DECLARE(dw_apb_ictl, |
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"snps,dw-apb-ictl", dw_apb_ictl_init);
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