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73 lines
1.7 KiB
73 lines
1.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* perf.h - performance monitor header |
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* |
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* Copyright (C) 2021 Intel Corporation |
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* |
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* Author: Lu Baolu <[email protected]> |
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*/ |
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enum latency_type { |
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DMAR_LATENCY_INV_IOTLB = 0, |
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DMAR_LATENCY_INV_DEVTLB, |
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DMAR_LATENCY_INV_IEC, |
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DMAR_LATENCY_PRQ, |
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DMAR_LATENCY_NUM |
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}; |
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enum latency_count { |
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COUNTS_10e2 = 0, /* < 0.1us */ |
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COUNTS_10e3, /* 0.1us ~ 1us */ |
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COUNTS_10e4, /* 1us ~ 10us */ |
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COUNTS_10e5, /* 10us ~ 100us */ |
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COUNTS_10e6, /* 100us ~ 1ms */ |
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COUNTS_10e7, /* 1ms ~ 10ms */ |
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COUNTS_10e8_plus, /* 10ms and plus*/ |
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COUNTS_MIN, |
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COUNTS_MAX, |
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COUNTS_SUM, |
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COUNTS_NUM |
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}; |
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struct latency_statistic { |
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bool enabled; |
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u64 counter[COUNTS_NUM]; |
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u64 samples; |
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}; |
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#ifdef CONFIG_DMAR_PERF |
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int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type); |
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void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type); |
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bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type); |
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void dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, |
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u64 latency); |
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int dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size); |
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#else |
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static inline int |
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dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type) |
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{ |
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return -EINVAL; |
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} |
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static inline void |
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dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type) |
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{ |
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} |
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static inline bool |
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dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type) |
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{ |
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return false; |
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} |
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static inline void |
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dmar_latency_update(struct intel_iommu *iommu, enum latency_type type, u64 latency) |
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{ |
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} |
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static inline int |
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dmar_latency_snapshot(struct intel_iommu *iommu, char *str, size_t size) |
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{ |
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return 0; |
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} |
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#endif /* CONFIG_DMAR_PERF */
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