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631 lines
16 KiB
631 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Analog Devices ADF4371 SPI Wideband Synthesizer driver |
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* |
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* Copyright 2019 Analog Devices Inc. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/gcd.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/regmap.h> |
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#include <linux/sysfs.h> |
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#include <linux/spi/spi.h> |
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#include <linux/iio/iio.h> |
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|
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/* Registers address macro */ |
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#define ADF4371_REG(x) (x) |
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/* ADF4371_REG0 */ |
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#define ADF4371_ADDR_ASC_MSK BIT(2) |
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#define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x) |
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#define ADF4371_ADDR_ASC_R_MSK BIT(5) |
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#define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x) |
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#define ADF4371_RESET_CMD 0x81 |
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|
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/* ADF4371_REG17 */ |
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#define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1) |
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#define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x) |
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#define ADF4371_FRAC1WORD_MSK BIT(0) |
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#define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x) |
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/* ADF4371_REG18 */ |
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#define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0) |
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#define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x) |
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/* ADF4371_REG1A */ |
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#define ADF4371_MOD2WORD_MSK GENMASK(5, 0) |
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#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x) |
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/* ADF4371_REG24 */ |
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#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) |
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#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) |
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/* ADF4371_REG25 */ |
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#define ADF4371_MUTE_LD_MSK BIT(7) |
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#define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x) |
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/* ADF4371_REG32 */ |
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#define ADF4371_TIMEOUT_MSK GENMASK(1, 0) |
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#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) |
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/* ADF4371_REG34 */ |
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#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0) |
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#define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x) |
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|
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/* Specifications */ |
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#define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */ |
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#define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */ |
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#define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */ |
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#define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */ |
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#define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */ |
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#define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */ |
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#define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */ |
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#define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */ |
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#define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */ |
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#define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */ |
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/* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */ |
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#define ADF4371_MODULUS1 33554432ULL |
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/* MOD2 is the programmable, 14-bit auxiliary fractional modulus */ |
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#define ADF4371_MAX_MODULUS2 BIT(14) |
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#define ADF4371_CHECK_RANGE(freq, range) \ |
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((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range)) |
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enum { |
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ADF4371_FREQ, |
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ADF4371_POWER_DOWN, |
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ADF4371_CHANNEL_NAME |
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}; |
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enum { |
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ADF4371_CH_RF8, |
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ADF4371_CH_RFAUX8, |
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ADF4371_CH_RF16, |
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ADF4371_CH_RF32 |
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}; |
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enum adf4371_variant { |
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ADF4371, |
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ADF4372 |
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}; |
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struct adf4371_pwrdown { |
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unsigned int reg; |
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unsigned int bit; |
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}; |
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static const char * const adf4371_ch_names[] = { |
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"RF8x", "RFAUX8x", "RF16x", "RF32x" |
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}; |
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static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = { |
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[ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 }, |
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[ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 }, |
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[ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 }, |
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[ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 }, |
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}; |
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static const struct reg_sequence adf4371_reg_defaults[] = { |
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{ ADF4371_REG(0x0), 0x18 }, |
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{ ADF4371_REG(0x12), 0x40 }, |
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{ ADF4371_REG(0x1E), 0x48 }, |
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{ ADF4371_REG(0x20), 0x14 }, |
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{ ADF4371_REG(0x22), 0x00 }, |
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{ ADF4371_REG(0x23), 0x00 }, |
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{ ADF4371_REG(0x24), 0x80 }, |
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{ ADF4371_REG(0x25), 0x07 }, |
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{ ADF4371_REG(0x27), 0xC5 }, |
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{ ADF4371_REG(0x28), 0x83 }, |
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{ ADF4371_REG(0x2C), 0x44 }, |
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{ ADF4371_REG(0x2D), 0x11 }, |
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{ ADF4371_REG(0x2E), 0x12 }, |
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{ ADF4371_REG(0x2F), 0x94 }, |
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{ ADF4371_REG(0x32), 0x04 }, |
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{ ADF4371_REG(0x35), 0xFA }, |
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{ ADF4371_REG(0x36), 0x30 }, |
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{ ADF4371_REG(0x39), 0x07 }, |
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{ ADF4371_REG(0x3A), 0x55 }, |
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{ ADF4371_REG(0x3E), 0x0C }, |
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{ ADF4371_REG(0x3F), 0x80 }, |
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{ ADF4371_REG(0x40), 0x50 }, |
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{ ADF4371_REG(0x41), 0x28 }, |
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{ ADF4371_REG(0x47), 0xC0 }, |
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{ ADF4371_REG(0x52), 0xF4 }, |
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{ ADF4371_REG(0x70), 0x03 }, |
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{ ADF4371_REG(0x71), 0x60 }, |
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{ ADF4371_REG(0x72), 0x32 }, |
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}; |
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static const struct regmap_config adf4371_regmap_config = { |
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.reg_bits = 16, |
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.val_bits = 8, |
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.read_flag_mask = BIT(7), |
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}; |
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struct adf4371_chip_info { |
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unsigned int num_channels; |
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const struct iio_chan_spec *channels; |
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}; |
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struct adf4371_state { |
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struct spi_device *spi; |
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struct regmap *regmap; |
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struct clk *clkin; |
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/* |
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* Lock for accessing device registers. Some operations require |
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* multiple consecutive R/W operations, during which the device |
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* shouldn't be interrupted. The buffers are also shared across |
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* all operations so need to be protected on stand alone reads and |
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* writes. |
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*/ |
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struct mutex lock; |
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const struct adf4371_chip_info *chip_info; |
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unsigned long clkin_freq; |
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unsigned long fpfd; |
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unsigned int integer; |
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unsigned int fract1; |
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unsigned int fract2; |
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unsigned int mod2; |
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unsigned int rf_div_sel; |
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unsigned int ref_div_factor; |
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u8 buf[10] ____cacheline_aligned; |
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}; |
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static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st, |
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u32 channel) |
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{ |
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unsigned long long val, tmp; |
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unsigned int ref_div_sel; |
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val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd; |
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tmp = (u64)st->fract2 * st->fpfd; |
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do_div(tmp, st->mod2); |
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val += tmp + ADF4371_MODULUS1 / 2; |
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if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8) |
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ref_div_sel = st->rf_div_sel; |
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else |
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ref_div_sel = 0; |
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do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel)); |
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if (channel == ADF4371_CH_RF16) |
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val <<= 1; |
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else if (channel == ADF4371_CH_RF32) |
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val <<= 2; |
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return val; |
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} |
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static void adf4371_pll_fract_n_compute(unsigned long long vco, |
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unsigned long long pfd, |
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unsigned int *integer, |
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unsigned int *fract1, |
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unsigned int *fract2, |
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unsigned int *mod2) |
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{ |
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unsigned long long tmp; |
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u32 gcd_div; |
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tmp = do_div(vco, pfd); |
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tmp = tmp * ADF4371_MODULUS1; |
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*fract2 = do_div(tmp, pfd); |
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*integer = vco; |
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*fract1 = tmp; |
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*mod2 = pfd; |
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while (*mod2 > ADF4371_MAX_MODULUS2) { |
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*mod2 >>= 1; |
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*fract2 >>= 1; |
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} |
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gcd_div = gcd(*fract2, *mod2); |
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*mod2 /= gcd_div; |
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*fract2 /= gcd_div; |
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} |
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static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq, |
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unsigned int channel) |
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{ |
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u32 cp_bleed; |
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u8 int_mode = 0; |
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int ret; |
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switch (channel) { |
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case ADF4371_CH_RF8: |
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case ADF4371_CH_RFAUX8: |
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if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ)) |
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return -EINVAL; |
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st->rf_div_sel = 0; |
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while (freq < ADF4371_MIN_VCO_FREQ) { |
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freq <<= 1; |
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st->rf_div_sel++; |
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} |
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break; |
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case ADF4371_CH_RF16: |
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/* ADF4371 RF16 8000...16000 MHz */ |
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if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ)) |
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return -EINVAL; |
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freq >>= 1; |
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break; |
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case ADF4371_CH_RF32: |
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/* ADF4371 RF32 16000...32000 MHz */ |
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if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ)) |
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return -EINVAL; |
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freq >>= 2; |
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break; |
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default: |
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return -EINVAL; |
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} |
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adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1, |
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&st->fract2, &st->mod2); |
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st->buf[0] = st->integer >> 8; |
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st->buf[1] = 0x40; /* REG12 default */ |
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st->buf[2] = 0x00; |
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st->buf[3] = st->fract1 & 0xFF; |
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st->buf[4] = st->fract1 >> 8; |
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st->buf[5] = st->fract1 >> 16; |
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st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) | |
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ADF4371_FRAC1WORD(st->fract1 >> 24); |
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st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7); |
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st->buf[8] = st->mod2 & 0xFF; |
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st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8); |
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ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10); |
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if (ret < 0) |
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return ret; |
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/* |
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* The R counter allows the input reference frequency to be |
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* divided down to produce the reference clock to the PFD |
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*/ |
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ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor); |
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if (ret < 0) |
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return ret; |
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ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24), |
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ADF4371_RF_DIV_SEL_MSK, |
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ADF4371_RF_DIV_SEL(st->rf_div_sel)); |
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if (ret < 0) |
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return ret; |
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cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375); |
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cp_bleed = clamp(cp_bleed, 1U, 255U); |
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ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed); |
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if (ret < 0) |
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return ret; |
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/* |
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* Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0), |
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* and set to 0 when in FRAC mode. |
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*/ |
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if (st->fract1 == 0 && st->fract2 == 0) |
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int_mode = 0x01; |
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ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode); |
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if (ret < 0) |
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return ret; |
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return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF); |
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} |
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static ssize_t adf4371_read(struct iio_dev *indio_dev, |
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uintptr_t private, |
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const struct iio_chan_spec *chan, |
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char *buf) |
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{ |
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struct adf4371_state *st = iio_priv(indio_dev); |
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unsigned long long val = 0; |
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unsigned int readval, reg, bit; |
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int ret; |
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switch ((u32)private) { |
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case ADF4371_FREQ: |
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val = adf4371_pll_fract_n_get_rate(st, chan->channel); |
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ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval); |
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if (ret < 0) |
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break; |
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if (readval == 0x00) { |
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dev_dbg(&st->spi->dev, "PLL un-locked\n"); |
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ret = -EBUSY; |
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} |
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break; |
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case ADF4371_POWER_DOWN: |
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reg = adf4371_pwrdown_ch[chan->channel].reg; |
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bit = adf4371_pwrdown_ch[chan->channel].bit; |
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ret = regmap_read(st->regmap, reg, &readval); |
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if (ret < 0) |
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break; |
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val = !(readval & BIT(bit)); |
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break; |
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case ADF4371_CHANNEL_NAME: |
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return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]); |
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default: |
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ret = -EINVAL; |
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val = 0; |
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break; |
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} |
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return ret < 0 ? ret : sprintf(buf, "%llu\n", val); |
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} |
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static ssize_t adf4371_write(struct iio_dev *indio_dev, |
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uintptr_t private, |
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const struct iio_chan_spec *chan, |
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const char *buf, size_t len) |
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{ |
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struct adf4371_state *st = iio_priv(indio_dev); |
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unsigned long long freq; |
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bool power_down; |
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unsigned int bit, readval, reg; |
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int ret; |
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mutex_lock(&st->lock); |
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switch ((u32)private) { |
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case ADF4371_FREQ: |
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ret = kstrtoull(buf, 10, &freq); |
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if (ret) |
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break; |
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ret = adf4371_set_freq(st, freq, chan->channel); |
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break; |
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case ADF4371_POWER_DOWN: |
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ret = kstrtobool(buf, &power_down); |
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if (ret) |
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break; |
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reg = adf4371_pwrdown_ch[chan->channel].reg; |
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bit = adf4371_pwrdown_ch[chan->channel].bit; |
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ret = regmap_read(st->regmap, reg, &readval); |
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if (ret < 0) |
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break; |
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|
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readval &= ~BIT(bit); |
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readval |= (!power_down << bit); |
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|
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ret = regmap_write(st->regmap, reg, readval); |
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break; |
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default: |
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ret = -EINVAL; |
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break; |
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} |
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mutex_unlock(&st->lock); |
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|
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return ret ? ret : len; |
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} |
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|
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#define _ADF4371_EXT_INFO(_name, _ident) { \ |
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.name = _name, \ |
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.read = adf4371_read, \ |
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.write = adf4371_write, \ |
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.private = _ident, \ |
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.shared = IIO_SEPARATE, \ |
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} |
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|
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static const struct iio_chan_spec_ext_info adf4371_ext_info[] = { |
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/* |
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* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are |
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* values > 2^32 in order to support the entire frequency range |
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* in Hz. Using scale is a bit ugly. |
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*/ |
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_ADF4371_EXT_INFO("frequency", ADF4371_FREQ), |
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_ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN), |
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_ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME), |
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{ }, |
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}; |
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|
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#define ADF4371_CHANNEL(index) { \ |
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.type = IIO_ALTVOLTAGE, \ |
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.output = 1, \ |
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.channel = index, \ |
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.ext_info = adf4371_ext_info, \ |
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.indexed = 1, \ |
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} |
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|
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static const struct iio_chan_spec adf4371_chan[] = { |
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ADF4371_CHANNEL(ADF4371_CH_RF8), |
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ADF4371_CHANNEL(ADF4371_CH_RFAUX8), |
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ADF4371_CHANNEL(ADF4371_CH_RF16), |
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ADF4371_CHANNEL(ADF4371_CH_RF32), |
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}; |
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|
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static const struct adf4371_chip_info adf4371_chip_info[] = { |
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[ADF4371] = { |
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.channels = adf4371_chan, |
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.num_channels = 4, |
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}, |
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[ADF4372] = { |
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.channels = adf4371_chan, |
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.num_channels = 3, |
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} |
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}; |
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|
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static int adf4371_reg_access(struct iio_dev *indio_dev, |
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unsigned int reg, |
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unsigned int writeval, |
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unsigned int *readval) |
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{ |
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struct adf4371_state *st = iio_priv(indio_dev); |
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|
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if (readval) |
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return regmap_read(st->regmap, reg, readval); |
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else |
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return regmap_write(st->regmap, reg, writeval); |
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} |
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|
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static const struct iio_info adf4371_info = { |
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.debugfs_reg_access = &adf4371_reg_access, |
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}; |
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|
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static int adf4371_setup(struct adf4371_state *st) |
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{ |
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unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1; |
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unsigned int vco_band_div, tmp; |
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int ret; |
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|
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/* Perform a software reset */ |
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ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD); |
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if (ret < 0) |
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return ret; |
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|
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ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults, |
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ARRAY_SIZE(adf4371_reg_defaults)); |
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if (ret < 0) |
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return ret; |
|
|
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/* Mute to Lock Detect */ |
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if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) { |
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ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25), |
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ADF4371_MUTE_LD_MSK, |
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ADF4371_MUTE_LD(1)); |
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if (ret < 0) |
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return ret; |
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} |
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|
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/* Set address in ascending order, so the bulk_write() will work */ |
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ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0), |
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ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK, |
|
ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1)); |
|
if (ret < 0) |
|
return ret; |
|
/* |
|
* Calculate and maximize PFD frequency |
|
* fPFD = REFIN × ((1 + D)/(R × (1 + T))) |
|
* Where D is the REFIN doubler bit, T is the reference divide by 2, |
|
* R is the reference division factor |
|
* TODO: it is assumed D and T equal 0. |
|
*/ |
|
do { |
|
st->ref_div_factor++; |
|
st->fpfd = st->clkin_freq / st->ref_div_factor; |
|
} while (st->fpfd > ADF4371_MAX_FREQ_PFD); |
|
|
|
/* Calculate Timeouts */ |
|
vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U); |
|
|
|
tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U); |
|
do { |
|
timeout++; |
|
if (timeout > 1023) { |
|
timeout = 2; |
|
synth_timeout++; |
|
} |
|
} while (synth_timeout * 1024 + timeout <= 20 * tmp); |
|
|
|
do { |
|
vco_alc_timeout++; |
|
} while (vco_alc_timeout * 1024 - timeout <= 50 * tmp); |
|
|
|
st->buf[0] = vco_band_div; |
|
st->buf[1] = timeout & 0xFF; |
|
st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04; |
|
st->buf[3] = synth_timeout; |
|
st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout); |
|
|
|
return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5); |
|
} |
|
|
|
static void adf4371_clk_disable(void *data) |
|
{ |
|
struct adf4371_state *st = data; |
|
|
|
clk_disable_unprepare(st->clkin); |
|
} |
|
|
|
static int adf4371_probe(struct spi_device *spi) |
|
{ |
|
const struct spi_device_id *id = spi_get_device_id(spi); |
|
struct iio_dev *indio_dev; |
|
struct adf4371_state *st; |
|
struct regmap *regmap; |
|
int ret; |
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
|
if (!indio_dev) |
|
return -ENOMEM; |
|
|
|
regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config); |
|
if (IS_ERR(regmap)) { |
|
dev_err(&spi->dev, "Error initializing spi regmap: %ld\n", |
|
PTR_ERR(regmap)); |
|
return PTR_ERR(regmap); |
|
} |
|
|
|
st = iio_priv(indio_dev); |
|
spi_set_drvdata(spi, indio_dev); |
|
st->spi = spi; |
|
st->regmap = regmap; |
|
mutex_init(&st->lock); |
|
|
|
st->chip_info = &adf4371_chip_info[id->driver_data]; |
|
indio_dev->name = id->name; |
|
indio_dev->info = &adf4371_info; |
|
indio_dev->modes = INDIO_DIRECT_MODE; |
|
indio_dev->channels = st->chip_info->channels; |
|
indio_dev->num_channels = st->chip_info->num_channels; |
|
|
|
st->clkin = devm_clk_get(&spi->dev, "clkin"); |
|
if (IS_ERR(st->clkin)) |
|
return PTR_ERR(st->clkin); |
|
|
|
ret = clk_prepare_enable(st->clkin); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = devm_add_action_or_reset(&spi->dev, adf4371_clk_disable, st); |
|
if (ret) |
|
return ret; |
|
|
|
st->clkin_freq = clk_get_rate(st->clkin); |
|
|
|
ret = adf4371_setup(st); |
|
if (ret < 0) { |
|
dev_err(&spi->dev, "ADF4371 setup failed\n"); |
|
return ret; |
|
} |
|
|
|
return devm_iio_device_register(&spi->dev, indio_dev); |
|
} |
|
|
|
static const struct spi_device_id adf4371_id_table[] = { |
|
{ "adf4371", ADF4371 }, |
|
{ "adf4372", ADF4372 }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(spi, adf4371_id_table); |
|
|
|
static const struct of_device_id adf4371_of_match[] = { |
|
{ .compatible = "adi,adf4371" }, |
|
{ .compatible = "adi,adf4372" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, adf4371_of_match); |
|
|
|
static struct spi_driver adf4371_driver = { |
|
.driver = { |
|
.name = "adf4371", |
|
.of_match_table = adf4371_of_match, |
|
}, |
|
.probe = adf4371_probe, |
|
.id_table = adf4371_id_table, |
|
}; |
|
module_spi_driver(adf4371_driver); |
|
|
|
MODULE_AUTHOR("Stefan Popa <[email protected]>"); |
|
MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL"); |
|
MODULE_LICENSE("GPL");
|
|
|