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182 lines
4.9 KiB
182 lines
4.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2000-2002 Andre Hedrick <[email protected]> |
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* Copyright (C) 2006-2007 MontaVista Software, Inc. <[email protected]> |
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* |
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* This is a look-alike variation of the ICH0 PIIX4 Ultra-66, |
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* but this keeps the ISA-Bridge and slots alive. |
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* |
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*/ |
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#include <linux/types.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/ide.h> |
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#include <linux/init.h> |
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#define DRV_NAME "slc90e66" |
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static DEFINE_SPINLOCK(slc90e66_lock); |
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static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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int is_slave = drive->dn & 1; |
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int master_port = hwif->channel ? 0x42 : 0x40; |
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int slave_port = 0x44; |
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unsigned long flags; |
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u16 master_data; |
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u8 slave_data; |
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int control = 0; |
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const u8 pio = drive->pio_mode - XFER_PIO_0; |
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/* ISP RTC */ |
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static const u8 timings[][2] = { |
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{ 0, 0 }, |
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{ 0, 0 }, |
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{ 1, 0 }, |
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{ 2, 1 }, |
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{ 2, 3 }, }; |
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spin_lock_irqsave(&slc90e66_lock, flags); |
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pci_read_config_word(dev, master_port, &master_data); |
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if (pio > 1) |
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control |= 1; /* Programmable timing on */ |
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if (drive->media == ide_disk) |
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control |= 4; /* Prefetch, post write */ |
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if (ide_pio_need_iordy(drive, pio)) |
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control |= 2; /* IORDY */ |
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if (is_slave) { |
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master_data |= 0x4000; |
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master_data &= ~0x0070; |
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if (pio > 1) { |
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/* Set PPE, IE and TIME */ |
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master_data |= control << 4; |
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} |
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pci_read_config_byte(dev, slave_port, &slave_data); |
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slave_data &= hwif->channel ? 0x0f : 0xf0; |
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << |
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(hwif->channel ? 4 : 0); |
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} else { |
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master_data &= ~0x3307; |
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if (pio > 1) { |
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/* enable PPE, IE and TIME */ |
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master_data |= control; |
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} |
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master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); |
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} |
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pci_write_config_word(dev, master_port, master_data); |
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if (is_slave) |
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pci_write_config_byte(dev, slave_port, slave_data); |
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spin_unlock_irqrestore(&slc90e66_lock, flags); |
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} |
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static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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u8 maslave = hwif->channel ? 0x42 : 0x40; |
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int sitre = 0, a_speed = 7 << (drive->dn * 4); |
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int u_speed = 0, u_flag = 1 << drive->dn; |
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u16 reg4042, reg44, reg48, reg4a; |
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const u8 speed = drive->dma_mode; |
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pci_read_config_word(dev, maslave, ®4042); |
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sitre = (reg4042 & 0x4000) ? 1 : 0; |
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pci_read_config_word(dev, 0x44, ®44); |
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pci_read_config_word(dev, 0x48, ®48); |
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pci_read_config_word(dev, 0x4a, ®4a); |
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if (speed >= XFER_UDMA_0) { |
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u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4); |
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if (!(reg48 & u_flag)) |
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pci_write_config_word(dev, 0x48, reg48|u_flag); |
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if ((reg4a & a_speed) != u_speed) { |
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); |
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pci_read_config_word(dev, 0x4a, ®4a); |
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pci_write_config_word(dev, 0x4a, reg4a|u_speed); |
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} |
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} else { |
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const u8 mwdma_to_pio[] = { 0, 3, 4 }; |
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if (reg48 & u_flag) |
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pci_write_config_word(dev, 0x48, reg48 & ~u_flag); |
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if (reg4a & a_speed) |
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pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); |
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if (speed >= XFER_MW_DMA_0) |
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drive->pio_mode = |
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mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0; |
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else |
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drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */ |
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slc90e66_set_pio_mode(hwif, drive); |
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} |
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} |
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static u8 slc90e66_cable_detect(ide_hwif_t *hwif) |
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{ |
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struct pci_dev *dev = to_pci_dev(hwif->dev); |
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u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02; |
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pci_read_config_byte(dev, 0x47, ®47); |
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/* bit[0(1)]: 0:80, 1:40 */ |
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return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80; |
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} |
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static const struct ide_port_ops slc90e66_port_ops = { |
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.set_pio_mode = slc90e66_set_pio_mode, |
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.set_dma_mode = slc90e66_set_dma_mode, |
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.cable_detect = slc90e66_cable_detect, |
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}; |
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static const struct ide_port_info slc90e66_chipset = { |
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.name = DRV_NAME, |
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.enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} }, |
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.port_ops = &slc90e66_port_ops, |
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.pio_mask = ATA_PIO4, |
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.swdma_mask = ATA_SWDMA2_ONLY, |
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.mwdma_mask = ATA_MWDMA12_ONLY, |
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.udma_mask = ATA_UDMA4, |
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}; |
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static int slc90e66_init_one(struct pci_dev *dev, |
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const struct pci_device_id *id) |
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{ |
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return ide_pci_init_one(dev, &slc90e66_chipset, NULL); |
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} |
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static const struct pci_device_id slc90e66_pci_tbl[] = { |
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{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 }, |
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{ 0, }, |
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}; |
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MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl); |
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static struct pci_driver slc90e66_pci_driver = { |
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.name = "SLC90e66_IDE", |
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.id_table = slc90e66_pci_tbl, |
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.probe = slc90e66_init_one, |
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.remove = ide_pci_remove, |
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.suspend = ide_pci_suspend, |
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.resume = ide_pci_resume, |
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}; |
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static int __init slc90e66_ide_init(void) |
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{ |
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return ide_pci_register_driver(&slc90e66_pci_driver); |
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} |
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static void __exit slc90e66_ide_exit(void) |
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{ |
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pci_unregister_driver(&slc90e66_pci_driver); |
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} |
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module_init(slc90e66_ide_init); |
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module_exit(slc90e66_ide_exit); |
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MODULE_AUTHOR("Andre Hedrick"); |
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MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE"); |
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MODULE_LICENSE("GPL");
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